From dffe85cd687754e6ef963c226defd6e712f2ed28 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 15:40:35 +0800 Subject: [PATCH 01/22] align enum of adccommon_h50 with adccommon_h5 --- data/registers/adccommon_h50.yaml | 82 +++++++++++++++++++++++++------ 1 file changed, 66 insertions(+), 16 deletions(-) diff --git a/data/registers/adccommon_h50.yaml b/data/registers/adccommon_h50.yaml index 2d14a37..b30aabb 100644 --- a/data/registers/adccommon_h50.yaml +++ b/data/registers/adccommon_h50.yaml @@ -16,11 +16,9 @@ block/ADC_COMMON: - name: IPDR description: identification register byte_offset: 248 - fieldset: IPDR - name: SIDR description: size identification register byte_offset: 252 - fieldset: SIDR fieldset/CCR: description: common control register fields: @@ -28,10 +26,12 @@ fieldset/CCR: description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).' bit_offset: 16 bit_size: 2 + enum: CKMODE - name: PRESC description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.' bit_offset: 18 bit_size: 4 + enum: PRESC - name: VREFEN description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel bit_offset: 22 @@ -63,6 +63,7 @@ fieldset/HWCFGR0: description: Idle value for non-selected channels bit_offset: 12 bit_size: 4 + enum: IDLEVALUE fieldset/VERR: description: version register fields: @@ -74,17 +75,66 @@ fieldset/VERR: description: Major revision These bits returns the ADC IP major revision bit_offset: 4 bit_size: 4 -fieldset/IPDR: - description: identification register - fields: - - name: ID - description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.' - bit_offset: 0 - bit_size: 32 -fieldset/SIDR: - description: size identification register - fields: - - name: SID - description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.' - bit_offset: 0 - bit_size: 32 +enum/CKMODE: + bit_size: 2 + variants: + - name: Asynchronous + description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock + value: 0 + - name: SyncDiv1 + description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck + value: 1 + - name: SyncDiv2 + description: Use AHB clock rcc_hclk3 divided by 2 + value: 2 + - name: SyncDiv4 + description: Use AHB clock rcc_hclk3 divided by 4 + value: 3 +enum/IDLEVALUE: + bit_size: 4 + variants: + - name: H13 + description: Dummy channel selection is 0x13 + value: 0 + - name: H1F + description: Dummy channel selection is 0x1F + value: 1 +enum/PRESC: + bit_size: 4 + variants: + - name: Div1 + description: adc_ker_ck_input not divided + value: 0 + - name: Div2 + description: adc_ker_ck_input divided by 2 + value: 1 + - name: Div4 + description: adc_ker_ck_input divided by 4 + value: 2 + - name: Div6 + description: adc_ker_ck_input divided by 6 + value: 3 + - name: Div8 + description: adc_ker_ck_input divided by 8 + value: 4 + - name: Div10 + description: adc_ker_ck_input divided by 10 + value: 5 + - name: Div12 + description: adc_ker_ck_input divided by 12 + value: 6 + - name: Div16 + description: adc_ker_ck_input divided by 16 + value: 7 + - name: Div32 + description: adc_ker_ck_input divided by 32 + value: 8 + - name: Div64 + description: adc_ker_ck_input divided by 64 + value: 9 + - name: Div128 + description: adc_ker_ck_input divided by 128 + value: 10 + - name: Div256 + description: adc_ker_ck_input divided by 256 + value: 11 From de9eb01e709593cd465f46a0c4d97475958d7982 Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Sat, 24 Feb 2024 16:45:16 -0500 Subject: [PATCH 02/22] Correct 'CRYPT' to 'CRYP' in RCC. --- data/registers/rcc_h7ab.yaml | 12 ++++++------ data/registers/rcc_h7rm0433.yaml | 20 ++++++++++---------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 96512be..b358ba2 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -345,8 +345,8 @@ fieldset/AHB2ENR: description: DCMI peripheral clock bit_offset: 0 bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable + - name: CRYPEN + description: CRYP peripheral clock enable bit_offset: 4 bit_size: 1 - name: HASHEN @@ -392,8 +392,8 @@ fieldset/AHB2LPENR: description: DCMI peripheral clock enable during csleep mode bit_offset: 0 bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode + - name: CRYPLPEN + description: CRYP peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - name: HASHLPEN @@ -439,8 +439,8 @@ fieldset/AHB2RSTR: description: DCMI block reset bit_offset: 0 bit_size: 1 - - name: CRYPTRST - description: Cryptography block reset + - name: CRYPRST + description: CRYPography block reset bit_offset: 4 bit_size: 1 - name: HASHRST diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index f3e4b7b..f8b99fd 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -425,8 +425,8 @@ fieldset/AHB2ENR: description: DCMI peripheral clock bit_offset: 0 bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable + - name: CRYPEN + description: CRYP peripheral clock enable bit_offset: 4 bit_size: 1 - name: HASHEN @@ -468,8 +468,8 @@ fieldset/AHB2LPENR: description: DCMI peripheral clock enable during csleep mode bit_offset: 0 bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode + - name: CRYPLPEN + description: CRYP peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - name: HASHLPEN @@ -511,8 +511,8 @@ fieldset/AHB2RSTR: description: DCMI block reset bit_offset: 0 bit_size: 1 - - name: CRYPTRST - description: Cryptography block reset + - name: CRYPRST + description: CRYPography block reset bit_offset: 4 bit_size: 1 - name: HASHRST @@ -1872,8 +1872,8 @@ fieldset/C1_AHB2ENR: description: DCMI peripheral clock bit_offset: 0 bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable + - name: CRYPEN + description: CRYP peripheral clock enable bit_offset: 4 bit_size: 1 - name: HASHEN @@ -1907,8 +1907,8 @@ fieldset/C1_AHB2LPENR: description: DCMI peripheral clock enable during csleep mode bit_offset: 0 bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode + - name: CRYPLPEN + description: CRYP peripheral clock enable during CSleep mode bit_offset: 4 bit_size: 1 - name: HASHLPEN From 39b513b598d7945c7275d1a020153d4e9c165b6e Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:14:56 +0800 Subject: [PATCH 03/22] rename aes_u5 to aes_v3a --- data/registers/{aes_u5.yaml => aes_v3a.yaml} | 0 stm32-data-gen/src/chips.rs | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename data/registers/{aes_u5.yaml => aes_v3a.yaml} (100%) diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_v3a.yaml similarity index 100% rename from data/registers/aes_u5.yaml rename to data/registers/aes_v3a.yaml diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e6de9f0..20b5520 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -152,9 +152,9 @@ impl PeriMatcher { ("STM32L1.*:AES:.*", ("aes", "v1", "AES")), ("STM32L4.*:AES:.*", ("aes", "v1", "AES")), ("STM32L5.*:AES:.*", ("aes", "v2", "AES")), - ("STM32U5.*:AES:.*", ("aes", "u5", "AES")), ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), + ("STM32U5.*:AES:.*", ("aes", "v3a", "AES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 2c6cd074ef325278197e798bd21edf02809699b8 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:27:17 +0800 Subject: [PATCH 04/22] concate `CHMOD` field into one --- data/registers/aes_v3a.yaml | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/data/registers/aes_v3a.yaml b/data/registers/aes_v3a.yaml index e46fc54..bbe75a7 100644 --- a/data/registers/aes_v3a.yaml +++ b/data/registers/aes_v3a.yaml @@ -74,10 +74,15 @@ fieldset/CR: bit_offset: 3 bit_size: 2 enum: MODE - - name: CHMOD10 - description: Chaining mode bit1 bit0 - bit_offset: 5 - bit_size: 2 + - name: CHMOD + description: Chaining mode selection + bit_offset: + - start: 5 + end: 6 + - start: 16 + end: 16 + bit_size: 3 + enum: CHMOD - name: DMAINEN description: Enable DMA management of data input phase bit_offset: 11 @@ -91,10 +96,6 @@ fieldset/CR: bit_offset: 13 bit_size: 2 enum: GCMPH - - name: CHMOD2 - description: Chaining mode bit2 - bit_offset: 16 - bit_size: 1 - name: KEYSIZE description: Key size selection bit_offset: 18 @@ -256,3 +257,21 @@ enum/MODE: - name: Mode3 description: Decryption value: 2 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 From 3f975e6217e692846279740a0b0863cd3fd2811a Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:33:58 +0800 Subject: [PATCH 05/22] branch from v3a to v3b --- data/registers/aes_v3b.yaml | 277 ++++++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) create mode 100644 data/registers/aes_v3b.yaml diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml new file mode 100644 index 0000000..bbe75a7 --- /dev/null +++ b/data/registers/aes_v3b.yaml @@ -0,0 +1,277 @@ +block/AES: + description: Advanced encryption standard hardware accelerator + items: + - name: CR + description: Control register + byte_offset: 0 + fieldset: CR + - name: SR + description: Status register + byte_offset: 4 + fieldset: SR + - name: DINR + description: Data input register + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: Data output register + byte_offset: 12 + fieldset: DOUTR + - name: KEYR + description: Key register + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 + byte_offset: 16 + fieldset: KEYR + - name: IVR + description: Initialization vector register + array: + len: 4 + stride: 4 + byte_offset: 32 + fieldset: IVR + - name: SUSPR + description: Suspend register + array: + len: 8 + stride: 4 + byte_offset: 64 + fieldset: SUSPR + - name: IER + description: interrupt enable register + byte_offset: 768 + fieldset: IER + - name: ISR + description: interrupt status register + byte_offset: 772 + fieldset: ISR + - name: ICR + description: interrupt clear register + byte_offset: 776 + fieldset: ICR +fieldset/CR: + description: Control register + fields: + - name: EN + description: AES enable + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: Data type selection + bit_offset: 1 + bit_size: 2 + enum: DATATYPE + - name: MODE + description: Operating mode + bit_offset: 3 + bit_size: 2 + enum: MODE + - name: CHMOD + description: Chaining mode selection + bit_offset: + - start: 5 + end: 6 + - start: 16 + end: 16 + bit_size: 3 + enum: CHMOD + - name: DMAINEN + description: Enable DMA management of data input phase + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: Enable DMA management of data output phase + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: GCM or CCM phase selection + bit_offset: 13 + bit_size: 2 + enum: GCMPH + - name: KEYSIZE + description: Key size selection + bit_offset: 18 + bit_size: 1 + - name: NPBLB + description: Number of padding bytes in last block of payload + bit_offset: 20 + bit_size: 4 + - name: KMOD + description: Key mode selection + bit_offset: 24 + bit_size: 2 + - name: IPRST + description: AES peripheral software reset + bit_offset: 31 + bit_size: 1 +fieldset/DINR: + description: Data input register + fields: + - name: DIN + description: Input data word + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: Data output register + fields: + - name: DOUT + description: Output data word + bit_offset: 0 + bit_size: 32 +fieldset/ICR: + description: Interrupt clear register + fields: + - name: CCF + description: Computation complete flag clear + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag clear + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag clear + bit_offset: 2 + bit_size: 1 +fieldset/IER: + description: Interrupt enable register + fields: + - name: CCFIE + description: Computation complete flag interrupt enable + bit_offset: 0 + bit_size: 1 + - name: RWEIE + description: Read or write error interrupt enable + bit_offset: 1 + bit_size: 1 + - name: KEIE + description: Key error interrupt enable + bit_offset: 2 + bit_size: 1 +fieldset/ISR: + description: Interrupt status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag + bit_offset: 2 + bit_size: 1 +fieldset/IVR: + description: Initialization vector register + fields: + - name: IVI + description: Initialization vector input + bit_offset: 0 + bit_size: 32 +fieldset/KEYR: + description: Key register + fields: + - name: KEY + description: Cryptographic key + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: Status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: Read error flag + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: Write error flag + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy flag + bit_offset: 3 + bit_size: 1 + - name: KEYVALID + description: Key valid flag + bit_offset: 7 + bit_size: 1 +fieldset/SUSPR: + description: Suspend register + fields: + - name: SUSP + description: AES suspend + bit_offset: 0 + bit_size: 32 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: Encryption + value: 0 + - name: Mode2 + description: Key derivation (or key preparation for ECB/CBC decryption) + value: 1 + - name: Mode3 + description: Decryption + value: 2 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 From ccb0f18f5be6f15cd8dab2e4e1890b5252b62948 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:33:11 +0800 Subject: [PATCH 06/22] tailoring from aes_v3a to aes_v3b --- data/registers/aes_v3b.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml index bbe75a7..32a85c0 100644 --- a/data/registers/aes_v3b.yaml +++ b/data/registers/aes_v3b.yaml @@ -129,10 +129,6 @@ fieldset/DOUTR: fieldset/ICR: description: Interrupt clear register fields: - - name: CCF - description: Computation complete flag clear - bit_offset: 0 - bit_size: 1 - name: RWEIF description: Read or write error interrupt flag clear bit_offset: 1 From 12810e94550facbe78b2c7afa019e6fca7706df3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 13:46:25 +0800 Subject: [PATCH 07/22] add aes_v3b to chips.rs --- stm32-data-gen/src/chips.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 20b5520..a1270f2 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -155,6 +155,7 @@ impl PeriMatcher { ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), ("STM32U5.*:AES:.*", ("aes", "v3a", "AES")), + ("STM32(H5|WBA).*:AES:.*", ("aes", "v3b", "AES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From 0437b81a9edf4e1867548e1bd5a5b787c99129ee Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 16:43:46 +0800 Subject: [PATCH 08/22] extract --- data/registers/saes_v1a.yaml | 408 +++++++++++++++++++++++++++++++++++ 1 file changed, 408 insertions(+) create mode 100644 data/registers/saes_v1a.yaml diff --git a/data/registers/saes_v1a.yaml b/data/registers/saes_v1a.yaml new file mode 100644 index 0000000..d1bae76 --- /dev/null +++ b/data/registers/saes_v1a.yaml @@ -0,0 +1,408 @@ +block/SAES: + description: Secure advanced encryption standard hardware accelerator. + items: + - name: CR + description: SAES control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: SAES status register. + byte_offset: 4 + fieldset: SR + - name: DINR + description: SAES data input register. + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: SAES data output register. + byte_offset: 12 + fieldset: DOUTR + - name: KEYR0 + description: SAES key register 0. + byte_offset: 16 + fieldset: KEYR0 + - name: KEYR1 + description: SAES key register 1. + byte_offset: 20 + fieldset: KEYR1 + - name: KEYR2 + description: SAES key register 2. + byte_offset: 24 + fieldset: KEYR2 + - name: KEYR3 + description: SAES key register 3. + byte_offset: 28 + fieldset: KEYR3 + - name: IVR0 + description: SAES initialization vector register 0. + byte_offset: 32 + fieldset: IVR0 + - name: IVR1 + description: SAES initialization vector register 1. + byte_offset: 36 + fieldset: IVR1 + - name: IVR2 + description: SAES initialization vector register 2. + byte_offset: 40 + fieldset: IVR2 + - name: IVR3 + description: SAES initialization vector register 3. + byte_offset: 44 + fieldset: IVR3 + - name: KEYR4 + description: SAES key register 4. + byte_offset: 48 + fieldset: KEYR4 + - name: KEYR5 + description: SAES key register 5. + byte_offset: 52 + fieldset: KEYR5 + - name: KEYR6 + description: SAES key register 6. + byte_offset: 56 + fieldset: KEYR6 + - name: KEYR7 + description: SAES key register 7. + byte_offset: 60 + fieldset: KEYR7 + - name: SUSP0R + description: SAES suspend registers. + byte_offset: 64 + fieldset: SUSP0R + - name: SUSP1R + description: SAES suspend registers. + byte_offset: 68 + fieldset: SUSP1R + - name: SUSP2R + description: SAES suspend registers. + byte_offset: 72 + fieldset: SUSP2R + - name: SUSP3R + description: SAES suspend registers. + byte_offset: 76 + fieldset: SUSP3R + - name: SUSP4R + description: SAES suspend registers. + byte_offset: 80 + fieldset: SUSP4R + - name: SUSP5R + description: SAES suspend registers. + byte_offset: 84 + fieldset: SUSP5R + - name: SUSP6R + description: SAES suspend registers. + byte_offset: 88 + fieldset: SUSP6R + - name: SUSP7R + description: SAES suspend registers. + byte_offset: 92 + fieldset: SUSP7R + - name: IER + description: SAES interrupt enable register. + byte_offset: 768 + fieldset: IER + - name: ISR + description: SAES interrupt status register. + byte_offset: 772 + fieldset: ISR + - name: ICR + description: SAES interrupt clear register. + byte_offset: 776 + fieldset: ICR +fieldset/CR: + description: SAES control register. + fields: + - name: EN + description: 'SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN.' + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: 'Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 1 + bit_size: 2 + - name: MODE + description: 'SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 3 + bit_size: 2 + - name: CHMOD1 + description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 5 + bit_size: 2 + - name: DMAINEN + description: 'DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: 'DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: 'GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).' + bit_offset: 13 + bit_size: 2 + - name: CHMOD2 + description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 16 + bit_size: 1 + - name: KEYSIZE + description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 18 + bit_size: 1 + - name: KEYPROT + description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + bit_offset: 19 + bit_size: 1 + - name: NPBLB + description: 'Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...' + bit_offset: 20 + bit_size: 4 + - name: KMOD + description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 24 + bit_size: 2 + - name: KSHAREID + description: 'Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 26 + bit_size: 2 + - name: KEYSEL + description: 'Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 28 + bit_size: 3 + - name: IPRST + description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. + bit_offset: 31 + bit_size: 1 +fieldset/DINR: + description: SAES data input register. + fields: + - name: DIN + description: 'Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the SAES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the SAES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (SAES_KEYRx registers used for input if KEYSEL=0) - Mode 3 (decryption): ciphertext The data swap operation is described in on page 1149.' + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: SAES data output register. + fields: + - name: DOUT + description: 'Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the SAES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the SAES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used - Mode 3 (decryption): plaintext The data swap operation is described in on page 1149.' + bit_offset: 0 + bit_size: 32 +fieldset/ICR: + description: SAES interrupt clear register. + fields: + - name: CCF + description: Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. + bit_offset: 2 + bit_size: 1 + - name: RNGEIF + description: RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. + bit_offset: 3 + bit_size: 1 +fieldset/IER: + description: SAES interrupt enable register. + fields: + - name: CCFIE + description: Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. + bit_offset: 0 + bit_size: 1 + - name: RWEIE + description: Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. + bit_offset: 1 + bit_size: 1 + - name: KEIE + description: Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. + bit_offset: 2 + bit_size: 1 + - name: RNGEIE + description: RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. + bit_offset: 3 + bit_size: 1 +fieldset/ISR: + description: SAES interrupt status register. + fields: + - name: CCF + description: 'Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.' + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: 'Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.' + bit_offset: 2 + bit_size: 1 + - name: RNGEIF + description: RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. + bit_offset: 3 + bit_size: 1 +fieldset/IVR0: + description: SAES initialization vector register 0. + fields: + - name: IVI + description: Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The SAES_IVRx registers may be written only when the SAES peripheral is disabled. + bit_offset: 0 + bit_size: 32 +fieldset/IVR1: + description: SAES initialization vector register 1. + fields: + - name: IVI + description: Initialization vector input, bits [63:32] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/IVR2: + description: SAES initialization vector register 2. + fields: + - name: IVI + description: Initialization vector input, bits [95:64] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/IVR3: + description: SAES initialization vector register 3. + fields: + - name: IVI + description: Initialization vector input, bits [127:96] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR0: + description: SAES key register 0. + fields: + - name: KEY + description: 'Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. The SAES_KEYRx registers may be written only when KEYSIZE value is correct and when the SAES peripheral is disabled (EN bit of the SAES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the SAES_SR register. Note that, if KEYSEL is different from 0 and KEYVALID = 0, the key is directly loaded to SAES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details.' + bit_offset: 0 + bit_size: 32 +fieldset/KEYR1: + description: SAES key register 1. + fields: + - name: KEY + description: Cryptographic key, bits [63:32] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR2: + description: SAES key register 2. + fields: + - name: KEY + description: Cryptographic key, bits [95:64] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR3: + description: SAES key register 3. + fields: + - name: KEY + description: Cryptographic key, bits [127:96] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR4: + description: SAES key register 4. + fields: + - name: KEY + description: Cryptographic key, bits [159:128] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR5: + description: SAES key register 5. + fields: + - name: KEY + description: Cryptographic key, bits [191:160] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR6: + description: SAES key register 6. + fields: + - name: KEY + description: Cryptographic key, bits [223:192] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/KEYR7: + description: SAES key register 7. + fields: + - name: KEY + description: Cryptographic key, bits [255:224] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: SAES status register. + fields: + - name: CCF + description: Computation completed flag This bit mirrors the CCF bit of the SAES_ISR register. + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.' + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: 'Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored.' + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: 'Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase.' + bit_offset: 3 + bit_size: 1 + - name: KEYVALID + description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. + bit_offset: 7 + bit_size: 1 +fieldset/SUSP0R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP1R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP2R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP3R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP4R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP5R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP6R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 +fieldset/SUSP7R: + description: SAES suspend registers. + fields: + - name: SUSP + description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. + bit_offset: 0 + bit_size: 32 From 93a943cf3a10fbff8a18734cb3f99a5a8277f6e4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 18:33:51 +0800 Subject: [PATCH 09/22] apply transform --- data/registers/saes_v1a.yaml | 249 +++-------------------------------- transforms/SAES.yaml | 19 +++ 2 files changed, 38 insertions(+), 230 deletions(-) create mode 100644 transforms/SAES.yaml diff --git a/data/registers/saes_v1a.yaml b/data/registers/saes_v1a.yaml index d1bae76..8c3a3bd 100644 --- a/data/registers/saes_v1a.yaml +++ b/data/registers/saes_v1a.yaml @@ -12,91 +12,34 @@ block/SAES: - name: DINR description: SAES data input register. byte_offset: 8 - fieldset: DINR - name: DOUTR description: SAES data output register. byte_offset: 12 - fieldset: DOUTR - - name: KEYR0 + - name: KEYR description: SAES key register 0. + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: SAES key register 1. - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: SAES key register 2. - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: SAES key register 3. - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 + - name: IVR description: SAES initialization vector register 0. + array: + len: 4 + stride: 4 byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: SAES initialization vector register 1. - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: SAES initialization vector register 2. - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: SAES initialization vector register 3. - byte_offset: 44 - fieldset: IVR3 - - name: KEYR4 - description: SAES key register 4. - byte_offset: 48 - fieldset: KEYR4 - - name: KEYR5 - description: SAES key register 5. - byte_offset: 52 - fieldset: KEYR5 - - name: KEYR6 - description: SAES key register 6. - byte_offset: 56 - fieldset: KEYR6 - - name: KEYR7 - description: SAES key register 7. - byte_offset: 60 - fieldset: KEYR7 - - name: SUSP0R + - name: SUSPR description: SAES suspend registers. + array: + len: 8 + stride: 4 byte_offset: 64 - fieldset: SUSP0R - - name: SUSP1R - description: SAES suspend registers. - byte_offset: 68 - fieldset: SUSP1R - - name: SUSP2R - description: SAES suspend registers. - byte_offset: 72 - fieldset: SUSP2R - - name: SUSP3R - description: SAES suspend registers. - byte_offset: 76 - fieldset: SUSP3R - - name: SUSP4R - description: SAES suspend registers. - byte_offset: 80 - fieldset: SUSP4R - - name: SUSP5R - description: SAES suspend registers. - byte_offset: 84 - fieldset: SUSP5R - - name: SUSP6R - description: SAES suspend registers. - byte_offset: 88 - fieldset: SUSP6R - - name: SUSP7R - description: SAES suspend registers. - byte_offset: 92 - fieldset: SUSP7R - name: IER description: SAES interrupt enable register. byte_offset: 768 @@ -172,20 +115,6 @@ fieldset/CR: description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. bit_offset: 31 bit_size: 1 -fieldset/DINR: - description: SAES data input register. - fields: - - name: DIN - description: 'Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the SAES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the SAES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (SAES_KEYRx registers used for input if KEYSEL=0) - Mode 3 (decryption): ciphertext The data swap operation is described in on page 1149.' - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: SAES data output register. - fields: - - name: DOUT - description: 'Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the SAES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the SAES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used - Mode 3 (decryption): plaintext The data swap operation is described in on page 1149.' - bit_offset: 0 - bit_size: 32 fieldset/ICR: description: SAES interrupt clear register. fields: @@ -243,90 +172,6 @@ fieldset/ISR: description: RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. bit_offset: 3 bit_size: 1 -fieldset/IVR0: - description: SAES initialization vector register 0. - fields: - - name: IVI - description: Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The SAES_IVRx registers may be written only when the SAES peripheral is disabled. - bit_offset: 0 - bit_size: 32 -fieldset/IVR1: - description: SAES initialization vector register 1. - fields: - - name: IVI - description: Initialization vector input, bits [63:32] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: SAES initialization vector register 2. - fields: - - name: IVI - description: Initialization vector input, bits [95:64] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: SAES initialization vector register 3. - fields: - - name: IVI - description: Initialization vector input, bits [127:96] Refer to the SAES_IVR0 register for description of the IVI[128:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: SAES key register 0. - fields: - - name: KEY - description: 'Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. The SAES_KEYRx registers may be written only when KEYSIZE value is correct and when the SAES peripheral is disabled (EN bit of the SAES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the SAES_SR register. Note that, if KEYSEL is different from 0 and KEYVALID = 0, the key is directly loaded to SAES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details.' - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: SAES key register 1. - fields: - - name: KEY - description: Cryptographic key, bits [63:32] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: SAES key register 2. - fields: - - name: KEY - description: Cryptographic key, bits [95:64] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: SAES key register 3. - fields: - - name: KEY - description: Cryptographic key, bits [127:96] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR4: - description: SAES key register 4. - fields: - - name: KEY - description: Cryptographic key, bits [159:128] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR5: - description: SAES key register 5. - fields: - - name: KEY - description: Cryptographic key, bits [191:160] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR6: - description: SAES key register 6. - fields: - - name: KEY - description: Cryptographic key, bits [223:192] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 -fieldset/KEYR7: - description: SAES key register 7. - fields: - - name: KEY - description: Cryptographic key, bits [255:224] Refer to the SAES_KEYR0 register for description of the KEY[255:0] bitfield. - bit_offset: 0 - bit_size: 32 fieldset/SR: description: SAES status register. fields: @@ -350,59 +195,3 @@ fieldset/SR: description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. bit_offset: 7 bit_size: 1 -fieldset/SUSP0R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP1R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP2R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP3R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP4R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP5R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP6R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 -fieldset/SUSP7R: - description: SAES suspend registers. - fields: - - name: SUSP - description: SAES suspend Upon suspend operation, this bitfield of the corresponding SAES_SUSPxR register takes the value of one of internal SAES registers. - bit_offset: 0 - bit_size: 32 diff --git a/transforms/SAES.yaml b/transforms/SAES.yaml new file mode 100644 index 0000000..3739152 --- /dev/null +++ b/transforms/SAES.yaml @@ -0,0 +1,19 @@ +transforms: + - !DeleteFieldsets + from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$ + + - !MakeRegisterArray + blocks: SAES + from: ^(IVR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: SAES + allow_cursed: true + from: ^(KEYR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: SAES + from: ^(SUSP)\d(R)$ + to: $1$2 From 25ae37ec2220920004e63c28cf0f48ef181695e4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 18:37:31 +0800 Subject: [PATCH 10/22] recreate transform file and apply transform --- data/registers/aes_v3a.yaml | 76 +++++++++---------------------------- data/registers/aes_v3b.yaml | 76 +++++++++---------------------------- transforms/AES.yaml | 19 ++++++++++ 3 files changed, 55 insertions(+), 116 deletions(-) create mode 100644 transforms/AES.yaml diff --git a/data/registers/aes_v3a.yaml b/data/registers/aes_v3a.yaml index bbe75a7..9dd3cad 100644 --- a/data/registers/aes_v3a.yaml +++ b/data/registers/aes_v3a.yaml @@ -12,11 +12,9 @@ block/AES: - name: DINR description: Data input register byte_offset: 8 - fieldset: DINR - name: DOUTR description: Data output register byte_offset: 12 - fieldset: DOUTR - name: KEYR description: Key register array: @@ -30,21 +28,18 @@ block/AES: - 40 - 44 byte_offset: 16 - fieldset: KEYR - name: IVR description: Initialization vector register array: len: 4 stride: 4 byte_offset: 32 - fieldset: IVR - name: SUSPR description: Suspend register array: len: 8 stride: 4 byte_offset: 64 - fieldset: SUSPR - name: IER description: interrupt enable register byte_offset: 768 @@ -112,20 +107,6 @@ fieldset/CR: description: AES peripheral software reset bit_offset: 31 bit_size: 1 -fieldset/DINR: - description: Data input register - fields: - - name: DIN - description: Input data word - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: Data output register - fields: - - name: DOUT - description: Output data word - bit_offset: 0 - bit_size: 32 fieldset/ICR: description: Interrupt clear register fields: @@ -171,20 +152,6 @@ fieldset/ISR: description: Key error interrupt flag bit_offset: 2 bit_size: 1 -fieldset/IVR: - description: Initialization vector register - fields: - - name: IVI - description: Initialization vector input - bit_offset: 0 - bit_size: 32 -fieldset/KEYR: - description: Key register - fields: - - name: KEY - description: Cryptographic key - bit_offset: 0 - bit_size: 32 fieldset/SR: description: Status register fields: @@ -208,13 +175,24 @@ fieldset/SR: description: Key valid flag bit_offset: 7 bit_size: 1 -fieldset/SUSPR: - description: Suspend register - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 enum/DATATYPE: bit_size: 2 variants: @@ -257,21 +235,3 @@ enum/MODE: - name: Mode3 description: Decryption value: 2 -enum/CHMOD: - bit_size: 3 - variants: - - name: ECB - description: Electronic codebook - value: 0 - - name: CBC - description: Cipher-block chaining - value: 1 - - name: CTR - description: Counter mode - value: 2 - - name: GCM_GMAC - description: Galois counter mode and Galois message authentication code - value: 3 - - name: CCM - description: Counter with CBC-MAC - value: 4 diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml index 32a85c0..0ef8b12 100644 --- a/data/registers/aes_v3b.yaml +++ b/data/registers/aes_v3b.yaml @@ -12,11 +12,9 @@ block/AES: - name: DINR description: Data input register byte_offset: 8 - fieldset: DINR - name: DOUTR description: Data output register byte_offset: 12 - fieldset: DOUTR - name: KEYR description: Key register array: @@ -30,21 +28,18 @@ block/AES: - 40 - 44 byte_offset: 16 - fieldset: KEYR - name: IVR description: Initialization vector register array: len: 4 stride: 4 byte_offset: 32 - fieldset: IVR - name: SUSPR description: Suspend register array: len: 8 stride: 4 byte_offset: 64 - fieldset: SUSPR - name: IER description: interrupt enable register byte_offset: 768 @@ -112,20 +107,6 @@ fieldset/CR: description: AES peripheral software reset bit_offset: 31 bit_size: 1 -fieldset/DINR: - description: Data input register - fields: - - name: DIN - description: Input data word - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: Data output register - fields: - - name: DOUT - description: Output data word - bit_offset: 0 - bit_size: 32 fieldset/ICR: description: Interrupt clear register fields: @@ -167,20 +148,6 @@ fieldset/ISR: description: Key error interrupt flag bit_offset: 2 bit_size: 1 -fieldset/IVR: - description: Initialization vector register - fields: - - name: IVI - description: Initialization vector input - bit_offset: 0 - bit_size: 32 -fieldset/KEYR: - description: Key register - fields: - - name: KEY - description: Cryptographic key - bit_offset: 0 - bit_size: 32 fieldset/SR: description: Status register fields: @@ -204,13 +171,24 @@ fieldset/SR: description: Key valid flag bit_offset: 7 bit_size: 1 -fieldset/SUSPR: - description: Suspend register - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 enum/DATATYPE: bit_size: 2 variants: @@ -253,21 +231,3 @@ enum/MODE: - name: Mode3 description: Decryption value: 2 -enum/CHMOD: - bit_size: 3 - variants: - - name: ECB - description: Electronic codebook - value: 0 - - name: CBC - description: Cipher-block chaining - value: 1 - - name: CTR - description: Counter mode - value: 2 - - name: GCM_GMAC - description: Galois counter mode and Galois message authentication code - value: 3 - - name: CCM - description: Counter with CBC-MAC - value: 4 diff --git a/transforms/AES.yaml b/transforms/AES.yaml new file mode 100644 index 0000000..b8a13c8 --- /dev/null +++ b/transforms/AES.yaml @@ -0,0 +1,19 @@ +transforms: + - !DeleteFieldsets + from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$ + + - !MakeRegisterArray + blocks: AES + from: ^(IVR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: AES + allow_cursed: true + from: ^(KEYR)\d$ + to: $1 + + - !MakeRegisterArray + blocks: AES + from: ^(SUSP)\d(R)$ + to: $1$2 From b1bd6e97d6999a5a8e885612a520b85e911123db Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 19:21:56 +0800 Subject: [PATCH 11/22] add enum to saes_v1a --- data/registers/saes_v1a.yaml | 133 ++++++++++++++++++++++++++++++++--- 1 file changed, 122 insertions(+), 11 deletions(-) diff --git a/data/registers/saes_v1a.yaml b/data/registers/saes_v1a.yaml index 8c3a3bd..44b4d83 100644 --- a/data/registers/saes_v1a.yaml +++ b/data/registers/saes_v1a.yaml @@ -63,14 +63,21 @@ fieldset/CR: description: 'Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 1 bit_size: 2 + enum: DATATYPE - name: MODE description: 'SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 3 bit_size: 2 - - name: CHMOD1 + enum: MODE + - name: CHMOD description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' - bit_offset: 5 - bit_size: 2 + bit_offset: + - start: 5 + end: 6 + - start: 16 + end: 16 + bit_size: 3 + enum: CHMOD - name: DMAINEN description: 'DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' bit_offset: 11 @@ -83,14 +90,12 @@ fieldset/CR: description: 'GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).' bit_offset: 13 bit_size: 2 - - name: CHMOD2 - description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' - bit_offset: 16 - bit_size: 1 + enum: GCMPH - name: KEYSIZE description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 18 bit_size: 1 + enum: KEYSIZE - name: KEYPROT description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. bit_offset: 19 @@ -103,14 +108,17 @@ fieldset/CR: description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 24 bit_size: 2 + enum: KMOD - name: KSHAREID description: 'Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 26 bit_size: 2 + enum: KSHAREID - name: KEYSEL description: 'Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 28 bit_size: 3 + enum: KEYSEL - name: IPRST description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. bit_offset: 31 @@ -175,10 +183,6 @@ fieldset/ISR: fieldset/SR: description: SAES status register. fields: - - name: CCF - description: Computation completed flag This bit mirrors the CCF bit of the SAES_ISR register. - bit_offset: 0 - bit_size: 1 - name: RDERR description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.' bit_offset: 1 @@ -195,3 +199,110 @@ fieldset/SR: description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. bit_offset: 7 bit_size: 1 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: No swapping (32-bit data). + value: 0 + - name: HalfWord + description: Half-word swapping (16-bit data) + value: 1 + - name: Byte + description: Byte swapping (8-bit data) + value: 2 + - name: Bit + description: Bit-level swapping + value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: InitPhase + description: Initialization phase + value: 0 + - name: HeaderPhase + description: Header phase + value: 1 + - name: PayloadPhase + description: Payload phase + value: 2 + - name: FinalPhase + description: Final phase + value: 3 +enum/KEYSEL: + bit_size: 3 + variants: + - name: SoftwareKey + description: Software key, loaded in key registers SAES_KEYx + value: 0 + - name: DHUK + description: Derived hardware unique key + value: 1 + - name: BHK + description: Boot hardware key + value: 2 + - name: XOR_DHUK_BHK + description: XOR of DHUK and BHK + value: 4 +enum/KEYSIZE: + bit_size: 1 + variants: + - name: Bits128 + description: 128-bit + value: 0 + - name: Bits256 + description: 256-bit + value: 1 +enum/KMOD: + bit_size: 2 + variants: + - name: Normal + description: AES peripheral + value: 0 + - name: WrappedKey + description: |- + Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or + decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is + automatically loaded into SAES key registers after a successful decryption process. + value: 1 + - name: SharedKey + description: |- + Shared key mode. After a successful decryption process (unwrapping), SAES key registers are + shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while + KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR + register is automatically loaded into SAES key registers after a successful decryption process. + value: 2 +enum/KSHAREID: + bit_size: 2 + variants: + - name: AES + description: AES peripheral + value: 0 +enum/MODE: + bit_size: 2 + variants: + - name: Encryption + value: 0 + - name: KeyDerivation + description: Key derivation (or key preparation), for ECB/CBC decryption only + value: 1 + - name: Decryption + value: 2 From a26d7f3e117dd01de3d8a9bd8158ff0b196998c8 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 19:28:21 +0800 Subject: [PATCH 12/22] branch from saes_v1a to saes_v1b --- data/registers/saes_v1b.yaml | 308 +++++++++++++++++++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 data/registers/saes_v1b.yaml diff --git a/data/registers/saes_v1b.yaml b/data/registers/saes_v1b.yaml new file mode 100644 index 0000000..44b4d83 --- /dev/null +++ b/data/registers/saes_v1b.yaml @@ -0,0 +1,308 @@ +block/SAES: + description: Secure advanced encryption standard hardware accelerator. + items: + - name: CR + description: SAES control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: SAES status register. + byte_offset: 4 + fieldset: SR + - name: DINR + description: SAES data input register. + byte_offset: 8 + - name: DOUTR + description: SAES data output register. + byte_offset: 12 + - name: KEYR + description: SAES key register 0. + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 + byte_offset: 16 + - name: IVR + description: SAES initialization vector register 0. + array: + len: 4 + stride: 4 + byte_offset: 32 + - name: SUSPR + description: SAES suspend registers. + array: + len: 8 + stride: 4 + byte_offset: 64 + - name: IER + description: SAES interrupt enable register. + byte_offset: 768 + fieldset: IER + - name: ISR + description: SAES interrupt status register. + byte_offset: 772 + fieldset: ISR + - name: ICR + description: SAES interrupt clear register. + byte_offset: 776 + fieldset: ICR +fieldset/CR: + description: SAES control register. + fields: + - name: EN + description: 'SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN.' + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: 'Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 1 + bit_size: 2 + enum: DATATYPE + - name: MODE + description: 'SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 3 + bit_size: 2 + enum: MODE + - name: CHMOD + description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: + - start: 5 + end: 6 + - start: 16 + end: 16 + bit_size: 3 + enum: CHMOD + - name: DMAINEN + description: 'DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: 'DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: 'GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).' + bit_offset: 13 + bit_size: 2 + enum: GCMPH + - name: KEYSIZE + description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 18 + bit_size: 1 + enum: KEYSIZE + - name: KEYPROT + description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. + bit_offset: 19 + bit_size: 1 + - name: NPBLB + description: 'Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...' + bit_offset: 20 + bit_size: 4 + - name: KMOD + description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 24 + bit_size: 2 + enum: KMOD + - name: KSHAREID + description: 'Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 26 + bit_size: 2 + enum: KSHAREID + - name: KEYSEL + description: 'Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' + bit_offset: 28 + bit_size: 3 + enum: KEYSEL + - name: IPRST + description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers. + bit_offset: 31 + bit_size: 1 +fieldset/ICR: + description: SAES interrupt clear register. + fields: + - name: CCF + description: Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers. + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register. + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register. + bit_offset: 2 + bit_size: 1 + - name: RNGEIF + description: RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register. + bit_offset: 3 + bit_size: 1 +fieldset/IER: + description: SAES interrupt enable register. + fields: + - name: CCFIE + description: Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set. + bit_offset: 0 + bit_size: 1 + - name: RWEIE + description: Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set. + bit_offset: 1 + bit_size: 1 + - name: KEIE + description: Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set. + bit_offset: 2 + bit_size: 1 + - name: RNGEIE + description: RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set. + bit_offset: 3 + bit_size: 1 +fieldset/ISR: + description: SAES interrupt status register. + fields: + - name: CCF + description: 'Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.' + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected. + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: 'Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.' + bit_offset: 2 + bit_size: 1 + - name: RNGEIF + description: RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral. + bit_offset: 3 + bit_size: 1 +fieldset/SR: + description: SAES status register. + fields: + - name: RDERR + description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.' + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: 'Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored.' + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: 'Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase.' + bit_offset: 3 + bit_size: 1 + - name: KEYVALID + description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to. + bit_offset: 7 + bit_size: 1 +enum/CHMOD: + bit_size: 3 + variants: + - name: ECB + description: Electronic codebook + value: 0 + - name: CBC + description: Cipher-block chaining + value: 1 + - name: CTR + description: Counter mode + value: 2 + - name: GCM_GMAC + description: Galois counter mode and Galois message authentication code + value: 3 + - name: CCM + description: Counter with CBC-MAC + value: 4 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: No swapping (32-bit data). + value: 0 + - name: HalfWord + description: Half-word swapping (16-bit data) + value: 1 + - name: Byte + description: Byte swapping (8-bit data) + value: 2 + - name: Bit + description: Bit-level swapping + value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: InitPhase + description: Initialization phase + value: 0 + - name: HeaderPhase + description: Header phase + value: 1 + - name: PayloadPhase + description: Payload phase + value: 2 + - name: FinalPhase + description: Final phase + value: 3 +enum/KEYSEL: + bit_size: 3 + variants: + - name: SoftwareKey + description: Software key, loaded in key registers SAES_KEYx + value: 0 + - name: DHUK + description: Derived hardware unique key + value: 1 + - name: BHK + description: Boot hardware key + value: 2 + - name: XOR_DHUK_BHK + description: XOR of DHUK and BHK + value: 4 +enum/KEYSIZE: + bit_size: 1 + variants: + - name: Bits128 + description: 128-bit + value: 0 + - name: Bits256 + description: 256-bit + value: 1 +enum/KMOD: + bit_size: 2 + variants: + - name: Normal + description: AES peripheral + value: 0 + - name: WrappedKey + description: |- + Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or + decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is + automatically loaded into SAES key registers after a successful decryption process. + value: 1 + - name: SharedKey + description: |- + Shared key mode. After a successful decryption process (unwrapping), SAES key registers are + shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while + KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR + register is automatically loaded into SAES key registers after a successful decryption process. + value: 2 +enum/KSHAREID: + bit_size: 2 + variants: + - name: AES + description: AES peripheral + value: 0 +enum/MODE: + bit_size: 2 + variants: + - name: Encryption + value: 0 + - name: KeyDerivation + description: Key derivation (or key preparation), for ECB/CBC decryption only + value: 1 + - name: Decryption + value: 2 From 6f45c8c9b2ccc1a891e3aa40a31d56b545a9c61f Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 19:34:56 +0800 Subject: [PATCH 13/22] tailoring from saes_v1a to saes_v1b --- data/registers/saes_v1b.yaml | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/data/registers/saes_v1b.yaml b/data/registers/saes_v1b.yaml index 44b4d83..26881aa 100644 --- a/data/registers/saes_v1b.yaml +++ b/data/registers/saes_v1b.yaml @@ -86,11 +86,6 @@ fieldset/CR: description: 'DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' bit_offset: 12 bit_size: 1 - - name: GCMPH - description: 'GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).' - bit_offset: 13 - bit_size: 2 - enum: GCMPH - name: KEYSIZE description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 18 @@ -100,10 +95,6 @@ fieldset/CR: description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. bit_offset: 19 bit_size: 1 - - name: NPBLB - description: 'Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...' - bit_offset: 20 - bit_size: 4 - name: KMOD description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 24 @@ -183,6 +174,10 @@ fieldset/ISR: fieldset/SR: description: SAES status register. fields: + - name: CCF + description: Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register. + bit_offset: 1 + bit_size: 1 - name: RDERR description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.' bit_offset: 1 @@ -232,21 +227,6 @@ enum/DATATYPE: - name: Bit description: Bit-level swapping value: 3 -enum/GCMPH: - bit_size: 2 - variants: - - name: InitPhase - description: Initialization phase - value: 0 - - name: HeaderPhase - description: Header phase - value: 1 - - name: PayloadPhase - description: Payload phase - value: 2 - - name: FinalPhase - description: Final phase - value: 3 enum/KEYSEL: bit_size: 3 variants: From 213784d2316fd37bce7638062ee2af0dd5034cf0 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 19:38:56 +0800 Subject: [PATCH 14/22] add saes to chip.rs --- stm32-data-gen/src/chips.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e6de9f0..48cafc5 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -155,6 +155,8 @@ impl PeriMatcher { ("STM32U5.*:AES:.*", ("aes", "u5", "AES")), ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), + ("STM32(H5|WBA).*:SAES:.*", ("saes", "v1a", "SAES")), + ("STM32U5.*:SAES:.*", ("saes", "v1b", "SAES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")), From c20cd25016b2a8af0e5df39c95e53df5cc1c4928 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 20:04:41 +0800 Subject: [PATCH 15/22] extract --- data/registers/pka_v1a.yaml | 96 +++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 data/registers/pka_v1a.yaml diff --git a/data/registers/pka_v1a.yaml b/data/registers/pka_v1a.yaml new file mode 100644 index 0000000..226d69e --- /dev/null +++ b/data/registers/pka_v1a.yaml @@ -0,0 +1,96 @@ +block/PKA: + description: Private key accelerator. + items: + - name: CR + description: PKA control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: PKA status register. + byte_offset: 4 + fieldset: SR + - name: CLRFR + description: PKA clear flag register. + byte_offset: 8 + fieldset: CLRFR +fieldset/CLRFR: + description: PKA clear flag register. + fields: + - name: PROCENDFC + description: Clear PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRFC + description: Clear PKA RAM error flag. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRFC + description: Clear address error flag. + bit_offset: 20 + bit_size: 1 + - name: OPERRFC + description: Clear operation error flag. + bit_offset: 21 + bit_size: 1 +fieldset/CR: + description: PKA control register. + fields: + - name: EN + description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + bit_offset: 0 + bit_size: 1 + - name: START + description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + bit_offset: 1 + bit_size: 1 + - name: MODE + description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + bit_offset: 8 + bit_size: 6 + - name: PROCENDIE + description: End of operation interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: RAMERRIE + description: RAM error interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRIE + description: Address error interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: OPERRIE + description: Operation error interrupt enable. + bit_offset: 21 + bit_size: 1 +fieldset/SR: + description: PKA status register. + fields: + - name: INITOK + description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + bit_offset: 0 + bit_size: 1 + - name: LMF + description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + bit_offset: 16 + bit_size: 1 + - name: PROCENDF + description: PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRF + description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRF + description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + bit_offset: 20 + bit_size: 1 + - name: OPERRF + description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + bit_offset: 21 + bit_size: 1 From e5d85dae39053a90b97f341c1b4c6419d807cdd5 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:04:31 +0800 Subject: [PATCH 16/22] add enum --- data/registers/pka_v1a.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/data/registers/pka_v1a.yaml b/data/registers/pka_v1a.yaml index 226d69e..bebc11a 100644 --- a/data/registers/pka_v1a.yaml +++ b/data/registers/pka_v1a.yaml @@ -74,6 +74,7 @@ fieldset/SR: description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. bit_offset: 1 bit_size: 1 + enum: LMF - name: BUSY description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). bit_offset: 16 @@ -94,3 +95,12 @@ fieldset/SR: description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. bit_offset: 21 bit_size: 1 +enum/LMF: + bit_size: 1 + variants: + - name: All + description: All values documented in MODE bitfield can be used. + value: 0 + - name: Limited + description: Only ECDSA verification (MODE = 0x26) is supported by the PKA. + value: 1 From 2fec12bda672a7dc340dc9ea347b6dc98b93a158 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:35:04 +0800 Subject: [PATCH 17/22] branch from pka_v1a to pka_v1b --- data/registers/pka_v1b.yaml | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 data/registers/pka_v1b.yaml diff --git a/data/registers/pka_v1b.yaml b/data/registers/pka_v1b.yaml new file mode 100644 index 0000000..bebc11a --- /dev/null +++ b/data/registers/pka_v1b.yaml @@ -0,0 +1,106 @@ +block/PKA: + description: Private key accelerator. + items: + - name: CR + description: PKA control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: PKA status register. + byte_offset: 4 + fieldset: SR + - name: CLRFR + description: PKA clear flag register. + byte_offset: 8 + fieldset: CLRFR +fieldset/CLRFR: + description: PKA clear flag register. + fields: + - name: PROCENDFC + description: Clear PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRFC + description: Clear PKA RAM error flag. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRFC + description: Clear address error flag. + bit_offset: 20 + bit_size: 1 + - name: OPERRFC + description: Clear operation error flag. + bit_offset: 21 + bit_size: 1 +fieldset/CR: + description: PKA control register. + fields: + - name: EN + description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + bit_offset: 0 + bit_size: 1 + - name: START + description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + bit_offset: 1 + bit_size: 1 + - name: MODE + description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + bit_offset: 8 + bit_size: 6 + - name: PROCENDIE + description: End of operation interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: RAMERRIE + description: RAM error interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRIE + description: Address error interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: OPERRIE + description: Operation error interrupt enable. + bit_offset: 21 + bit_size: 1 +fieldset/SR: + description: PKA status register. + fields: + - name: INITOK + description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + bit_offset: 0 + bit_size: 1 + - name: LMF + description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. + bit_offset: 1 + bit_size: 1 + enum: LMF + - name: BUSY + description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + bit_offset: 16 + bit_size: 1 + - name: PROCENDF + description: PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRF + description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRF + description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + bit_offset: 20 + bit_size: 1 + - name: OPERRF + description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + bit_offset: 21 + bit_size: 1 +enum/LMF: + bit_size: 1 + variants: + - name: All + description: All values documented in MODE bitfield can be used. + value: 0 + - name: Limited + description: Only ECDSA verification (MODE = 0x26) is supported by the PKA. + value: 1 From f839d76da67923c0cc95acd10daa7dfe4dad323c Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:36:20 +0800 Subject: [PATCH 18/22] tailoring from pka_v1a to pka_v1b --- data/registers/pka_v1b.yaml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/data/registers/pka_v1b.yaml b/data/registers/pka_v1b.yaml index bebc11a..51a1b24 100644 --- a/data/registers/pka_v1b.yaml +++ b/data/registers/pka_v1b.yaml @@ -70,11 +70,6 @@ fieldset/SR: description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. bit_offset: 0 bit_size: 1 - - name: LMF - description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. - bit_offset: 1 - bit_size: 1 - enum: LMF - name: BUSY description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). bit_offset: 16 @@ -95,12 +90,3 @@ fieldset/SR: description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. bit_offset: 21 bit_size: 1 -enum/LMF: - bit_size: 1 - variants: - - name: All - description: All values documented in MODE bitfield can be used. - value: 0 - - name: Limited - description: Only ECDSA verification (MODE = 0x26) is supported by the PKA. - value: 1 From f4567db67a43153c7bca4a99c296e87f197c521b Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:42:57 +0800 Subject: [PATCH 19/22] branch from pka_v1b to pka_v1c --- data/registers/pka_v1c.yaml | 92 +++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 data/registers/pka_v1c.yaml diff --git a/data/registers/pka_v1c.yaml b/data/registers/pka_v1c.yaml new file mode 100644 index 0000000..51a1b24 --- /dev/null +++ b/data/registers/pka_v1c.yaml @@ -0,0 +1,92 @@ +block/PKA: + description: Private key accelerator. + items: + - name: CR + description: PKA control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: PKA status register. + byte_offset: 4 + fieldset: SR + - name: CLRFR + description: PKA clear flag register. + byte_offset: 8 + fieldset: CLRFR +fieldset/CLRFR: + description: PKA clear flag register. + fields: + - name: PROCENDFC + description: Clear PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRFC + description: Clear PKA RAM error flag. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRFC + description: Clear address error flag. + bit_offset: 20 + bit_size: 1 + - name: OPERRFC + description: Clear operation error flag. + bit_offset: 21 + bit_size: 1 +fieldset/CR: + description: PKA control register. + fields: + - name: EN + description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + bit_offset: 0 + bit_size: 1 + - name: START + description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + bit_offset: 1 + bit_size: 1 + - name: MODE + description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + bit_offset: 8 + bit_size: 6 + - name: PROCENDIE + description: End of operation interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: RAMERRIE + description: RAM error interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRIE + description: Address error interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: OPERRIE + description: Operation error interrupt enable. + bit_offset: 21 + bit_size: 1 +fieldset/SR: + description: PKA status register. + fields: + - name: INITOK + description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + bit_offset: 0 + bit_size: 1 + - name: BUSY + description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + bit_offset: 16 + bit_size: 1 + - name: PROCENDF + description: PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRF + description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRF + description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + bit_offset: 20 + bit_size: 1 + - name: OPERRF + description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + bit_offset: 21 + bit_size: 1 From 6f3f972c6ce2ea0ae1af5bb075fa3094c65702ea Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:44:44 +0800 Subject: [PATCH 20/22] tailoring from pka_v1b to pka_v1c --- data/registers/pka_v1c.yaml | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/data/registers/pka_v1c.yaml b/data/registers/pka_v1c.yaml index 51a1b24..1c08919 100644 --- a/data/registers/pka_v1c.yaml +++ b/data/registers/pka_v1c.yaml @@ -28,10 +28,6 @@ fieldset/CLRFR: description: Clear address error flag. bit_offset: 20 bit_size: 1 - - name: OPERRFC - description: Clear operation error flag. - bit_offset: 21 - bit_size: 1 fieldset/CR: description: PKA control register. fields: @@ -59,17 +55,9 @@ fieldset/CR: description: Address error interrupt enable. bit_offset: 20 bit_size: 1 - - name: OPERRIE - description: Operation error interrupt enable. - bit_offset: 21 - bit_size: 1 fieldset/SR: description: PKA status register. fields: - - name: INITOK - description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. - bit_offset: 0 - bit_size: 1 - name: BUSY description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). bit_offset: 16 @@ -86,7 +74,3 @@ fieldset/SR: description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. bit_offset: 20 bit_size: 1 - - name: OPERRF - description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. - bit_offset: 21 - bit_size: 1 From 2a8bc99b555846d1d0b876aa8fdfa877713d69e7 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:48:39 +0800 Subject: [PATCH 21/22] add pka to chips.rs --- stm32-data-gen/src/chips.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e6de9f0..fc5f0c3 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -621,6 +621,9 @@ impl PeriMatcher { ("STM32(H7|U5).*:VREFBUF:.*", ("vrefbuf", "v2a1", "VREFBUF")), ("STM32H5.*:VREFBUF:.*", ("vrefbuf", "v2a2", "VREFBUF")), ("STM32G4.*:VREFBUF:.*", ("vrefbuf", "v2b", "VREFBUF")), + ("STM32(H5|WBA).*:PKA:.*", ("pka", "v1a", "PKA")), + ("STM32U5.*:PKA:.*", ("pka", "v1b", "PKA")), + ("STM32(L5|WL|WB).*:PKA:.*", ("pka", "v1c", "PKA")), ]; Self { From 24b62ea85d89c5d173c0f39ac65b850b907c1263 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 24 Feb 2024 13:06:50 +0800 Subject: [PATCH 22/22] make address of registers show as hex --- Cargo.lock | 2 +- stm32-data-gen/Cargo.toml | 2 +- stm32-metapac-gen/Cargo.toml | 2 +- stm32-metapac-gen/src/data.rs | 59 +++++++++++++++++++++++++++++++++-- 4 files changed, 59 insertions(+), 6 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 7bd0cdb..75bf756 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -85,7 +85,7 @@ checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" [[package]] name = "chiptool" version = "0.1.0" -source = "git+https://github.com/embassy-rs/chiptool?rev=247ccbe44669ac716393247e56693a396e641e4a#247ccbe44669ac716393247e56693a396e641e4a" +source = "git+https://github.com/embassy-rs/chiptool?rev=1c198ae678ebd426751513f0deab6fbd6f8b8211#1c198ae678ebd426751513f0deab6fbd6f8b8211" dependencies = [ "anyhow", "clap", diff --git a/stm32-data-gen/Cargo.toml b/stm32-data-gen/Cargo.toml index ba8f21e..6ae7720 100644 --- a/stm32-data-gen/Cargo.toml +++ b/stm32-data-gen/Cargo.toml @@ -17,7 +17,7 @@ quick-xml = { version = "0.26.0", features = ["serialize"] } regex = "1.7.1" serde = { version = "1.0.157", features = ["derive"] } serde_yaml = "0.9.19" -chiptool = { git = "https://github.com/embassy-rs/chiptool", rev="247ccbe44669ac716393247e56693a396e641e4a" } +chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "1c198ae678ebd426751513f0deab6fbd6f8b8211" } serde_json = "1.0.94" rayon = { version = "1.7.0", optional = true } stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" } diff --git a/stm32-metapac-gen/Cargo.toml b/stm32-metapac-gen/Cargo.toml index f9a12fb..60eddef 100644 --- a/stm32-metapac-gen/Cargo.toml +++ b/stm32-metapac-gen/Cargo.toml @@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0" [dependencies] regex = "1.7.1" -chiptool = { git = "https://github.com/embassy-rs/chiptool", rev="247ccbe44669ac716393247e56693a396e641e4a" } +chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "1c198ae678ebd426751513f0deab6fbd6f8b8211" } serde = { version = "1.0.157", features = [ "derive" ] } serde_json = "1.0.94" proc-macro2 = "1.0.52" diff --git a/stm32-metapac-gen/src/data.rs b/stm32-metapac-gen/src/data.rs index 9e3549d..dc24d63 100644 --- a/stm32-metapac-gen/src/data.rs +++ b/stm32-metapac-gen/src/data.rs @@ -158,7 +158,10 @@ pub mod ir { pub items: Vec, } - #[derive(Debug, Eq, PartialEq, Clone, Deserialize)] + // Notice: + // BlockItem has custom Debug implement, + // when modify the struct, make sure Debug impl reflect the change. + #[derive(Eq, PartialEq, Clone, Deserialize)] pub struct BlockItem { pub name: String, pub description: Option, @@ -169,6 +172,20 @@ pub mod ir { pub inner: BlockItemInner, } + // Notice: + // Debug implement AFFECT OUTPUT METAPAC, modify with caution + impl std::fmt::Debug for BlockItem { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("BlockItem") + .field("name", &self.name) + .field("description", &self.description) + .field("array", &self.array) + .field("byte_offset", &format_args!("{:#x}", self.byte_offset)) + .field("inner", &self.inner) + .finish() + } + } + #[derive(EnumDebug, Eq, PartialEq, Clone, Deserialize)] pub enum BlockItemInner { Block(BlockItemBlock), @@ -274,7 +291,10 @@ pub struct Chip { pub packages: Vec, } -#[derive(Debug, Eq, PartialEq, Clone, Deserialize)] +// Notice: +// MemoryRegion has custom Debug implement, +// when modify the struct, make sure Debug impl reflect the change. +#[derive(Eq, PartialEq, Clone, Deserialize)] pub struct MemoryRegion { pub name: String, pub kind: MemoryRegionKind, @@ -283,6 +303,20 @@ pub struct MemoryRegion { pub settings: Option, } +// Notice: +// Debug implement AFFECT OUTPUT METAPAC, modify with caution +impl std::fmt::Debug for MemoryRegion { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("MemoryRegion") + .field("name", &self.name) + .field("kind", &self.kind) + .field("address", &format_args!("{:#x}", self.address)) + .field("size", &self.size) + .field("settings", &self.settings) + .finish() + } +} + #[derive(Debug, Eq, PartialEq, Clone, Deserialize)] pub struct FlashSettings { pub erase_size: u32, @@ -320,7 +354,10 @@ pub struct Package { pub package: String, } -#[derive(Debug, Eq, PartialEq, Clone, Deserialize)] +// Notice: +// Peripheral has custom Debug implement, +// when modify struct, make sure Debug impl reflect the change. +#[derive(Eq, PartialEq, Clone, Deserialize)] pub struct Peripheral { pub name: String, pub address: u64, @@ -336,6 +373,22 @@ pub struct Peripheral { pub interrupts: Vec, } +// Notice: +// Debug implement AFFECT OUTPUT METAPAC, modify with caution +impl std::fmt::Debug for Peripheral { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.debug_struct("Peripheral") + .field("name", &self.name) + .field("address", &format_args!("{:#x}", self.address)) + .field("registers", &self.registers) + .field("rcc", &self.rcc) + .field("pins", &self.pins) + .field("dma_channels", &self.dma_channels) + .field("interrupts", &self.interrupts) + .finish() + } +} + #[derive(Debug, Eq, PartialEq, Clone, Deserialize)] pub struct PeripheralInterrupt { pub signal: String,