diff --git a/Cargo.lock b/Cargo.lock
index 7bd0cdb..75bf756 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -85,7 +85,7 @@ checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
 [[package]]
 name = "chiptool"
 version = "0.1.0"
-source = "git+https://github.com/embassy-rs/chiptool?rev=247ccbe44669ac716393247e56693a396e641e4a#247ccbe44669ac716393247e56693a396e641e4a"
+source = "git+https://github.com/embassy-rs/chiptool?rev=1c198ae678ebd426751513f0deab6fbd6f8b8211#1c198ae678ebd426751513f0deab6fbd6f8b8211"
 dependencies = [
  "anyhow",
  "clap",
diff --git a/data/registers/adccommon_h50.yaml b/data/registers/adccommon_h50.yaml
index 2d14a37..b30aabb 100644
--- a/data/registers/adccommon_h50.yaml
+++ b/data/registers/adccommon_h50.yaml
@@ -16,11 +16,9 @@ block/ADC_COMMON:
   - name: IPDR
     description: identification register
     byte_offset: 248
-    fieldset: IPDR
   - name: SIDR
     description: size identification register
     byte_offset: 252
-    fieldset: SIDR
 fieldset/CCR:
   description: common control register
   fields:
@@ -28,10 +26,12 @@ fieldset/CCR:
     description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
     bit_offset: 16
     bit_size: 2
+    enum: CKMODE
   - name: PRESC
     description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
     bit_offset: 18
     bit_size: 4
+    enum: PRESC
   - name: VREFEN
     description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
     bit_offset: 22
@@ -63,6 +63,7 @@ fieldset/HWCFGR0:
     description: Idle value for non-selected channels
     bit_offset: 12
     bit_size: 4
+    enum: IDLEVALUE
 fieldset/VERR:
   description: version register
   fields:
@@ -74,17 +75,66 @@ fieldset/VERR:
     description: Major revision These bits returns the ADC IP major revision
     bit_offset: 4
     bit_size: 4
-fieldset/IPDR:
-  description: identification register
-  fields:
-  - name: ID
-    description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.'
-    bit_offset: 0
-    bit_size: 32
-fieldset/SIDR:
-  description: size identification register
-  fields:
-  - name: SID
-    description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.'
-    bit_offset: 0
-    bit_size: 32
+enum/CKMODE:
+  bit_size: 2
+  variants:
+  - name: Asynchronous
+    description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
+    value: 0
+  - name: SyncDiv1
+    description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
+    value: 1
+  - name: SyncDiv2
+    description: Use AHB clock rcc_hclk3 divided by 2
+    value: 2
+  - name: SyncDiv4
+    description: Use AHB clock rcc_hclk3 divided by 4
+    value: 3
+enum/IDLEVALUE:
+  bit_size: 4
+  variants:
+  - name: H13
+    description: Dummy channel selection is 0x13
+    value: 0
+  - name: H1F
+    description: Dummy channel selection is 0x1F
+    value: 1
+enum/PRESC:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: adc_ker_ck_input not divided
+    value: 0
+  - name: Div2
+    description: adc_ker_ck_input divided by 2
+    value: 1
+  - name: Div4
+    description: adc_ker_ck_input divided by 4
+    value: 2
+  - name: Div6
+    description: adc_ker_ck_input divided by 6
+    value: 3
+  - name: Div8
+    description: adc_ker_ck_input divided by 8
+    value: 4
+  - name: Div10
+    description: adc_ker_ck_input divided by 10
+    value: 5
+  - name: Div12
+    description: adc_ker_ck_input divided by 12
+    value: 6
+  - name: Div16
+    description: adc_ker_ck_input divided by 16
+    value: 7
+  - name: Div32
+    description: adc_ker_ck_input divided by 32
+    value: 8
+  - name: Div64
+    description: adc_ker_ck_input divided by 64
+    value: 9
+  - name: Div128
+    description: adc_ker_ck_input divided by 128
+    value: 10
+  - name: Div256
+    description: adc_ker_ck_input divided by 256
+    value: 11
diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_v3a.yaml
similarity index 81%
rename from data/registers/aes_u5.yaml
rename to data/registers/aes_v3a.yaml
index e46fc54..9dd3cad 100644
--- a/data/registers/aes_u5.yaml
+++ b/data/registers/aes_v3a.yaml
@@ -12,11 +12,9 @@ block/AES:
   - name: DINR
     description: Data input register
     byte_offset: 8
-    fieldset: DINR
   - name: DOUTR
     description: Data output register
     byte_offset: 12
-    fieldset: DOUTR
   - name: KEYR
     description: Key register
     array:
@@ -30,21 +28,18 @@ block/AES:
       - 40
       - 44
     byte_offset: 16
-    fieldset: KEYR
   - name: IVR
     description: Initialization vector register
     array:
       len: 4
       stride: 4
     byte_offset: 32
-    fieldset: IVR
   - name: SUSPR
     description: Suspend register
     array:
       len: 8
       stride: 4
     byte_offset: 64
-    fieldset: SUSPR
   - name: IER
     description: interrupt enable register
     byte_offset: 768
@@ -74,10 +69,15 @@ fieldset/CR:
     bit_offset: 3
     bit_size: 2
     enum: MODE
-  - name: CHMOD10
-    description: Chaining mode bit1 bit0
-    bit_offset: 5
-    bit_size: 2
+  - name: CHMOD
+    description: Chaining mode selection
+    bit_offset:
+    - start: 5
+      end: 6
+    - start: 16
+      end: 16
+    bit_size: 3
+    enum: CHMOD
   - name: DMAINEN
     description: Enable DMA management of data input phase
     bit_offset: 11
@@ -91,10 +91,6 @@ fieldset/CR:
     bit_offset: 13
     bit_size: 2
     enum: GCMPH
-  - name: CHMOD2
-    description: Chaining mode bit2
-    bit_offset: 16
-    bit_size: 1
   - name: KEYSIZE
     description: Key size selection
     bit_offset: 18
@@ -111,20 +107,6 @@ fieldset/CR:
     description: AES peripheral software reset
     bit_offset: 31
     bit_size: 1
-fieldset/DINR:
-  description: Data input register
-  fields:
-  - name: DIN
-    description: Input data word
-    bit_offset: 0
-    bit_size: 32
-fieldset/DOUTR:
-  description: Data output register
-  fields:
-  - name: DOUT
-    description: Output data word
-    bit_offset: 0
-    bit_size: 32
 fieldset/ICR:
   description: Interrupt clear register
   fields:
@@ -170,20 +152,6 @@ fieldset/ISR:
     description: Key error interrupt flag
     bit_offset: 2
     bit_size: 1
-fieldset/IVR:
-  description: Initialization vector register
-  fields:
-  - name: IVI
-    description: Initialization vector input
-    bit_offset: 0
-    bit_size: 32
-fieldset/KEYR:
-  description: Key register
-  fields:
-  - name: KEY
-    description: Cryptographic key
-    bit_offset: 0
-    bit_size: 32
 fieldset/SR:
   description: Status register
   fields:
@@ -207,13 +175,24 @@ fieldset/SR:
     description: Key valid flag
     bit_offset: 7
     bit_size: 1
-fieldset/SUSPR:
-  description: Suspend register
-  fields:
-  - name: SUSP
-    description: AES suspend
-    bit_offset: 0
-    bit_size: 32
+enum/CHMOD:
+  bit_size: 3
+  variants:
+  - name: ECB
+    description: Electronic codebook
+    value: 0
+  - name: CBC
+    description: Cipher-block chaining
+    value: 1
+  - name: CTR
+    description: Counter mode
+    value: 2
+  - name: GCM_GMAC
+    description: Galois counter mode and Galois message authentication code
+    value: 3
+  - name: CCM
+    description: Counter with CBC-MAC
+    value: 4
 enum/DATATYPE:
   bit_size: 2
   variants:
diff --git a/data/registers/aes_v3b.yaml b/data/registers/aes_v3b.yaml
new file mode 100644
index 0000000..0ef8b12
--- /dev/null
+++ b/data/registers/aes_v3b.yaml
@@ -0,0 +1,233 @@
+block/AES:
+  description: Advanced encryption standard hardware accelerator
+  items:
+  - name: CR
+    description: Control register
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: Status register
+    byte_offset: 4
+    fieldset: SR
+  - name: DINR
+    description: Data input register
+    byte_offset: 8
+  - name: DOUTR
+    description: Data output register
+    byte_offset: 12
+  - name: KEYR
+    description: Key register
+    array:
+      offsets:
+      - 0
+      - 4
+      - 8
+      - 12
+      - 32
+      - 36
+      - 40
+      - 44
+    byte_offset: 16
+  - name: IVR
+    description: Initialization vector register
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 32
+  - name: SUSPR
+    description: Suspend register
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 64
+  - name: IER
+    description: interrupt enable register
+    byte_offset: 768
+    fieldset: IER
+  - name: ISR
+    description: interrupt status register
+    byte_offset: 772
+    fieldset: ISR
+  - name: ICR
+    description: interrupt clear register
+    byte_offset: 776
+    fieldset: ICR
+fieldset/CR:
+  description: Control register
+  fields:
+  - name: EN
+    description: AES enable
+    bit_offset: 0
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection
+    bit_offset: 1
+    bit_size: 2
+    enum: DATATYPE
+  - name: MODE
+    description: Operating mode
+    bit_offset: 3
+    bit_size: 2
+    enum: MODE
+  - name: CHMOD
+    description: Chaining mode selection
+    bit_offset:
+    - start: 5
+      end: 6
+    - start: 16
+      end: 16
+    bit_size: 3
+    enum: CHMOD
+  - name: DMAINEN
+    description: Enable DMA management of data input phase
+    bit_offset: 11
+    bit_size: 1
+  - name: DMAOUTEN
+    description: Enable DMA management of data output phase
+    bit_offset: 12
+    bit_size: 1
+  - name: GCMPH
+    description: GCM or CCM phase selection
+    bit_offset: 13
+    bit_size: 2
+    enum: GCMPH
+  - name: KEYSIZE
+    description: Key size selection
+    bit_offset: 18
+    bit_size: 1
+  - name: NPBLB
+    description: Number of padding bytes in last block of payload
+    bit_offset: 20
+    bit_size: 4
+  - name: KMOD
+    description: Key mode selection
+    bit_offset: 24
+    bit_size: 2
+  - name: IPRST
+    description: AES peripheral software reset
+    bit_offset: 31
+    bit_size: 1
+fieldset/ICR:
+  description: Interrupt clear register
+  fields:
+  - name: RWEIF
+    description: Read or write error interrupt flag clear
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIF
+    description: Key error interrupt flag clear
+    bit_offset: 2
+    bit_size: 1
+fieldset/IER:
+  description: Interrupt enable register
+  fields:
+  - name: CCFIE
+    description: Computation complete flag interrupt enable
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIE
+    description: Read or write error interrupt enable
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIE
+    description: Key error interrupt enable
+    bit_offset: 2
+    bit_size: 1
+fieldset/ISR:
+  description: Interrupt status register
+  fields:
+  - name: CCF
+    description: Computation complete flag
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIF
+    description: Read or write error interrupt flag
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIF
+    description: Key error interrupt flag
+    bit_offset: 2
+    bit_size: 1
+fieldset/SR:
+  description: Status register
+  fields:
+  - name: CCF
+    description: Computation complete flag
+    bit_offset: 0
+    bit_size: 1
+  - name: RDERR
+    description: Read error flag
+    bit_offset: 1
+    bit_size: 1
+  - name: WRERR
+    description: Write error flag
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy flag
+    bit_offset: 3
+    bit_size: 1
+  - name: KEYVALID
+    description: Key valid flag
+    bit_offset: 7
+    bit_size: 1
+enum/CHMOD:
+  bit_size: 3
+  variants:
+  - name: ECB
+    description: Electronic codebook
+    value: 0
+  - name: CBC
+    description: Cipher-block chaining
+    value: 1
+  - name: CTR
+    description: Counter mode
+    value: 2
+  - name: GCM_GMAC
+    description: Galois counter mode and Galois message authentication code
+    value: 3
+  - name: CCM
+    description: Counter with CBC-MAC
+    value: 4
+enum/DATATYPE:
+  bit_size: 2
+  variants:
+  - name: None
+    description: Word
+    value: 0
+  - name: HalfWord
+    description: Half-word (16-bit)
+    value: 1
+  - name: Byte
+    description: Byte (8-bit)
+    value: 2
+  - name: Bit
+    description: Bit
+    value: 3
+enum/GCMPH:
+  bit_size: 2
+  variants:
+  - name: Init phase
+    description: Init phase
+    value: 0
+  - name: Header phase
+    description: Header phase
+    value: 1
+  - name: Payload phase
+    description: Payload phase
+    value: 2
+  - name: Final phase
+    description: Final phase
+    value: 3
+enum/MODE:
+  bit_size: 2
+  variants:
+  - name: Mode1
+    description: Encryption
+    value: 0
+  - name: Mode2
+    description: Key derivation (or key preparation for ECB/CBC decryption)
+    value: 1
+  - name: Mode3
+    description: Decryption
+    value: 2
diff --git a/data/registers/pka_v1a.yaml b/data/registers/pka_v1a.yaml
new file mode 100644
index 0000000..bebc11a
--- /dev/null
+++ b/data/registers/pka_v1a.yaml
@@ -0,0 +1,106 @@
+block/PKA:
+  description: Private key accelerator.
+  items:
+  - name: CR
+    description: PKA control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: PKA status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: CLRFR
+    description: PKA clear flag register.
+    byte_offset: 8
+    fieldset: CLRFR
+fieldset/CLRFR:
+  description: PKA clear flag register.
+  fields:
+  - name: PROCENDFC
+    description: Clear PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRFC
+    description: Clear PKA RAM error flag.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRFC
+    description: Clear address error flag.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRFC
+    description: Clear operation error flag.
+    bit_offset: 21
+    bit_size: 1
+fieldset/CR:
+  description: PKA control register.
+  fields:
+  - name: EN
+    description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.
+    bit_offset: 0
+    bit_size: 1
+  - name: START
+    description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.
+    bit_offset: 1
+    bit_size: 1
+  - name: MODE
+    description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.
+    bit_offset: 8
+    bit_size: 6
+  - name: PROCENDIE
+    description: End of operation interrupt enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRIE
+    description: RAM error interrupt enable.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRIE
+    description: Address error interrupt enable.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRIE
+    description: Operation error interrupt enable.
+    bit_offset: 21
+    bit_size: 1
+fieldset/SR:
+  description: PKA status register.
+  fields:
+  - name: INITOK
+    description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0.
+    bit_offset: 0
+    bit_size: 1
+  - name: LMF
+    description: Limited mode flag This bit is updated when EN bit in PKA_CR is set.
+    bit_offset: 1
+    bit_size: 1
+    enum: LMF
+  - name: BUSY
+    description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).
+    bit_offset: 16
+    bit_size: 1
+  - name: PROCENDF
+    description: PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRF
+    description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRF
+    description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRF
+    description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR.
+    bit_offset: 21
+    bit_size: 1
+enum/LMF:
+  bit_size: 1
+  variants:
+  - name: All
+    description: All values documented in MODE bitfield can be used.
+    value: 0
+  - name: Limited
+    description: Only ECDSA verification (MODE = 0x26) is supported by the PKA.
+    value: 1
diff --git a/data/registers/pka_v1b.yaml b/data/registers/pka_v1b.yaml
new file mode 100644
index 0000000..51a1b24
--- /dev/null
+++ b/data/registers/pka_v1b.yaml
@@ -0,0 +1,92 @@
+block/PKA:
+  description: Private key accelerator.
+  items:
+  - name: CR
+    description: PKA control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: PKA status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: CLRFR
+    description: PKA clear flag register.
+    byte_offset: 8
+    fieldset: CLRFR
+fieldset/CLRFR:
+  description: PKA clear flag register.
+  fields:
+  - name: PROCENDFC
+    description: Clear PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRFC
+    description: Clear PKA RAM error flag.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRFC
+    description: Clear address error flag.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRFC
+    description: Clear operation error flag.
+    bit_offset: 21
+    bit_size: 1
+fieldset/CR:
+  description: PKA control register.
+  fields:
+  - name: EN
+    description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.
+    bit_offset: 0
+    bit_size: 1
+  - name: START
+    description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.
+    bit_offset: 1
+    bit_size: 1
+  - name: MODE
+    description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.
+    bit_offset: 8
+    bit_size: 6
+  - name: PROCENDIE
+    description: End of operation interrupt enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRIE
+    description: RAM error interrupt enable.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRIE
+    description: Address error interrupt enable.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRIE
+    description: Operation error interrupt enable.
+    bit_offset: 21
+    bit_size: 1
+fieldset/SR:
+  description: PKA status register.
+  fields:
+  - name: INITOK
+    description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0.
+    bit_offset: 0
+    bit_size: 1
+  - name: BUSY
+    description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).
+    bit_offset: 16
+    bit_size: 1
+  - name: PROCENDF
+    description: PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRF
+    description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRF
+    description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.
+    bit_offset: 20
+    bit_size: 1
+  - name: OPERRF
+    description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR.
+    bit_offset: 21
+    bit_size: 1
diff --git a/data/registers/pka_v1c.yaml b/data/registers/pka_v1c.yaml
new file mode 100644
index 0000000..1c08919
--- /dev/null
+++ b/data/registers/pka_v1c.yaml
@@ -0,0 +1,76 @@
+block/PKA:
+  description: Private key accelerator.
+  items:
+  - name: CR
+    description: PKA control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: PKA status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: CLRFR
+    description: PKA clear flag register.
+    byte_offset: 8
+    fieldset: CLRFR
+fieldset/CLRFR:
+  description: PKA clear flag register.
+  fields:
+  - name: PROCENDFC
+    description: Clear PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRFC
+    description: Clear PKA RAM error flag.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRFC
+    description: Clear address error flag.
+    bit_offset: 20
+    bit_size: 1
+fieldset/CR:
+  description: PKA control register.
+  fields:
+  - name: EN
+    description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.
+    bit_offset: 0
+    bit_size: 1
+  - name: START
+    description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.
+    bit_offset: 1
+    bit_size: 1
+  - name: MODE
+    description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.
+    bit_offset: 8
+    bit_size: 6
+  - name: PROCENDIE
+    description: End of operation interrupt enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRIE
+    description: RAM error interrupt enable.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRIE
+    description: Address error interrupt enable.
+    bit_offset: 20
+    bit_size: 1
+fieldset/SR:
+  description: PKA status register.
+  fields:
+  - name: BUSY
+    description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).
+    bit_offset: 16
+    bit_size: 1
+  - name: PROCENDF
+    description: PKA End of Operation flag.
+    bit_offset: 17
+    bit_size: 1
+  - name: RAMERRF
+    description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.
+    bit_offset: 19
+    bit_size: 1
+  - name: ADDRERRF
+    description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.
+    bit_offset: 20
+    bit_size: 1
diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml
index 3a09f85..69230d0 100644
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@@ -345,8 +345,8 @@ fieldset/AHB2ENR:
     description: DCMI peripheral clock
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTEN
-    description: CRYPT peripheral clock enable
+  - name: CRYPEN
+    description: CRYP peripheral clock enable
     bit_offset: 4
     bit_size: 1
   - name: HASHEN
@@ -392,8 +392,8 @@ fieldset/AHB2LPENR:
     description: DCMI peripheral clock enable during csleep mode
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTLPEN
-    description: CRYPT peripheral clock enable during CSleep mode
+  - name: CRYPLPEN
+    description: CRYP peripheral clock enable during CSleep mode
     bit_offset: 4
     bit_size: 1
   - name: HASHLPEN
@@ -439,8 +439,8 @@ fieldset/AHB2RSTR:
     description: DCMI block reset
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTRST
-    description: Cryptography block reset
+  - name: CRYPRST
+    description: CRYPography block reset
     bit_offset: 4
     bit_size: 1
   - name: HASHRST
diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml
index 2108340..38ae54b 100644
--- a/data/registers/rcc_h7rm0433.yaml
+++ b/data/registers/rcc_h7rm0433.yaml
@@ -425,8 +425,8 @@ fieldset/AHB2ENR:
     description: DCMI peripheral clock
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTEN
-    description: CRYPT peripheral clock enable
+  - name: CRYPEN
+    description: CRYP peripheral clock enable
     bit_offset: 4
     bit_size: 1
   - name: HASHEN
@@ -468,8 +468,8 @@ fieldset/AHB2LPENR:
     description: DCMI peripheral clock enable during csleep mode
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTLPEN
-    description: CRYPT peripheral clock enable during CSleep mode
+  - name: CRYPLPEN
+    description: CRYP peripheral clock enable during CSleep mode
     bit_offset: 4
     bit_size: 1
   - name: HASHLPEN
@@ -511,8 +511,8 @@ fieldset/AHB2RSTR:
     description: DCMI block reset
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTRST
-    description: Cryptography block reset
+  - name: CRYPRST
+    description: CRYPography block reset
     bit_offset: 4
     bit_size: 1
   - name: HASHRST
@@ -1872,8 +1872,8 @@ fieldset/C1_AHB2ENR:
     description: DCMI peripheral clock
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTEN
-    description: CRYPT peripheral clock enable
+  - name: CRYPEN
+    description: CRYP peripheral clock enable
     bit_offset: 4
     bit_size: 1
   - name: HASHEN
@@ -1907,8 +1907,8 @@ fieldset/C1_AHB2LPENR:
     description: DCMI peripheral clock enable during csleep mode
     bit_offset: 0
     bit_size: 1
-  - name: CRYPTLPEN
-    description: CRYPT peripheral clock enable during CSleep mode
+  - name: CRYPLPEN
+    description: CRYP peripheral clock enable during CSleep mode
     bit_offset: 4
     bit_size: 1
   - name: HASHLPEN
diff --git a/data/registers/saes_v1a.yaml b/data/registers/saes_v1a.yaml
new file mode 100644
index 0000000..44b4d83
--- /dev/null
+++ b/data/registers/saes_v1a.yaml
@@ -0,0 +1,308 @@
+block/SAES:
+  description: Secure advanced encryption standard hardware accelerator.
+  items:
+  - name: CR
+    description: SAES control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: SAES status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: DINR
+    description: SAES data input register.
+    byte_offset: 8
+  - name: DOUTR
+    description: SAES data output register.
+    byte_offset: 12
+  - name: KEYR
+    description: SAES key register 0.
+    array:
+      offsets:
+      - 0
+      - 4
+      - 8
+      - 12
+      - 32
+      - 36
+      - 40
+      - 44
+    byte_offset: 16
+  - name: IVR
+    description: SAES initialization vector register 0.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 32
+  - name: SUSPR
+    description: SAES suspend registers.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 64
+  - name: IER
+    description: SAES interrupt enable register.
+    byte_offset: 768
+    fieldset: IER
+  - name: ISR
+    description: SAES interrupt status register.
+    byte_offset: 772
+    fieldset: ISR
+  - name: ICR
+    description: SAES interrupt clear register.
+    byte_offset: 776
+    fieldset: ICR
+fieldset/CR:
+  description: SAES control register.
+  fields:
+  - name: EN
+    description: 'SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN.'
+    bit_offset: 0
+    bit_size: 1
+  - name: DATATYPE
+    description: 'Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 1
+    bit_size: 2
+    enum: DATATYPE
+  - name: MODE
+    description: 'SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 3
+    bit_size: 2
+    enum: MODE
+  - name: CHMOD
+    description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset:
+    - start: 5
+      end: 6
+    - start: 16
+      end: 16
+    bit_size: 3
+    enum: CHMOD
+  - name: DMAINEN
+    description: 'DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).'
+    bit_offset: 11
+    bit_size: 1
+  - name: DMAOUTEN
+    description: 'DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).'
+    bit_offset: 12
+    bit_size: 1
+  - name: GCMPH
+    description: 'GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).'
+    bit_offset: 13
+    bit_size: 2
+    enum: GCMPH
+  - name: KEYSIZE
+    description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 18
+    bit_size: 1
+    enum: KEYSIZE
+  - name: KEYPROT
+    description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.
+    bit_offset: 19
+    bit_size: 1
+  - name: NPBLB
+    description: 'Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...'
+    bit_offset: 20
+    bit_size: 4
+  - name: KMOD
+    description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 24
+    bit_size: 2
+    enum: KMOD
+  - name: KSHAREID
+    description: 'Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 26
+    bit_size: 2
+    enum: KSHAREID
+  - name: KEYSEL
+    description: 'Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 28
+    bit_size: 3
+    enum: KEYSEL
+  - name: IPRST
+    description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers.
+    bit_offset: 31
+    bit_size: 1
+fieldset/ICR:
+  description: SAES interrupt clear register.
+  fields:
+  - name: CCF
+    description: Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers.
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIF
+    description: Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register.
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIF
+    description: Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register.
+    bit_offset: 2
+    bit_size: 1
+  - name: RNGEIF
+    description: RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register.
+    bit_offset: 3
+    bit_size: 1
+fieldset/IER:
+  description: SAES interrupt enable register.
+  fields:
+  - name: CCFIE
+    description: Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set.
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIE
+    description: Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set.
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIE
+    description: Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set.
+    bit_offset: 2
+    bit_size: 1
+  - name: RNGEIE
+    description: RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set.
+    bit_offset: 3
+    bit_size: 1
+fieldset/ISR:
+  description: SAES interrupt status register.
+  fields:
+  - name: CCF
+    description: 'Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.'
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIF
+    description: Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected.
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIF
+    description: 'Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.'
+    bit_offset: 2
+    bit_size: 1
+  - name: RNGEIF
+    description: RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral.
+    bit_offset: 3
+    bit_size: 1
+fieldset/SR:
+  description: SAES status register.
+  fields:
+  - name: RDERR
+    description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.'
+    bit_offset: 1
+    bit_size: 1
+  - name: WRERR
+    description: 'Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored.'
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: 'Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase.'
+    bit_offset: 3
+    bit_size: 1
+  - name: KEYVALID
+    description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to.
+    bit_offset: 7
+    bit_size: 1
+enum/CHMOD:
+  bit_size: 3
+  variants:
+  - name: ECB
+    description: Electronic codebook
+    value: 0
+  - name: CBC
+    description: Cipher-block chaining
+    value: 1
+  - name: CTR
+    description: Counter mode
+    value: 2
+  - name: GCM_GMAC
+    description: Galois counter mode and Galois message authentication code
+    value: 3
+  - name: CCM
+    description: Counter with CBC-MAC
+    value: 4
+enum/DATATYPE:
+  bit_size: 2
+  variants:
+  - name: None
+    description: No swapping (32-bit data).
+    value: 0
+  - name: HalfWord
+    description: Half-word swapping (16-bit data)
+    value: 1
+  - name: Byte
+    description: Byte swapping (8-bit data)
+    value: 2
+  - name: Bit
+    description: Bit-level swapping
+    value: 3
+enum/GCMPH:
+  bit_size: 2
+  variants:
+  - name: InitPhase
+    description: Initialization phase
+    value: 0
+  - name: HeaderPhase
+    description: Header phase
+    value: 1
+  - name: PayloadPhase
+    description: Payload phase
+    value: 2
+  - name: FinalPhase
+    description: Final phase
+    value: 3
+enum/KEYSEL:
+  bit_size: 3
+  variants:
+  - name: SoftwareKey
+    description: Software key, loaded in key registers SAES_KEYx
+    value: 0
+  - name: DHUK
+    description: Derived hardware unique key
+    value: 1
+  - name: BHK
+    description: Boot hardware key
+    value: 2
+  - name: XOR_DHUK_BHK
+    description: XOR of DHUK and BHK
+    value: 4
+enum/KEYSIZE:
+  bit_size: 1
+  variants:
+  - name: Bits128
+    description: 128-bit
+    value: 0
+  - name: Bits256
+    description: 256-bit
+    value: 1
+enum/KMOD:
+  bit_size: 2
+  variants:
+  - name: Normal
+    description: AES peripheral
+    value: 0
+  - name: WrappedKey
+    description: |-
+      Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or
+      decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is
+      automatically loaded into SAES key registers after a successful decryption process.
+    value: 1
+  - name: SharedKey
+    description: |-
+      Shared key mode. After a successful decryption process (unwrapping), SAES key registers are
+      shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while
+      KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR
+      register is automatically loaded into SAES key registers after a successful decryption process.
+    value: 2
+enum/KSHAREID:
+  bit_size: 2
+  variants:
+  - name: AES
+    description: AES peripheral
+    value: 0
+enum/MODE:
+  bit_size: 2
+  variants:
+  - name: Encryption
+    value: 0
+  - name: KeyDerivation
+    description: Key derivation (or key preparation), for ECB/CBC decryption only
+    value: 1
+  - name: Decryption
+    value: 2
diff --git a/data/registers/saes_v1b.yaml b/data/registers/saes_v1b.yaml
new file mode 100644
index 0000000..26881aa
--- /dev/null
+++ b/data/registers/saes_v1b.yaml
@@ -0,0 +1,288 @@
+block/SAES:
+  description: Secure advanced encryption standard hardware accelerator.
+  items:
+  - name: CR
+    description: SAES control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: SAES status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: DINR
+    description: SAES data input register.
+    byte_offset: 8
+  - name: DOUTR
+    description: SAES data output register.
+    byte_offset: 12
+  - name: KEYR
+    description: SAES key register 0.
+    array:
+      offsets:
+      - 0
+      - 4
+      - 8
+      - 12
+      - 32
+      - 36
+      - 40
+      - 44
+    byte_offset: 16
+  - name: IVR
+    description: SAES initialization vector register 0.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 32
+  - name: SUSPR
+    description: SAES suspend registers.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 64
+  - name: IER
+    description: SAES interrupt enable register.
+    byte_offset: 768
+    fieldset: IER
+  - name: ISR
+    description: SAES interrupt status register.
+    byte_offset: 772
+    fieldset: ISR
+  - name: ICR
+    description: SAES interrupt clear register.
+    byte_offset: 776
+    fieldset: ICR
+fieldset/CR:
+  description: SAES control register.
+  fields:
+  - name: EN
+    description: 'SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN.'
+    bit_offset: 0
+    bit_size: 1
+  - name: DATATYPE
+    description: 'Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 1
+    bit_size: 2
+    enum: DATATYPE
+  - name: MODE
+    description: 'SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 3
+    bit_size: 2
+    enum: MODE
+  - name: CHMOD
+    description: 'Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset:
+    - start: 5
+      end: 6
+    - start: 16
+      end: 16
+    bit_size: 3
+    enum: CHMOD
+  - name: DMAINEN
+    description: 'DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).'
+    bit_offset: 11
+    bit_size: 1
+  - name: DMAOUTEN
+    description: 'DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).'
+    bit_offset: 12
+    bit_size: 1
+  - name: KEYSIZE
+    description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 18
+    bit_size: 1
+    enum: KEYSIZE
+  - name: KEYPROT
+    description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.
+    bit_offset: 19
+    bit_size: 1
+  - name: KMOD
+    description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 24
+    bit_size: 2
+    enum: KMOD
+  - name: KSHAREID
+    description: 'Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 26
+    bit_size: 2
+    enum: KSHAREID
+  - name: KEYSEL
+    description: 'Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.'
+    bit_offset: 28
+    bit_size: 3
+    enum: KEYSEL
+  - name: IPRST
+    description: SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers.
+    bit_offset: 31
+    bit_size: 1
+fieldset/ICR:
+  description: SAES interrupt clear register.
+  fields:
+  - name: CCF
+    description: Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers.
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIF
+    description: Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register.
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIF
+    description: Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register.
+    bit_offset: 2
+    bit_size: 1
+  - name: RNGEIF
+    description: RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register.
+    bit_offset: 3
+    bit_size: 1
+fieldset/IER:
+  description: SAES interrupt enable register.
+  fields:
+  - name: CCFIE
+    description: Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set.
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIE
+    description: Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set.
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIE
+    description: Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set.
+    bit_offset: 2
+    bit_size: 1
+  - name: RNGEIE
+    description: RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set.
+    bit_offset: 3
+    bit_size: 1
+fieldset/ISR:
+  description: SAES interrupt status register.
+  fields:
+  - name: CCF
+    description: 'Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.'
+    bit_offset: 0
+    bit_size: 1
+  - name: RWEIF
+    description: Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected.
+    bit_offset: 1
+    bit_size: 1
+  - name: KEIF
+    description: 'Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.'
+    bit_offset: 2
+    bit_size: 1
+  - name: RNGEIF
+    description: RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral.
+    bit_offset: 3
+    bit_size: 1
+fieldset/SR:
+  description: SAES status register.
+  fields:
+  - name: CCF
+    description: Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register.
+    bit_offset: 1
+    bit_size: 1
+  - name: RDERR
+    description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.'
+    bit_offset: 1
+    bit_size: 1
+  - name: WRERR
+    description: 'Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored.'
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: 'Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase.'
+    bit_offset: 3
+    bit_size: 1
+  - name: KEYVALID
+    description: Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to.
+    bit_offset: 7
+    bit_size: 1
+enum/CHMOD:
+  bit_size: 3
+  variants:
+  - name: ECB
+    description: Electronic codebook
+    value: 0
+  - name: CBC
+    description: Cipher-block chaining
+    value: 1
+  - name: CTR
+    description: Counter mode
+    value: 2
+  - name: GCM_GMAC
+    description: Galois counter mode and Galois message authentication code
+    value: 3
+  - name: CCM
+    description: Counter with CBC-MAC
+    value: 4
+enum/DATATYPE:
+  bit_size: 2
+  variants:
+  - name: None
+    description: No swapping (32-bit data).
+    value: 0
+  - name: HalfWord
+    description: Half-word swapping (16-bit data)
+    value: 1
+  - name: Byte
+    description: Byte swapping (8-bit data)
+    value: 2
+  - name: Bit
+    description: Bit-level swapping
+    value: 3
+enum/KEYSEL:
+  bit_size: 3
+  variants:
+  - name: SoftwareKey
+    description: Software key, loaded in key registers SAES_KEYx
+    value: 0
+  - name: DHUK
+    description: Derived hardware unique key
+    value: 1
+  - name: BHK
+    description: Boot hardware key
+    value: 2
+  - name: XOR_DHUK_BHK
+    description: XOR of DHUK and BHK
+    value: 4
+enum/KEYSIZE:
+  bit_size: 1
+  variants:
+  - name: Bits128
+    description: 128-bit
+    value: 0
+  - name: Bits256
+    description: 256-bit
+    value: 1
+enum/KMOD:
+  bit_size: 2
+  variants:
+  - name: Normal
+    description: AES peripheral
+    value: 0
+  - name: WrappedKey
+    description: |-
+      Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or
+      decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is
+      automatically loaded into SAES key registers after a successful decryption process.
+    value: 1
+  - name: SharedKey
+    description: |-
+      Shared key mode. After a successful decryption process (unwrapping), SAES key registers are
+      shared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while
+      KMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR
+      register is automatically loaded into SAES key registers after a successful decryption process.
+    value: 2
+enum/KSHAREID:
+  bit_size: 2
+  variants:
+  - name: AES
+    description: AES peripheral
+    value: 0
+enum/MODE:
+  bit_size: 2
+  variants:
+  - name: Encryption
+    value: 0
+  - name: KeyDerivation
+    description: Key derivation (or key preparation), for ECB/CBC decryption only
+    value: 1
+  - name: Decryption
+    value: 2
diff --git a/stm32-data-gen/Cargo.toml b/stm32-data-gen/Cargo.toml
index ba8f21e..6ae7720 100644
--- a/stm32-data-gen/Cargo.toml
+++ b/stm32-data-gen/Cargo.toml
@@ -17,7 +17,7 @@ quick-xml = { version = "0.26.0", features = ["serialize"] }
 regex = "1.7.1"
 serde = { version = "1.0.157", features = ["derive"] }
 serde_yaml = "0.9.19"
-chiptool = { git = "https://github.com/embassy-rs/chiptool", rev="247ccbe44669ac716393247e56693a396e641e4a" }
+chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "1c198ae678ebd426751513f0deab6fbd6f8b8211" }
 serde_json = "1.0.94"
 rayon = { version = "1.7.0", optional = true }
 stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" }
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index a150000..6e981a5 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -152,9 +152,12 @@ impl PeriMatcher {
             ("STM32L1.*:AES:.*", ("aes", "v1", "AES")),
             ("STM32L4.*:AES:.*", ("aes", "v1", "AES")),
             ("STM32L5.*:AES:.*", ("aes", "v2", "AES")),
-            ("STM32U5.*:AES:.*", ("aes", "u5", "AES")),
             ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")),
             ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")),
+            ("STM32U5.*:AES:.*", ("aes", "v3a", "AES")),
+            ("STM32(H5|WBA).*:AES:.*", ("aes", "v3b", "AES")),
+            ("STM32(H5|WBA).*:SAES:.*", ("saes", "v1a", "SAES")),
+            ("STM32U5.*:SAES:.*", ("saes", "v1b", "SAES")),
             (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")),
             (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")),
             (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")),
@@ -622,6 +625,9 @@ impl PeriMatcher {
             ("STM32H5.*:VREFBUF:.*", ("vrefbuf", "v2a2", "VREFBUF")),
             ("STM32G4.*:VREFBUF:.*", ("vrefbuf", "v2b", "VREFBUF")),
             ("STM32H5.*:I3C:.*", ("i3c", "v1", "I3C")),
+            ("STM32(H5|WBA).*:PKA:.*", ("pka", "v1a", "PKA")),
+            ("STM32U5.*:PKA:.*", ("pka", "v1b", "PKA")),
+            ("STM32(L5|WL|WB).*:PKA:.*", ("pka", "v1c", "PKA")),
         ];
 
         Self {
diff --git a/stm32-metapac-gen/Cargo.toml b/stm32-metapac-gen/Cargo.toml
index f9a12fb..60eddef 100644
--- a/stm32-metapac-gen/Cargo.toml
+++ b/stm32-metapac-gen/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 regex = "1.7.1"
-chiptool = { git = "https://github.com/embassy-rs/chiptool", rev="247ccbe44669ac716393247e56693a396e641e4a" }
+chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "1c198ae678ebd426751513f0deab6fbd6f8b8211" }
 serde = { version = "1.0.157", features = [ "derive" ] }
 serde_json = "1.0.94"
 proc-macro2 = "1.0.52"
diff --git a/stm32-metapac-gen/src/data.rs b/stm32-metapac-gen/src/data.rs
index 9e3549d..dc24d63 100644
--- a/stm32-metapac-gen/src/data.rs
+++ b/stm32-metapac-gen/src/data.rs
@@ -158,7 +158,10 @@ pub mod ir {
         pub items: Vec<BlockItem>,
     }
 
-    #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
+    // Notice:
+    // BlockItem has custom Debug implement,
+    // when modify the struct, make sure Debug impl reflect the change.
+    #[derive(Eq, PartialEq, Clone, Deserialize)]
     pub struct BlockItem {
         pub name: String,
         pub description: Option<String>,
@@ -169,6 +172,20 @@ pub mod ir {
         pub inner: BlockItemInner,
     }
 
+    // Notice:
+    // Debug implement AFFECT OUTPUT METAPAC, modify with caution
+    impl std::fmt::Debug for BlockItem {
+        fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+            f.debug_struct("BlockItem")
+                .field("name", &self.name)
+                .field("description", &self.description)
+                .field("array", &self.array)
+                .field("byte_offset", &format_args!("{:#x}", self.byte_offset))
+                .field("inner", &self.inner)
+                .finish()
+        }
+    }
+
     #[derive(EnumDebug, Eq, PartialEq, Clone, Deserialize)]
     pub enum BlockItemInner {
         Block(BlockItemBlock),
@@ -274,7 +291,10 @@ pub struct Chip {
     pub packages: Vec<Package>,
 }
 
-#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
+// Notice:
+// MemoryRegion has custom Debug implement,
+// when modify the struct, make sure Debug impl reflect the change.
+#[derive(Eq, PartialEq, Clone, Deserialize)]
 pub struct MemoryRegion {
     pub name: String,
     pub kind: MemoryRegionKind,
@@ -283,6 +303,20 @@ pub struct MemoryRegion {
     pub settings: Option<FlashSettings>,
 }
 
+// Notice:
+// Debug implement AFFECT OUTPUT METAPAC, modify with caution
+impl std::fmt::Debug for MemoryRegion {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        f.debug_struct("MemoryRegion")
+            .field("name", &self.name)
+            .field("kind", &self.kind)
+            .field("address", &format_args!("{:#x}", self.address))
+            .field("size", &self.size)
+            .field("settings", &self.settings)
+            .finish()
+    }
+}
+
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
 pub struct FlashSettings {
     pub erase_size: u32,
@@ -320,7 +354,10 @@ pub struct Package {
     pub package: String,
 }
 
-#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
+// Notice:
+// Peripheral has custom Debug implement,
+// when modify struct, make sure Debug impl reflect the change.
+#[derive(Eq, PartialEq, Clone, Deserialize)]
 pub struct Peripheral {
     pub name: String,
     pub address: u64,
@@ -336,6 +373,22 @@ pub struct Peripheral {
     pub interrupts: Vec<PeripheralInterrupt>,
 }
 
+// Notice:
+// Debug implement AFFECT OUTPUT METAPAC, modify with caution
+impl std::fmt::Debug for Peripheral {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        f.debug_struct("Peripheral")
+            .field("name", &self.name)
+            .field("address", &format_args!("{:#x}", self.address))
+            .field("registers", &self.registers)
+            .field("rcc", &self.rcc)
+            .field("pins", &self.pins)
+            .field("dma_channels", &self.dma_channels)
+            .field("interrupts", &self.interrupts)
+            .finish()
+    }
+}
+
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
 pub struct PeripheralInterrupt {
     pub signal: String,
diff --git a/transforms/AES.yaml b/transforms/AES.yaml
new file mode 100644
index 0000000..b8a13c8
--- /dev/null
+++ b/transforms/AES.yaml
@@ -0,0 +1,19 @@
+transforms:
+  - !DeleteFieldsets
+    from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$
+
+  - !MakeRegisterArray
+    blocks: AES
+    from: ^(IVR)\d$
+    to: $1
+
+  - !MakeRegisterArray
+    blocks: AES
+    allow_cursed: true
+    from: ^(KEYR)\d$
+    to: $1
+
+  - !MakeRegisterArray
+    blocks: AES
+    from: ^(SUSP)\d(R)$
+    to: $1$2
diff --git a/transforms/SAES.yaml b/transforms/SAES.yaml
new file mode 100644
index 0000000..3739152
--- /dev/null
+++ b/transforms/SAES.yaml
@@ -0,0 +1,19 @@
+transforms:
+  - !DeleteFieldsets
+    from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$
+
+  - !MakeRegisterArray
+    blocks: SAES
+    from: ^(IVR)\d$
+    to: $1
+
+  - !MakeRegisterArray
+    blocks: SAES
+    allow_cursed: true
+    from: ^(KEYR)\d$
+    to: $1
+
+  - !MakeRegisterArray
+    blocks: SAES
+    from: ^(SUSP)\d(R)$
+    to: $1$2