From 675a67c3afc53443acdbce109cb54dade757484d Mon Sep 17 00:00:00 2001 From: Adin Ackerman Date: Tue, 30 Jan 2024 15:57:55 -0800 Subject: [PATCH 1/2] add comparators to G0 and G4 --- data/registers/comp_v1.yaml | 103 ++++++++++++++++++++++++++++++++++++ data/registers/comp_v2.yaml | 87 ++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 2 + 3 files changed, 192 insertions(+) create mode 100644 data/registers/comp_v1.yaml create mode 100644 data/registers/comp_v2.yaml diff --git a/data/registers/comp_v1.yaml b/data/registers/comp_v1.yaml new file mode 100644 index 0000000..c3e29d9 --- /dev/null +++ b/data/registers/comp_v1.yaml @@ -0,0 +1,103 @@ +block/COMP: + description: Comparator v1. (RM0444 18) + items: + - name: CSR + description: Comparator control and status register. + byte_offset: 0 + fieldset: CSR +fieldset/CSR: + description: Comparator control and status register. + fields: + - name: EN + description: COMP enable bit. + bit_offset: 0 + bit_size: 1 + - name: INMSEL + description: Comparator signal selector for inverting input INM. + bit_offset: 4 + bit_size: 4 + - name: INPSEL + description: Comparator signal selector for non-inverting input INP. + bit_offset: 8 + bit_size: 2 + - name: WINMODE + description: Comparator non-inverting input selector for window mode. + bit_offset: 11 + bit_size: 1 + - name: WINOUT + description: Comparator output selector. + bit_offset: 14 + bit_size: 1 + - name: POLARITY + description: Comparator polarity selector. + bit_offset: 15 + bit_size: 1 + enum: POLARITY + - name: HYST + description: Comparator hysteresis selector. + bit_offset: 16 + bit_size: 2 + enum: HYST + - name: PWRMODE + description: Comparator power mode selector. + bit_offset: 18 + bit_size: 2 + enum: PWRMODE + - name: BLANKSEL + description: Comparator blanking source selector. + bit_offset: 20 + bit_size: 5 + enum: BLANKSEL + - name: VALUE_DO_NOT_SET + description: Comparator output status. (READ ONLY) + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: CSR register lock. + bit_offset: 31 + bit_size: 1 +enum/POLARITY: + bit_size: 1 + variants: + - name: NonInverted + value: 0 + - name: Inverted + value: 1 +enum/HYST: + bit_size: 2 + variants: + - name: None + value: 0 + - name: Low + value: 1 + - name: Medium + value: 2 + - name: High + value: 3 +enum/PWRMODE: + bit_size: 2 + variants: + - name: HighSpeed + value: 0 + - name: MediumSpeed + value: 1 +enum/BLANKSEL: + bit_size: 5 + variants: + - name: None + value: 0 + - name: Tim1Oc4 + description: TIM1 OC4 + value: 1 + - name: Tim1Oc5 + description: TIM1 OC5 + value: 2 + - name: Tim2Oc3 + description: TIM2 OC3 + value: 4 + - name: Tim3Oc3 + description: TIM3 OC3 + value: 8 + - name: Tim15Oc2 + description: TIM15 OC2 + value: 16 diff --git a/data/registers/comp_v2.yaml b/data/registers/comp_v2.yaml new file mode 100644 index 0000000..0bef876 --- /dev/null +++ b/data/registers/comp_v2.yaml @@ -0,0 +1,87 @@ +block/COMP: + description: Comparator v2. (RM0440 24) + items: + - name: CSR + description: Comparator control and status register. + byte_offset: 0 + fieldset: CSR +fieldset/CSR: + description: Comparator control and status register. + fields: + - name: EN + description: COMP enable bit. + bit_offset: 0 + bit_size: 1 + - name: INMSEL + description: Comparator signal selector for inverting input INM. (RM0440 24.3.2 Table 197) + bit_offset: 4 + bit_size: 3 + - name: INPSEL + description: Comparator signal selector for non-inverting input INP. (RM0440 24.3.2 Table 196) + bit_offset: 8 + bit_size: 1 + - name: POLARITY + description: Comparator polarity selector. + bit_offset: 15 + bit_size: 1 + enum: POLARITY + - name: HYST + description: Comparator hysteresis selector. + bit_offset: 16 + bit_size: 3 + enum: HYST + - name: BLANKSEL + description: Comparator blanking source selector. (RM0440 24.3.6 Table 198) + bit_offset: 19 + bit_size: 3 + - name: BRGEN + description: Vrefint resistor bridge enable. (RM0440 24.6) + bit_offset: 22 + bit_size: 1 + - name: SCALEN + description: Vrefint scaled input enable. (RM0440 24.6) + bit_offset: 23 + bit_size: 1 + - name: VALUE_DO_NOT_SET + description: Comparator output status. (READ ONLY) + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: CSR register lock. + bit_offset: 31 + bit_size: 1 +enum/POLARITY: + bit_size: 1 + variants: + - name: NonInverted + description: Non-inverted polarity + value: 0 + - name: Inverted + description: Inverted polarity + value: 1 +enum/HYST: + bit_size: 3 + variants: + - name: None + value: 0 + - name: Hyst10m + description: 10mV hysteresis + value: 1 + - name: Hyst20m + description: 20mV hysteresis + value: 2 + - name: Hyst30m + description: 30mV hysteresis + value: 3 + - name: Hyst40m + description: 40mV hysteresis + value: 4 + - name: Hyst50m + description: 50mV hysteresis + value: 5 + - name: Hyst60m + description: 60mV hysteresis + value: 6 + - name: Hyst70m + description: 70mV hysteresis + value: 7 \ No newline at end of file diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 77f3b5a..7806757 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -523,6 +523,8 @@ impl PeriMatcher { ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")), ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")), ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")), + ("STM32G0.*1.*:.*:COMP:.*", ("comp", "v1", "COMP")), + ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")), ]; Self { From ee4b4abcc48d32f850f55f04bdddf0a343efea7f Mon Sep 17 00:00:00 2001 From: Adin Ackerman Date: Tue, 30 Jan 2024 18:32:48 -0800 Subject: [PATCH 2/2] update g0 regex for single character --- stm32-data-gen/src/chips.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index dfc89c8..67a84f6 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -536,7 +536,7 @@ impl PeriMatcher { (".*:CRYP:cryp1_v1_0.*", ("cryp", "v1", "CRYP")), (".*:CRYP:cryp1_v2_0.*", ("cryp", "v2", "CRYP")), (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")), - ("STM32G0.*1.*:.*:COMP:.*", ("comp", "v1", "COMP")), + ("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")), ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")), ];