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Add stm32u5 GPDMA, SPI

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This commit is contained in:
Dario Nieuwenhuis 2022-04-26 23:53:28 +02:00
parent bb6053d4ee
commit eff26e3e77
4 changed files with 1476 additions and 6 deletions
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114
data/dmamux/U5_GPDMA1.yaml Normal file
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ADC1: 0
ADC4: 1
DAC1_CH1: 2
DAC1_CH2: 3
TIM6_UPD: 4
TIM7_UPD: 5
SPI1_RX: 6
SPI1_TX: 7
SPI2_RX: 8
SPI2_TX: 9
SPI3_RX: 10
SPI3_TX: 11
I2C1_RX: 12
I2C1_TX: 13
I2C1_EVC: 14
I2C2_RX: 15
I2C2_TX: 16
I2C2_EVC: 17
I2C3_RX: 18
I2C3_TX: 19
I2C3_EVC: 20
I2C4_RX: 21
I2C4_TX: 22
I2C4_EVC: 23
USART1_RX: 24
USART1_TX: 25
USART2_RX: 26
USART2_TX: 27
USART3_RX: 28
USART3_TX: 29
UART4_RX: 30
UART4_TX: 31
UART5_RX: 32
UART5_TX: 33
LPUART1_RX: 34
LPUART1_TX: 35
SAI1_A: 36
SAI1_B: 37
SAI2_A: 38
SAI2_B: 39
OCTOSPI1: 40
OCTOSPI2: 41
TIM1_CC1: 42
TIM1_CC2: 43
TIM1_CC3: 44
TIM1_CC4: 45
TIM1_UPD: 46
TIM1_TRG: 47
TIM1_COM: 48
TIM8_CC1: 49
TIM8_CC2: 50
TIM8_CC3: 51
TIM8_CC4: 52
TIM8_UPD: 53
TIM8_TRG: 54
TIM8_COM: 55
TIM2_CC1: 56
TIM2_CC2: 57
TIM2_CC3: 58
TIM2_CC4: 59
TIM2_UPD: 60
TIM3_CC1: 61
TIM3_CC2: 62
TIM3_CC3: 63
TIM3_CC4: 64
TIM3_UPD: 65
TIM3_TRG: 66
TIM4_CC1: 67
TIM4_CC2: 68
TIM4_CC3: 69
TIM4_CC4: 70
TIM4_UPD: 71
TIM5_CC1: 72
TIM5_CC2: 73
TIM5_CC3: 74
TIM5_CC4: 75
TIM5_UPD: 76
TIM5_TRG: 77
TIM15_CC1: 78
TIM15_UPD: 79
TIM15_TRG: 80
TIM15_COM: 81
TIM16_CC1: 82
TIM16_UPD: 83
TIM17_CC1: 84
TIM17_UPD: 85
DCMI: 86
AES_IN: 87
AES_OUT: 88
HASH_IN: 89
UCPD1_TX: 90
UCPD1_RX: 91
MDF1_FLT0: 92
MDF1_FLT1: 93
MDF1_FLT2: 94
MDF1_FLT3: 95
MDF1_FLT4: 96
MDF1_FLT5: 97
ADF1_FLT0: 98
FMAC_READ: 99
FMAC_WRITE: 100
CORDIC_READ: 101
CORDIC_WRITE: 102
SAES_IN: 103
SAES_OUT: 104
LPTIM1_IC1: 105
LPTIM1_IC2: 106
LPTIM1_UE: 107
LPTIM2_IC1: 108
LPTIM2_IC2: 109
LPTIM2_UE: 110
LPTIM3_IC1: 111
LPTIM3_IC2: 112
LPTIM3_UE: 113

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data/registers/gpdma_v1.yaml Normal file
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---
block/Channel:
items:
- name: LBAR
description: GPDMA channel 15 linked-list base address register
byte_offset: 0
fieldset: CH_LBAR
- name: FCR
description: GPDMA channel 15 flag clear register
byte_offset: 12
fieldset: CH_FCR
- name: SR
description: GPDMA channel 15 status register
byte_offset: 16
fieldset: CH_SR
- name: CR
description: GPDMA channel 15 control register
byte_offset: 20
fieldset: CH_CR
- name: TR1
description: GPDMA channel 15 transfer register 1
byte_offset: 64
fieldset: CH_TR1
- name: TR2
description: GPDMA channel 15 transfer register 2
byte_offset: 68
fieldset: CH_TR2
- name: BR1
description: GPDMA channel 15 alternate block register 1
byte_offset: 72
fieldset: CH_BR1
- name: SAR
description: GPDMA channel 15 source address register
byte_offset: 76
- name: DAR
description: GPDMA channel 15 destination address register
byte_offset: 80
- name: TR3
description: GPDMA channel 15 transfer register 3
byte_offset: 84
fieldset: CH_TR3
- name: BR2
description: GPDMA channel 15 block register 2
byte_offset: 88
fieldset: CH_BR2
- name: LLR
description: GPDMA channel 15 alternate linked-list address register
byte_offset: 124
fieldset: CH_LLR
block/GPDMA:
description: GPDMA
items:
- name: SECCFGR
description: GPDMA secure configuration register
byte_offset: 0
fieldset: SECCFGR
- name: PRIVCFGR
description: GPDMA privileged configuration register
byte_offset: 4
fieldset: PRIVCFGR
- name: RCFGLOCKR
description: GPDMA configuration lock register
byte_offset: 8
fieldset: RCFGLOCKR
- name: MISR
description: GPDMA non-secure masked interrupt status register
byte_offset: 12
fieldset: MISR
- name: SMISR
description: GPDMA secure masked interrupt status register
byte_offset: 16
fieldset: MISR
- name: CH
array:
len: 16
stride: 128
byte_offset: 80
block: Channel
fieldset/CH_BR1:
description: GPDMA channel 15 alternate block register 1
fields:
- name: BNDT
description: "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued."
bit_offset: 0
bit_size: 16
- name: BRC
description: "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer."
bit_offset: 16
bit_size: 11
- name: SDEC
description: source address decrement
bit_offset: 28
bit_size: 1
enum: CH_BR1_DEC
- name: DDEC
description: destination address decrement
bit_offset: 29
bit_size: 1
enum: CH_BR1_DEC
- name: BRSDEC
description: "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer."
bit_offset: 30
bit_size: 1
enum: CH_BR1_DEC
- name: BRDDEC
description: "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer."
bit_offset: 31
bit_size: 1
enum: CH_BR1_DEC
fieldset/CH_BR2:
description: GPDMA channel 12 block register 2
fields:
- name: BRSAO
description: "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued."
bit_offset: 0
bit_size: 16
- name: BRDAO
description: "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued."
bit_offset: 16
bit_size: 16
fieldset/CH_CR:
description: GPDMA channel 11 control register
fields:
- name: EN
description: "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored."
bit_offset: 0
bit_size: 1
- name: RESET
description: "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in )."
bit_offset: 1
bit_size: 1
- name: SUSP
description: "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in ."
bit_offset: 2
bit_size: 1
- name: TCIE
description: transfer complete interrupt enable
bit_offset: 8
bit_size: 1
- name: HTIE
description: half transfer complete interrupt enable
bit_offset: 9
bit_size: 1
- name: DTEIE
description: data transfer error interrupt enable
bit_offset: 10
bit_size: 1
- name: ULEIE
description: update link transfer error interrupt enable
bit_offset: 11
bit_size: 1
- name: USEIE
description: user setting error interrupt enable
bit_offset: 12
bit_size: 1
- name: SUSPIE
description: completed suspension interrupt enable
bit_offset: 13
bit_size: 1
- name: TOIE
description: trigger overrun interrupt enable
bit_offset: 14
bit_size: 1
- name: LSM
description: "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1."
bit_offset: 16
bit_size: 1
enum: CH_CR_LSM
- name: LAP
description: "linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1."
bit_offset: 17
bit_size: 1
enum: CH_CR_LAP
- name: PRIO
description: "priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
bit_offset: 22
bit_size: 2
enum: CH_CR_PRIO
fieldset/CH_FCR:
description: GPDMA channel 7 flag clear register
fields:
- name: TCF
description: transfer complete flag clear
bit_offset: 8
bit_size: 1
- name: HTF
description: half transfer flag clear
bit_offset: 9
bit_size: 1
- name: DTEF
description: data transfer error flag clear
bit_offset: 10
bit_size: 1
- name: ULEF
description: update link transfer error flag clear
bit_offset: 11
bit_size: 1
- name: USEF
description: user setting error flag clear
bit_offset: 12
bit_size: 1
- name: SUSPF
description: completed suspension flag clear
bit_offset: 13
bit_size: 1
- name: TOF
description: trigger overrun flag clear
bit_offset: 14
bit_size: 1
fieldset/CH_LBAR:
description: GPDMA channel 14 linked-list base address register
fields:
- name: LBA
description: linked-list base address of GPDMA channel x
bit_offset: 16
bit_size: 16
fieldset/CH_LLR:
description: GPDMA channel 15 alternate linked-list address register
fields:
- name: LA
description: "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored."
bit_offset: 2
bit_size: 14
- name: ULL
description: "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer."
bit_offset: 16
bit_size: 1
- name: UB2
description: "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer."
bit_offset: 25
bit_size: 1
- name: UT3
description: "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer."
bit_offset: 26
bit_size: 1
- name: UDA
description: "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer."
bit_offset: 27
bit_size: 1
- name: USA
description: "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer."
bit_offset: 28
bit_size: 1
- name: UB1
description: "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer."
bit_offset: 29
bit_size: 1
- name: UT2
description: "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer."
bit_offset: 30
bit_size: 1
- name: UT1
description: "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer."
bit_offset: 31
bit_size: 1
fieldset/CH_SR:
description: GPDMA channel 15 status register
fields:
- name: IDLEF
description: "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state)."
bit_offset: 0
bit_size: 1
- name: TCF
description: "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0])."
bit_offset: 8
bit_size: 1
- name: HTF
description: "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination."
bit_offset: 9
bit_size: 1
- name: DTEF
description: data transfer error flag
bit_offset: 10
bit_size: 1
- name: ULEF
description: update link transfer error flag
bit_offset: 11
bit_size: 1
- name: USEF
description: user setting error flag
bit_offset: 12
bit_size: 1
- name: SUSPF
description: completed suspension flag
bit_offset: 13
bit_size: 1
- name: TOF
description: trigger overrun flag
bit_offset: 14
bit_size: 1
- name: FIFOL
description: "monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1)."
bit_offset: 16
bit_size: 8
fieldset/CH_TR1:
description: GPDMA channel 8 transfer register 1
fields:
- name: SDW
description: "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued."
bit_offset: 0
bit_size: 2
enum: CH_TR1_DW
- name: SINC
description: "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer."
bit_offset: 3
bit_size: 1
- name: SBL_1
description: "source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed."
bit_offset: 4
bit_size: 6
- name: PAM
description: "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:"
bit_offset: 11
bit_size: 2
enum: CH_TR1_PAM
- name: SBX
description: "source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored."
bit_offset: 13
bit_size: 1
- name: SAP
description: "source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
bit_offset: 14
bit_size: 1
enum: CH_TR1_AP
- name: SSEC
description: "security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure."
bit_offset: 15
bit_size: 1
- name: DDW
description: "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued."
bit_offset: 16
bit_size: 2
enum: CH_TR1_DW
- name: DINC
description: "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer."
bit_offset: 19
bit_size: 1
- name: DBL_1
description: "destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed."
bit_offset: 20
bit_size: 6
- name: DBX
description: "destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored."
bit_offset: 26
bit_size: 1
- name: DHX
description: "destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored."
bit_offset: 27
bit_size: 1
- name: DAP
description: "destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1."
bit_offset: 30
bit_size: 1
enum: CH_TR1_AP
- name: DSEC
description: "security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure."
bit_offset: 31
bit_size: 1
fieldset/CH_TR2:
description: GPDMA channel 10 transfer register 2
fields:
- name: REQSEL
description: "GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting."
bit_offset: 0
bit_size: 7
- name: SWREQ
description: "software request. This bit is internally taken into account when CH[x].CR.EN is asserted."
bit_offset: 9
bit_size: 1
enum: CH_TR2_SWREQ
- name: DREQ
description: "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:"
bit_offset: 10
bit_size: 1
enum: CH_TR2_DREQ
- name: BREQ
description: "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:"
bit_offset: 11
bit_size: 1
enum: CH_TR2_BREQ
- name: TRIGM
description: "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger."
bit_offset: 14
bit_size: 2
enum: CH_TR2_TRIGM
- name: TRIGSEL
description: "trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00."
bit_offset: 16
bit_size: 6
- name: TRIGPOL
description: "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]."
bit_offset: 24
bit_size: 2
enum: CH_TR2_TRIGPOL
- name: TCEM
description: "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1."
bit_offset: 30
bit_size: 2
enum: CH_TR2_TCEM
fieldset/CH_TR3:
description: GPDMA channel 14 transfer register 3
fields:
- name: SAO
description: "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied."
bit_offset: 0
bit_size: 13
- name: DAO
description: "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued."
bit_offset: 16
bit_size: 13
fieldset/MISR:
description: GPDMA secure masked interrupt status register
fields:
- name: MIS
description: MIS0
bit_offset: 0
bit_size: 1
array:
len: 16
stride: 1
fieldset/PRIVCFGR:
description: GPDMA privileged configuration register
fields:
- name: PRIV
description: PRIV0
bit_offset: 0
bit_size: 1
array:
len: 16
stride: 1
fieldset/RCFGLOCKR:
description: GPDMA configuration lock register
fields:
- name: LOCK
description: LOCK0
bit_offset: 0
bit_size: 1
array:
len: 16
stride: 1
fieldset/SECCFGR:
description: GPDMA secure configuration register
fields:
- name: SEC
description: SEC0
bit_offset: 0
bit_size: 1
array:
len: 16
stride: 1
enum/CH_BR1_DEC:
bit_size: 1
variants:
- name: Add
description: The address is incremented by the programmed offset.
value: 0
- name: Subtract
description: The address is decremented by the programmed offset.
value: 1
enum/CH_CR_LAP:
bit_size: 1
variants:
- name: Port0
description: port 0 (AHB) allocated
value: 0
- name: Port1
description: port 1 (AHB) allocated
value: 1
enum/CH_CR_LSM:
bit_size: 1
variants:
- name: RunToCompletion
description: "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present."
value: 0
- name: LinkStep
description: channel executed once for the current LLI
value: 1
enum/CH_CR_PRIO:
bit_size: 2
variants:
- name: LowWithLowhWeight
description: "low priority, low weight"
value: 0
- name: LowWithMidWeight
description: "low priority, mid weight"
value: 1
- name: LowWithHighWeight
description: "low priority, high weight"
value: 2
- name: High
description: high priority
value: 3
enum/CH_TR1_AP:
bit_size: 1
variants:
- name: Port0
description: port 0 (AHB) allocated
value: 0
- name: Port1
description: port 1 (AHB) allocated
value: 1
enum/CH_TR1_DW:
bit_size: 2
variants:
- name: Byte
description: byte
value: 0
- name: HalfWord
description: half-word (2 bytes)
value: 1
- name: Word
description: word (4 bytes)
value: 2
enum/CH_TR1_PAM:
bit_size: 2
variants:
- name: ZeroExtendOrLeftTruncate
description: "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width"
value: 0
- name: SignExtendOrRightTruncate
description: "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width"
value: 1
- name: Pack
description: "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination"
value: 2
enum/CH_TR2_BREQ:
bit_size: 1
variants:
- name: Burst
description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.
value: 0
- name: Block
description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).
value: 1
enum/CH_TR2_DREQ:
bit_size: 1
variants:
- name: SourcePeripheral
description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)
value: 0
- name: DestinationPeripheral
description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)
value: 1
enum/CH_TR2_SWREQ:
bit_size: 1
variants:
- name: Hardware
description: "no software request. The selected hardware request REQSEL[6:0] is taken into account."
value: 0
- name: Software
description: "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored."
value: 1
enum/CH_TR2_TCEM:
bit_size: 2
variants:
- name: EachBlock
description: "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block."
value: 0
- name: Each2DBlock
description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block."
value: 1
- name: EachLinkedListItem
description: "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer."
value: 2
- name: LastLinkedListItem
description: "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated."
value: 3
enum/CH_TR2_TRIGM:
bit_size: 2
variants:
- name: Block
description: "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0)."
value: 0
- name: 2DBlock
description: "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the"
value: 1
- name: LinkedListItem
description: "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned."
value: 2
- name: Burst
description: "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger."
value: 3
enum/CH_TR2_TRIGPOL:
bit_size: 2
variants:
- name: None
description: no trigger (masked trigger event)
value: 0
- name: RisingEdge
description: trigger on the rising edge
value: 1
- name: FallingEdge
description: trigger on the falling edge
value: 2
- name: NoneAlt
description: same as 00
value: 3

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data/registers/spi_v4.yaml Normal file
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---
block/SPI:
description: Serial peripheral interface
items:
- name: CR1
description: control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: control register 2
byte_offset: 4
fieldset: CR2
- name: CFG1
description: configuration register 1
byte_offset: 8
fieldset: CFG1
- name: CFG2
description: configuration register 2
byte_offset: 12
fieldset: CFG2
- name: IER
description: Interrupt Enable Register
byte_offset: 16
fieldset: IER
- name: SR
description: Status Register
byte_offset: 20
access: Read
fieldset: SR
- name: IFCR
description: Interrupt/Status Flags Clear Register
byte_offset: 24
access: Write
fieldset: IFCR
- name: AUTOCR
byte_offset: 28
fieldset: AUTOCR
- name: TXDR
description: Transmit Data Register
byte_offset: 32
access: Write
fieldset: TXDR
- name: RXDR
description: Receive Data Register
byte_offset: 48
access: Read
fieldset: RXDR
- name: CRCPOLY
description: Polynomial Register
byte_offset: 64
fieldset: CRCPOLY
- name: TXCRC
description: Transmitter CRC Register
byte_offset: 68
fieldset: TXCRC
- name: RXCRC
description: Receiver CRC Register
byte_offset: 72
fieldset: RXCRC
- name: UDRDR
description: Underrun Data Register
byte_offset: 76
fieldset: UDRDR
fieldset/AUTOCR:
fields:
- name: TRIGSEL
description: "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0."
bit_offset: 16
bit_size: 4
- name: TRIGPOL
description: "trigger polarity\n Note: This bit can be written only when SPE = 0."
bit_offset: 20
bit_size: 1
enum: TRIGPOL
- name: TRIGEN
description: "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled"
bit_offset: 21
bit_size: 1
fieldset/CFG1:
description: configuration register 1
fields:
- name: DSIZE
description: Number of bits in at single SPI data frame
bit_offset: 0
bit_size: 5
- name: FTHLV
description: threshold level
bit_offset: 5
bit_size: 4
enum: FTHLV
- name: UDRCFG
description: Behavior of slave transmitter at underrun condition
bit_offset: 9
bit_size: 2
enum: UDRCFG
- name: RXDMAEN
description: Rx DMA stream enable
bit_offset: 14
bit_size: 1
- name: TXDMAEN
description: Tx DMA stream enable
bit_offset: 15
bit_size: 1
- name: CRCSIZE
description: Length of CRC frame to be transacted and compared
bit_offset: 16
bit_size: 5
- name: CRCEN
description: Hardware CRC computation enable
bit_offset: 22
bit_size: 1
- name: MBR
description: Master baud rate
bit_offset: 28
bit_size: 3
enum: MBR
- name: BPASS
description: bypass of the prescaler at master baud rate clock generator
bit_offset: 31
bit_size: 1
fieldset/CFG2:
description: configuration register 2
fields:
- name: MSSI
description: Master SS Idleness
bit_offset: 0
bit_size: 4
- name: MIDI
description: Master Inter-Data Idleness
bit_offset: 4
bit_size: 4
- name: RDIOM
description: "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero."
bit_offset: 13
bit_size: 1
enum: RDIOM
- name: RDIOP
description: RDY signal input/output polarity
bit_offset: 14
bit_size: 1
enum: RDIOP
- name: IOSWP
description: Swap functionality of MISO and MOSI pins
bit_offset: 15
bit_size: 1
- name: COMM
description: SPI Communication Mode
bit_offset: 17
bit_size: 2
enum: COMM
- name: SP
description: Serial Protocol
bit_offset: 19
bit_size: 3
enum: SP
- name: MASTER
description: SPI Master
bit_offset: 22
bit_size: 1
enum: MASTER
- name: LSBFIRST
description: Data frame format
bit_offset: 23
bit_size: 1
enum: LSBFIRST
- name: CPHA
description: Clock phase
bit_offset: 24
bit_size: 1
enum: CPHA
- name: CPOL
description: Clock polarity
bit_offset: 25
bit_size: 1
enum: CPOL
- name: SSM
description: Software management of SS signal input
bit_offset: 26
bit_size: 1
- name: SSIOP
description: SS input/output polarity
bit_offset: 28
bit_size: 1
enum: SSIOP
- name: SSOE
description: SS output enable
bit_offset: 29
bit_size: 1
- name: SSOM
description: SS output management in master mode
bit_offset: 30
bit_size: 1
enum: SSOM
- name: AFCNTR
description: Alternate function GPIOs control
bit_offset: 31
bit_size: 1
enum: AFCNTR
fieldset/CR1:
description: control register 1
fields:
- name: SPE
description: Serial Peripheral Enable
bit_offset: 0
bit_size: 1
- name: MASRX
description: Master automatic SUSP in Receive mode
bit_offset: 8
bit_size: 1
- name: CSTART
description: Master transfer start
bit_offset: 9
bit_size: 1
- name: CSUSP
description: Master SUSPend request
bit_offset: 10
bit_size: 1
- name: HDDIR
description: Rx/Tx direction at Half-duplex mode
bit_offset: 11
bit_size: 1
enum: HDDIR
- name: SSI
description: Internal SS signal input level
bit_offset: 12
bit_size: 1
- name: CRC33_17
description: 32-bit CRC polynomial configuration
bit_offset: 13
bit_size: 1
enum: CRC_
- name: RCRCINI
description: CRC calculation initialization pattern control for receiver
bit_offset: 14
bit_size: 1
enum: RCRCINI
- name: TCRCINI
description: CRC calculation initialization pattern control for transmitter
bit_offset: 15
bit_size: 1
enum: TCRCINI
- name: IOLOCK
description: Locking the AF configuration of associated IOs
bit_offset: 16
bit_size: 1
fieldset/CR2:
description: control register 2
fields:
- name: TSIZE
description: Number of data at current transfer
bit_offset: 0
bit_size: 16
fieldset/CRCPOLY:
description: Polynomial Register
fields:
- name: CRCPOLY
description: CRC polynomial register
bit_offset: 0
bit_size: 32
fieldset/IER:
description: Interrupt Enable Register
fields:
- name: RXPIE
description: RXP Interrupt Enable
bit_offset: 0
bit_size: 1
- name: TXPIE
description: TXP interrupt enable
bit_offset: 1
bit_size: 1
- name: DXPIE
description: DXP interrupt enabled
bit_offset: 2
bit_size: 1
- name: EOTIE
description: "EOT, SUSP and TXC interrupt enable"
bit_offset: 3
bit_size: 1
- name: TXTFIE
description: TXTFIE interrupt enable
bit_offset: 4
bit_size: 1
- name: UDRIE
description: UDR interrupt enable
bit_offset: 5
bit_size: 1
- name: OVRIE
description: OVR interrupt enable
bit_offset: 6
bit_size: 1
- name: CRCEIE
description: CRC Interrupt enable
bit_offset: 7
bit_size: 1
- name: TIFREIE
description: TIFRE interrupt enable
bit_offset: 8
bit_size: 1
- name: MODFIE
description: Mode Fault interrupt enable
bit_offset: 9
bit_size: 1
fieldset/IFCR:
description: Interrupt/Status Flags Clear Register
fields:
- name: EOTC
description: End Of Transfer flag clear
bit_offset: 3
bit_size: 1
- name: TXTFC
description: Transmission Transfer Filled flag clear
bit_offset: 4
bit_size: 1
- name: UDRC
description: Underrun flag clear
bit_offset: 5
bit_size: 1
- name: OVRC
description: Overrun flag clear
bit_offset: 6
bit_size: 1
- name: CRCEC
description: CRC Error flag clear
bit_offset: 7
bit_size: 1
- name: TIFREC
description: TI frame format error flag clear
bit_offset: 8
bit_size: 1
- name: MODFC
description: Mode Fault flag clear
bit_offset: 9
bit_size: 1
- name: SUSPC
description: SUSPend flag clear
bit_offset: 11
bit_size: 1
fieldset/RXCRC:
description: Receiver CRC Register
fields:
- name: RXCRC
description: CRC register for receiver
bit_offset: 0
bit_size: 32
fieldset/RXDR:
description: Receive Data Register
fields:
- name: RXDR
description: Receive data register
bit_offset: 0
bit_size: 32
fieldset/SR:
description: Status Register
fields:
- name: RXP
description: Rx-Packet available
bit_offset: 0
bit_size: 1
- name: TXP
description: Tx-Packet space available
bit_offset: 1
bit_size: 1
- name: DXP
description: Duplex Packet
bit_offset: 2
bit_size: 1
- name: EOT
description: End Of Transfer
bit_offset: 3
bit_size: 1
- name: TXTF
description: Transmission Transfer Filled
bit_offset: 4
bit_size: 1
- name: UDR
description: Underrun at slave transmission mode
bit_offset: 5
bit_size: 1
- name: OVR
description: Overrun
bit_offset: 6
bit_size: 1
- name: CRCE
description: CRC Error
bit_offset: 7
bit_size: 1
- name: TIFRE
description: TI frame format error
bit_offset: 8
bit_size: 1
- name: MODF
description: Mode Fault
bit_offset: 9
bit_size: 1
- name: SUSP
description: SUSPend
bit_offset: 11
bit_size: 1
- name: TXC
description: TxFIFO transmission complete
bit_offset: 12
bit_size: 1
- name: RXPLVL
description: RxFIFO Packing LeVeL
bit_offset: 13
bit_size: 2
enum: RXPLVL
- name: RXWNE
description: RxFIFO Word Not Empty
bit_offset: 15
bit_size: 1
enum: RXWNE
- name: CTSIZE
description: Number of data frames remaining in current TSIZE session
bit_offset: 16
bit_size: 16
fieldset/TXCRC:
description: Transmitter CRC Register
fields:
- name: TXCRC
description: CRC register for transmitter
bit_offset: 0
bit_size: 32
fieldset/TXDR:
description: Transmit Data Register
fields:
- name: TXDR
description: Transmit data register
bit_offset: 0
bit_size: 32
fieldset/UDRDR:
description: Underrun Data Register
fields:
- name: UDRDR
description: Data at slave underrun condition
bit_offset: 0
bit_size: 32
enum/AFCNTR:
bit_size: 1
variants:
- name: NotControlled
description: Peripheral takes no control of GPIOs while disabled
value: 0
- name: Controlled
description: Peripheral controls GPIOs while disabled
value: 1
enum/COMM:
bit_size: 2
variants:
- name: FullDuplex
description: Full duplex
value: 0
- name: Transmitter
description: Simplex transmitter only
value: 1
- name: Receiver
description: Simplex receiver only
value: 2
- name: HalfDuplex
description: Half duplex
value: 3
enum/CPHA:
bit_size: 1
variants:
- name: FirstEdge
description: The first clock transition is the first data capture edge
value: 0
- name: SecondEdge
description: The second clock transition is the first data capture edge
value: 1
enum/CPOL:
bit_size: 1
variants:
- name: IdleLow
description: CK to 0 when idle
value: 0
- name: IdleHigh
description: CK to 1 when idle
value: 1
enum/CRC_:
bit_size: 1
variants:
- name: Disabled
description: Full size (33/17 bit) CRC polynomial is not used
value: 0
- name: Enabled
description: Full size (33/17 bit) CRC polynomial is used
value: 1
enum/DATFMT:
bit_size: 1
variants:
- name: RightAligned
description: The data inside RXDR and TXDR are right aligned
value: 0
- name: LeftAligned
description: The data inside RXDR and TXDR are left aligned
value: 1
enum/DATLEN:
bit_size: 2
variants:
- name: Bits16
description: 16 bit data length
value: 0
- name: Bits24
description: 24 bit data length
value: 1
- name: Bits32
description: 32 bit data length
value: 2
enum/FTHLV:
bit_size: 4
variants:
- name: OneFrame
description: 1 frame
value: 0
- name: TwoFrames
description: 2 frames
value: 1
- name: ThreeFrames
description: 3 frames
value: 2
- name: FourFrames
description: 4 frames
value: 3
- name: FiveFrames
description: 5 frames
value: 4
- name: SixFrames
description: 6 frames
value: 5
- name: SevenFrames
description: 7 frames
value: 6
- name: EightFrames
description: 8 frames
value: 7
- name: NineFrames
description: 9 frames
value: 8
- name: TenFrames
description: 10 frames
value: 9
- name: ElevenFrames
description: 11 frames
value: 10
- name: TwelveFrames
description: 12 frames
value: 11
- name: ThirteenFrames
description: 13 frames
value: 12
- name: FourteenFrames
description: 14 frames
value: 13
- name: FifteenFrames
description: 15 frames
value: 14
- name: SixteenFrames
description: 16 frames
value: 15
enum/HDDIR:
bit_size: 1
variants:
- name: Receiver
description: Receiver in half duplex mode
value: 0
- name: Transmitter
description: Transmitter in half duplex mode
value: 1
enum/LSBFIRST:
bit_size: 1
variants:
- name: MSBFirst
description: Data is transmitted/received with the MSB first
value: 0
- name: LSBFirst
description: Data is transmitted/received with the LSB first
value: 1
enum/MASTER:
bit_size: 1
variants:
- name: Slave
description: Slave configuration
value: 0
- name: Master
description: Master configuration
value: 1
enum/MBR:
bit_size: 3
variants:
- name: Div2
description: f_spi_ker_ck / 2
value: 0
- name: Div4
description: f_spi_ker_ck / 4
value: 1
- name: Div8
description: f_spi_ker_ck / 8
value: 2
- name: Div16
description: f_spi_ker_ck / 16
value: 3
- name: Div32
description: f_spi_ker_ck / 32
value: 4
- name: Div64
description: f_spi_ker_ck / 64
value: 5
- name: Div128
description: f_spi_ker_ck / 128
value: 6
- name: Div256
description: f_spi_ker_ck / 256
value: 7
enum/RCRCINI:
bit_size: 1
variants:
- name: AllZeros
description: All zeros RX CRC initialization pattern
value: 0
- name: AllOnes
description: All ones RX CRC initialization pattern
value: 1
enum/RDIOM:
bit_size: 1
variants:
- name: PermanentlyActive
description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)
value: 0
- name: FromInput
description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)
value: 1
enum/RDIOP:
bit_size: 1
variants:
- name: ReadyHigh
description: high level of the signal means the slave is ready for communication
value: 0
- name: ReadyLow
description: low level of the signal means the slave is ready for communication
value: 1
enum/RXPLVL:
bit_size: 2
variants:
- name: ZeroFrames
description: Zero frames beyond packing ratio available
value: 0
- name: OneFrame
description: One frame beyond packing ratio available
value: 1
- name: TwoFrames
description: Two frame beyond packing ratio available
value: 2
- name: ThreeFrames
description: Three frame beyond packing ratio available
value: 3
enum/RXWNE:
bit_size: 1
variants:
- name: LessThan32
description: Less than 32-bit data frame received
value: 0
- name: AtLeast32
description: At least 32-bit data frame received
value: 1
enum/SP:
bit_size: 3
variants:
- name: Motorola
description: Motorola SPI protocol
value: 0
- name: TI
description: TI SPI protocol
value: 1
enum/SSIOP:
bit_size: 1
variants:
- name: ActiveLow
description: Low level is active for SS signal
value: 0
- name: ActiveHigh
description: High level is active for SS signal
value: 1
enum/SSOM:
bit_size: 1
variants:
- name: Asserted
description: SS is asserted until data transfer complete
value: 0
- name: NotAsserted
description: Data frames interleaved with SS not asserted during MIDI
value: 1
enum/TCRCINI:
bit_size: 1
variants:
- name: AllZeros
description: All zeros TX CRC initialization pattern
value: 0
- name: AllOnes
description: All ones TX CRC initialization pattern
value: 1
enum/TRIGPOL:
bit_size: 1
variants:
- name: RisingEdge
description: trigger is active on raising edge
value: 0
- name: FallingEdge
description: trigger is active on falling edge
value: 1
enum/UDRCFG:
bit_size: 2
variants:
- name: Constant
description: Slave sends a constant underrun pattern
value: 0
- name: RepeatReceived
description: Slave repeats last received data frame from master
value: 1
- name: RepeatTransmitted
description: Slave repeats last transmitted data frame
value: 2

49
stm32data/__main__.py
View File

@ -114,6 +114,7 @@ perimap = [
('.*:SPI:spi2s1_v3_1', ('spi', 'v2', 'SPI')), ('.*:SPI:spi2s1_v3_1', ('spi', 'v2', 'SPI')),
('.*:SPI:spi2s2_v1_1', ('spi', 'v3', 'SPI')), ('.*:SPI:spi2s2_v1_1', ('spi', 'v3', 'SPI')),
('.*:SPI:spi2s2_v1_0', ('spi', 'v3', 'SPI')), ('.*:SPI:spi2s2_v1_0', ('spi', 'v3', 'SPI')),
('.*:SPI:spi2s3_v1_1', ('spi', 'v4', 'SPI')),
('.*:I2C:i2c1_v1_5', ('i2c', 'v1', 'I2C')), ('.*:I2C:i2c1_v1_5', ('i2c', 'v1', 'I2C')),
('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')),
('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')), ('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')),
@ -282,6 +283,7 @@ perimap = [
('.*:IPCC:v1_0', ('ipcc', 'v1', 'IPCC')), ('.*:IPCC:v1_0', ('ipcc', 'v1', 'IPCC')),
('.*:DMAMUX.*', ('dmamux', 'v1', 'DMAMUX')), ('.*:DMAMUX.*', ('dmamux', 'v1', 'DMAMUX')),
('.*:GPDMA\d?:.*', ('gpdma', 'v1', 'GPDMA')),
('.*:BDMA\d?:.*', ('bdma', 'v1', 'DMA')), ('.*:BDMA\d?:.*', ('bdma', 'v1', 'DMA')),
('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', ('dma2d', 'v2', 'DMA2D')), ('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', ('dma2d', 'v2', 'DMA2D')),
('.*:DMA2D:dma2d1_v1_0', ('dma2d', 'v1', 'DMA2D')), ('.*:DMA2D:dma2d1_v1_0', ('dma2d', 'v1', 'DMA2D')),
@ -771,12 +773,11 @@ def parse_chips():
# Collect DMA versions in the chip # Collect DMA versions in the chip
chip_dmas = [] chip_dmas = []
for want_kind in ('DMA', 'BDMA', 'BDMA1', 'BDMA2'): for ip in chip['ips'].values():
for ip in chip['ips'].values(): pkind = ip['@Name']
pkind = ip['@Name'] version = ip['@Version']
version = ip['@Version'] if pkind in ('DMA', 'BDMA', 'BDMA1', 'BDMA2', 'GPDMA') and version in dma_channels and version not in chip_dmas:
if pkind == want_kind and version in dma_channels and version not in chip_dmas: chip_dmas.append(version)
chip_dmas.append(version)
# Process DMA channels # Process DMA channels
chs = [] chs = []
@ -1180,6 +1181,42 @@ def parse_dma():
dma_channels[ff] = chip_dma dma_channels[ff] = chip_dma
# STM32U5
chip_dma = {
'channels': [],
'peripherals': {},
}
with open('data/dmamux/U5_GPDMA1.yaml', 'r') as yaml_file:
y = yaml.load(yaml_file)
for (request_name, request_num) in y.items():
parts = request_name.split('_')
target_peri_name = parts[0]
if len(parts) < 2:
request = target_peri_name
else:
request = parts[1]
chip_dma['peripherals'].setdefault(target_peri_name, []).append({
'signal': request,
"dma": 'GPDMA1',
"request": request_num,
})
for i in range(16):
chip_dma['channels'].append({
'name': 'GPDMA1_CH' + str(i),
'dma': 'GPDMA1',
'channel': i,
'supports_2d': i >= 12,
})
ff = 'STM32U5_dma3_Cube'
with open('tmp/dmas/' + ff + '.json', 'w') as f:
json.dump(chip_dma, f, indent=4)
dma_channels[ff] = chip_dma
peripheral_to_clock = {} peripheral_to_clock = {}