CRS: Use L0 CRS definitions for G0 and G4

Comparing the register definitions these peripherals are identical.

data/registers/crs_v1.yaml

@@ -38,6 +38,7 @@ fieldset/CFGR:
       description: SYNC signal source selection
       bit_offset: 28
       bit_size: 2
+      enum: SYNCSRC
     - name: SYNCPOL
       description: SYNC polarity selection
       bit_offset: 31
@@ -135,3 +136,42 @@ fieldset/ISR:
       description: Frequency error capture
       bit_offset: 16
       bit_size: 16
+enum/SYNCSRC:
+  bit_size: 2
+  variants:
+    - name: GPIO
+      description: GPIO selected as SYNC signal source
+      value: 0
+    - name: LSE
+      description: LSE selected as SYNC signal source
+      value: 1
+    - name: USB
+      description: USB SOF selected as SYNC signal source
+      value: 2
+enum/SYNCDIV:
+  bit_size: 3
+  variants:
+    - name: DIV1
+      description: f(SYNCDIV) = f(SYNCSRC)
+      value: 0
+    - name: DIV2
+      description: f(SYNCDIV) = f(SYNCSRC)/2
+      value: 1
+    - name: DIV4
+      description: f(SYNCDIV) = f(SYNCSRC)/4
+      value: 2
+    - name: DIV8
+      description: f(SYNCDIV) = f(SYNCSRC)/8
+      value: 3
+    - name: DIV16
+      description: f(SYNCDIV) = f(SYNCSRC)/16
+      value: 4
+    - name: DIV32
+      description: f(SYNCDIV) = f(SYNCSRC)/32
+      value: 5
+    - name: DIV64
+      description: f(SYNCDIV) = f(SYNCSRC)/64
+      value: 6
+    - name: DIV128
+      description: f(SYNCDIV) = f(SYNCSRC)/128
+      value: 7