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Merge pull request #33 from bobmcwhirter/dac_v2

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Dac v2
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Dario Nieuwenhuis 2021-05-27 23:38:14 +02:00 committed by GitHub
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data/registers/dac_v2.yaml Normal file
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---
block/DAC:
description: Digital-to-analog converter
items:
- name: CR
description: control register
byte_offset: 0
fieldset: CR
- name: SWTRIGR
description: software trigger register
byte_offset: 4
access: Write
fieldset: SWTRIGR
- name: DHR12R1
description: channel1 12-bit right-aligned data holding register
byte_offset: 8
fieldset: DHR12R1
- name: DHR12L1
description: channel1 12-bit left-aligned data holding register
byte_offset: 12
fieldset: DHR12L1
- name: DHR8R1
description: channel1 8-bit right-aligned data holding register
byte_offset: 16
fieldset: DHR8R1
- name: DHR12R2
description: channel2 12-bit right aligned data holding register
byte_offset: 20
fieldset: DHR12R2
- name: DHR12L2
description: channel2 12-bit left aligned data holding register
byte_offset: 24
fieldset: DHR12L2
- name: DHR8R2
description: channel2 8-bit right-aligned data holding register
byte_offset: 28
fieldset: DHR8R2
- name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register
byte_offset: 32
fieldset: DHR12RD
- name: DHR12LD
description: DUAL DAC 12-bit left aligned data holding register
byte_offset: 36
fieldset: DHR12LD
- name: DHR8RD
description: DUAL DAC 8-bit right aligned data holding register
byte_offset: 40
fieldset: DHR8RD
- name: DOR1
description: channel1 data output register
byte_offset: 44
access: Read
fieldset: DOR1
- name: DOR2
description: channel2 data output register
byte_offset: 48
access: Read
fieldset: DOR2
- name: SR
description: status register
byte_offset: 52
fieldset: SR
- name: CCR
description: calibration control register
byte_offset: 56
fieldset: CCR
- name: MCR
description: mode control register
byte_offset: 60
fieldset: MCR
- name: SHSR1
description: Sample and Hold sample time register 1
byte_offset: 64
fieldset: SHSR1
- name: SHSR2
description: Sample and Hold sample time register 2
byte_offset: 68
fieldset: SHSR2
- name: SHHR
description: Sample and Hold hold time register
byte_offset: 72
fieldset: SHHR
- name: SHRR
description: Sample and Hold refresh time register
byte_offset: 76
fieldset: SHRR
fieldset/CCR:
description: calibration control register
fields:
- name: OTRIM1
description: DAC Channel 1 offset trimming value
bit_offset: 0
bit_size: 5
- name: OTRIM2
description: DAC Channel 2 offset trimming value
bit_offset: 16
bit_size: 5
fieldset/CR:
description: control register
fields:
- name: EN1
description: DAC channel1 enable
bit_offset: 0
bit_size: 1
- name: TEN1
description: DAC channel1 trigger enable
bit_offset: 2
bit_size: 1
- name: TSEL1
description: DAC channel1 trigger selection
bit_offset: 3
bit_size: 3
enum: TSEL1
- name: WAVE1
description: DAC channel1 noise/triangle wave generation enable
bit_offset: 6
bit_size: 2
enum: WAVE
- name: MAMP1
description: DAC channel1 mask/amplitude selector
bit_offset: 8
bit_size: 4
- name: DMAEN1
description: DAC channel1 DMA enable
bit_offset: 12
bit_size: 1
- name: DMAUDRIE1
description: DAC channel1 DMA Underrun Interrupt enable
bit_offset: 13
bit_size: 1
- name: CEN1
description: DAC Channel 1 calibration enable
bit_offset: 14
bit_size: 1
- name: EN2
description: DAC channel2 enable
bit_offset: 16
bit_size: 1
- name: TEN2
description: DAC channel2 trigger enable
bit_offset: 18
bit_size: 1
- name: TSEL2
description: DAC channel2 trigger selection
bit_offset: 19
bit_size: 3
enum: TSEL2
- name: WAVE2
description: DAC channel2 noise/triangle wave generation enable
bit_offset: 22
bit_size: 2
enum: WAVE
- name: MAMP2
description: DAC channel2 mask/amplitude selector
bit_offset: 24
bit_size: 4
- name: DMAEN2
description: DAC channel2 DMA enable
bit_offset: 28
bit_size: 1
- name: DMAUDRIE2
description: DAC channel2 DMA underrun interrupt enable
bit_offset: 29
bit_size: 1
- name: CEN2
description: DAC Channel 2 calibration enable
bit_offset: 30
bit_size: 1
fieldset/DHR12L1:
description: channel1 12-bit left-aligned data holding register
fields:
- name: DACC1DHR
description: DAC channel1 12-bit left-aligned data
bit_offset: 4
bit_size: 12
fieldset/DHR12L2:
description: channel2 12-bit left aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 12-bit left-aligned data
bit_offset: 4
bit_size: 12
fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register
fields:
- name: DACC1DHR
description: DAC channel1 12-bit left-aligned data
bit_offset: 4
bit_size: 12
- name: DACC2DHR
description: DAC channel2 12-bit left-aligned data
bit_offset: 20
bit_size: 12
fieldset/DHR12R1:
description: channel1 12-bit right-aligned data holding register
fields:
- name: DACC1DHR
description: DAC channel1 12-bit right-aligned data
bit_offset: 0
bit_size: 12
fieldset/DHR12R2:
description: channel2 12-bit right aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 12-bit right-aligned data
bit_offset: 0
bit_size: 12
fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register
fields:
- name: DACC1DHR
description: DAC channel1 12-bit right-aligned data
bit_offset: 0
bit_size: 12
- name: DACC2DHR
description: DAC channel2 12-bit right-aligned data
bit_offset: 16
bit_size: 12
fieldset/DHR8R1:
description: channel1 8-bit right-aligned data holding register
fields:
- name: DACC1DHR
description: DAC channel1 8-bit right-aligned data
bit_offset: 0
bit_size: 8
fieldset/DHR8R2:
description: channel2 8-bit right-aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 8-bit right-aligned data
bit_offset: 0
bit_size: 8
fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register
fields:
- name: DACC1DHR
description: DAC channel1 8-bit right-aligned data
bit_offset: 0
bit_size: 8
- name: DACC2DHR
description: DAC channel2 8-bit right-aligned data
bit_offset: 8
bit_size: 8
fieldset/DOR1:
description: channel1 data output register
fields:
- name: DACC1DOR
description: DAC channel1 data output
bit_offset: 0
bit_size: 12
fieldset/DOR2:
description: channel2 data output register
fields:
- name: DACC2DOR
description: DAC channel2 data output
bit_offset: 0
bit_size: 12
fieldset/MCR:
description: mode control register
fields:
- name: MODE1
description: DAC Channel 1 mode
bit_offset: 0
bit_size: 3
- name: MODE2
description: DAC Channel 2 mode
bit_offset: 16
bit_size: 3
fieldset/SHHR:
description: Sample and Hold hold time register
fields:
- name: THOLD1
description: DAC Channel 1 hold Time
bit_offset: 0
bit_size: 10
- name: THOLD2
description: DAC Channel 2 hold time
bit_offset: 16
bit_size: 10
fieldset/SHRR:
description: Sample and Hold refresh time register
fields:
- name: TREFRESH1
description: DAC Channel 1 refresh Time
bit_offset: 0
bit_size: 8
- name: TREFRESH2
description: DAC Channel 2 refresh Time
bit_offset: 16
bit_size: 8
fieldset/SHSR1:
description: Sample and Hold sample time register 1
fields:
- name: TSAMPLE1
description: DAC Channel 1 sample Time
bit_offset: 0
bit_size: 10
fieldset/SHSR2:
description: Sample and Hold sample time register 2
fields:
- name: TSAMPLE2
description: DAC Channel 2 sample Time
bit_offset: 0
bit_size: 10
fieldset/SR:
description: status register
fields:
- name: DMAUDR1
description: DAC channel1 DMA underrun flag
bit_offset: 13
bit_size: 1
- name: CAL_FLAG1
description: DAC Channel 1 calibration offset status
bit_offset: 14
bit_size: 1
- name: BWST1
description: DAC Channel 1 busy writing sample time flag
bit_offset: 15
bit_size: 1
- name: DMAUDR2
description: DAC channel2 DMA underrun flag
bit_offset: 29
bit_size: 1
- name: CAL_FLAG2
description: DAC Channel 2 calibration offset status
bit_offset: 30
bit_size: 1
- name: BWST2
description: DAC Channel 2 busy writing sample time flag
bit_offset: 31
bit_size: 1
fieldset/SWTRIGR:
description: software trigger register
fields:
- name: SWTRIG1
description: DAC channel1 software trigger
bit_offset: 0
bit_size: 1
- name: SWTRIG2
description: DAC channel2 software trigger
bit_offset: 1
bit_size: 1
enum/TSEL1:
bit_size: 3
variants:
- name: TIM6_TRGO
description: Timer 6 TRGO event
value: 0
- name: TIM3_TRGO
description: Timer 3 TRGO event
value: 1
- name: TIM7_TRGO
description: Timer 7 TRGO event
value: 2
- name: TIM15_TRGO
description: Timer 15 TRGO event
value: 3
- name: TIM2_TRGO
description: Timer 2 TRGO event
value: 4
- name: EXTI9
description: EXTI line9
value: 6
- name: SOFTWARE
description: Software trigger
value: 7
enum/TSEL2:
bit_size: 3
variants:
- name: TIM6_TRGO
description: Timer 6 TRGO event
value: 0
- name: TIM8_TRGO
description: Timer 8 TRGO event
value: 1
- name: TIM7_TRGO
description: Timer 7 TRGO event
value: 2
- name: TIM5_TRGO
description: Timer 5 TRGO event
value: 3
- name: TIM2_TRGO
description: Timer 2 TRGO event
value: 4
- name: TIM4_TRGO
description: Timer 4 TRGO event
value: 5
- name: EXTI9
description: EXTI line9
value: 6
- name: SOFTWARE
description: Software trigger
value: 7
enum/WAVE:
bit_size: 2
variants:
- name: Disabled
description: Wave generation disabled
value: 0
- name: Noise
description: Noise wave generation enabled
value: 1
- name: Triangle
description: Triangle wave generation enabled
value: 2

1
parse.py
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@ -235,6 +235,7 @@ perimap = [
('.*:SPI:spi2s2_v1_0', 'spi_v3/SPI'), ('.*:SPI:spi2s2_v1_0', 'spi_v3/SPI'),
('.*:I2C:i2c1_v1_5', 'i2c_v1/I2C'), ('.*:I2C:i2c1_v1_5', 'i2c_v1/I2C'),
('.*:I2C:i2c2_v1_1F7', 'i2c_v2/I2C'), ('.*:I2C:i2c2_v1_1F7', 'i2c_v2/I2C'),
('.*:DAC:dacif_v2_0', 'dac_v2/DAC'),
('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),