diff --git a/data/registers/dbgmcu_wba.yaml b/data/registers/dbgmcu_wba.yaml index 264b506..d721f72 100644 --- a/data/registers/dbgmcu_wba.yaml +++ b/data/registers/dbgmcu_wba.yaml @@ -212,11 +212,11 @@ fieldset/CR: description: status and configuration register fields: - name: DBG_STOP - description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state." + description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state." bit_offset: 1 bit_size: 1 - name: DBG_STANDBY - description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed." + description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed." bit_offset: 2 bit_size: 1 - name: LPMS diff --git a/data/registers/pwr_wba.yaml b/data/registers/pwr_wba.yaml index 5ce7382..d39f5ef 100644 --- a/data/registers/pwr_wba.yaml +++ b/data/registers/pwr_wba.yaml @@ -93,7 +93,7 @@ fieldset/CR1: bit_size: 1 enum: RRSB - name: ULPMEN - description: "BOR0 ultra-low-power mode. \r This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled.\r Note: This bit must be set to reach the lowest power consumption in the low-power modes.\r Note: This bit must not be set together with autonomous peripherals using HSI16 as kernel clock.\r Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN." + description: "BOR0 ultra-low-power mode. \r This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled.\r Note: This bit must be set to reach the lowest power consumption in the low-power modes.\r Note: This bit must not be set together with autonomous peripherals using HSI as kernel clock.\r Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN." bit_offset: 7 bit_size: 1 - name: RADIORSB @@ -235,7 +235,7 @@ fieldset/SR: bit_offset: 0 bit_size: 1 - name: STOPF - description: "Stop flag\r This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set." + description: "Stop flag\r This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set." bit_offset: 1 bit_size: 1 - name: SBF diff --git a/data/registers/rcc_c0.yaml b/data/registers/rcc_c0.yaml index eb86c1b..555f289 100644 --- a/data/registers/rcc_c0.yaml +++ b/data/registers/rcc_c0.yaml @@ -402,7 +402,7 @@ fieldset/CICR: bit_offset: 1 bit_size: 1 - name: HSIRDYC - description: "HSI16 ready interrupt clear\r This bit is set software to clear the HSIRDYF flag." + description: "HSI ready interrupt clear\r This bit is set software to clear the HSIRDYF flag." bit_offset: 3 bit_size: 1 - name: HSERDYC @@ -429,7 +429,7 @@ fieldset/CIER: bit_offset: 1 bit_size: 1 - name: HSIRDYIE - description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:" + description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:" bit_offset: 3 bit_size: 1 - name: HSERDYIE @@ -448,7 +448,7 @@ fieldset/CIFR: bit_offset: 1 bit_size: 1 - name: HSIRDYF - description: "HSI16 ready interrupt flag\r This flag indicates a pending interrupt upon HSI16 clock getting ready.\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." + description: "HSI ready interrupt flag\r This flag indicates a pending interrupt upon HSI clock getting ready.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." bit_offset: 3 bit_size: 1 - name: HSERDYF diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index cd7d5f8..12b6c02 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -953,19 +953,19 @@ fieldset/CR: description: Clock control register fields: - name: HSION - description: HSI16 clock enable + description: HSI clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON - description: HSI16 always enable for peripheral kernels + description: HSI always enable for peripheral kernels bit_offset: 9 bit_size: 1 - name: HSIRDY - description: HSI16 clock ready flag + description: HSI clock ready flag bit_offset: 10 bit_size: 1 - name: HSIDIV - description: HSI16 clock division factor + description: HSI clock division factor bit_offset: 11 bit_size: 3 enum: HSIDIV @@ -1124,11 +1124,11 @@ fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: HSICAL - description: HSI16 clock calibration + description: HSI clock calibration bit_offset: 0 bit_size: 8 - name: HSITRIM - description: HSI16 clock trimming + description: HSI clock trimming bit_offset: 8 bit_size: 7 fieldset/PLLCFGR: @@ -1186,13 +1186,13 @@ enum/ADCSEL: description: PLLPCLK used as ADC clock source value: 1 - name: HSI - description: HSI16 used as ADC clock source + description: HSI used as ADC clock source value: 2 enum/CECSEL: bit_size: 1 variants: - name: HSI_DIV_488 - description: HSI16 divided by 488 used as CEC clock + description: HSI divided by 488 used as CEC clock value: 0 - name: LSE description: LSE used as CEC clock @@ -1276,7 +1276,7 @@ enum/I2C1SEL: description: SYSCLK used as I2C1 clock source value: 1 - name: HSI - description: HSI16 used as I2C1 clock source + description: HSI used as I2C1 clock source value: 2 enum/I2C2I2S1SEL: bit_size: 2 @@ -1288,7 +1288,7 @@ enum/I2C2I2S1SEL: description: SYSCLK used as I2C2/I2S2 clock source value: 1 - name: HSI - description: HSI16 used as I2C2/I2S2 clock source + description: HSI used as I2C2/I2S2 clock source value: 2 - name: I2S_CKIN description: External clock used as I2C2/I2S2 clock source @@ -1333,7 +1333,7 @@ enum/LPTIM1SEL: description: LSI used as LPTIM1 clock source value: 1 - name: HSI - description: HSI16 used as LPTIM1 clock source + description: HSI used as LPTIM1 clock source value: 2 - name: LSE description: LSE used as LPTIM1 clock source @@ -1348,7 +1348,7 @@ enum/LPTIM2SEL: description: LSI used as LPTIM2 clock source value: 1 - name: HSI - description: HSI16 used as LPTIM2 clock source + description: HSI used as LPTIM2 clock source value: 2 - name: LSE description: LSE used as LPTIM2 clock source @@ -1363,7 +1363,7 @@ enum/LPUART1SEL: description: SYSCLK used as LPUART1 clock source value: 1 - name: HSI - description: HSI16 used as LPUART1 clock source + description: HSI used as LPUART1 clock source value: 2 - name: LSE description: LSE used as LPUART1 clock source @@ -1378,7 +1378,7 @@ enum/LPUART2SEL: description: SYSCLK used as LPUART2 clock source value: 1 - name: HSI - description: HSI16 used as LPUART2 clock source + description: HSI used as LPUART2 clock source value: 2 - name: LSE description: LSE used as LPUART2 clock source @@ -1447,7 +1447,7 @@ enum/MCOSEL: description: HSI48 selected as MCO source value: 2 - name: HSI - description: HSI16 selected as MCO source + description: HSI selected as MCO source value: 3 - name: HSE description: HSE selected as MCO source @@ -1759,7 +1759,7 @@ enum/PLLSRC: description: No clock selected as PLL entry clock source value: 0 - name: HSI - description: HSI16 selected as PLL entry clock source + description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source @@ -1873,7 +1873,7 @@ enum/USART1SEL: description: SYSCLK used as USART1 clock source value: 1 - name: HSI - description: HSI16 used as USART1 clock source + description: HSI used as USART1 clock source value: 2 - name: LSE description: LSE used as USART1 clock source @@ -1888,7 +1888,7 @@ enum/USART2SEL: description: SYSCLK used as USART2 clock source value: 1 - name: HSI - description: HSI16 used as USART2 clock source + description: HSI used as USART2 clock source value: 2 - name: LSE description: LSE used as USART2 clock source @@ -1903,7 +1903,7 @@ enum/USART3SEL: description: SYSCLK used as USART3 clock source value: 1 - name: HSI - description: HSI16 used as USART3 clock source + description: HSI used as USART3 clock source value: 2 - name: LSE description: LSE used as USART3 clock source diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index c2a21ff..8100553 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1434,7 +1434,7 @@ enum/MCOSEL: description: SYSCLK selected as MCO source value: 1 - name: HSI - description: HSI16 selected as MCO source + description: HSI selected as MCO source value: 3 - name: HSE description: HSE selected as MCO source @@ -1828,7 +1828,7 @@ enum/PLLSRC: description: No clock selected as PLL entry clock source value: 0 - name: HSI - description: HSI16 selected as PLL entry clock source + description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source @@ -1870,7 +1870,7 @@ enum/SW: bit_size: 2 variants: - name: HSI - description: HSI16 selected as system clock + description: HSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 84d18e0..5967821 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -593,8 +593,8 @@ fieldset/CICR: description: LSE ready Interrupt clear bit_offset: 1 bit_size: 1 - - name: HSI16RDYC - description: HSI16 ready Interrupt clear + - name: HSIRDYC + description: HSI ready Interrupt clear bit_offset: 2 bit_size: 1 - name: HSERDYC @@ -628,8 +628,8 @@ fieldset/CIER: description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - - name: HSI16RDYIE - description: HSI16 ready interrupt flag + - name: HSIRDYIE + description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYIE @@ -659,8 +659,8 @@ fieldset/CIFR: description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - - name: HSI16RDYF - description: HSI16 ready interrupt flag + - name: HSIRDYF + description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYF @@ -686,27 +686,27 @@ fieldset/CIFR: fieldset/CR: description: Clock control register fields: - - name: HSI16ON + - name: HSION description: 16 MHz high-speed internal clock enable bit_offset: 0 bit_size: 1 - - name: HSI16KERON + - name: HSIKERON description: High-speed internal clock enable bit for some IP kernels bit_offset: 1 bit_size: 1 - - name: HSI16RDY + - name: HSIRDY description: Internal high-speed clock ready flag bit_offset: 2 bit_size: 1 - - name: HSI16DIVEN - description: HSI16DIVEN + - name: HSIDIVEN + description: HSIDIVEN bit_offset: 3 bit_size: 1 - - name: HSI16DIVF - description: HSI16DIVF + - name: HSIDIVF + description: HSIDIVF bit_offset: 4 bit_size: 1 - - name: HSI16OUTEN + - name: HSIOUTEN description: 16 MHz high-speed internal clock output enable bit_offset: 5 bit_size: 1 @@ -916,11 +916,11 @@ fieldset/GPIOSMEN: fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSI16CAL + - name: HSICAL description: nternal high speed clock calibration bit_offset: 0 bit_size: 8 - - name: HSI16TRIM + - name: HSITRIM description: High speed internal clock trimming bit_offset: 8 bit_size: 5 @@ -977,7 +977,7 @@ enum/ICSEL: description: System clock selected as peripheral clock value: 1 - name: HSI - description: HSI16 clock selected as peripheral clock + description: HSI clock selected as peripheral clock value: 2 enum/LPTIMSEL: bit_size: 2 @@ -989,7 +989,7 @@ enum/LPTIMSEL: description: LSI clock selected as Timer clock value: 1 - name: HSI - description: HSI16 clock selected as Timer clock + description: HSI clock selected as Timer clock value: 2 - name: LSE description: LSE clock selected as Timer clock @@ -1187,7 +1187,7 @@ enum/STOPWUCK: description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock value: 0 - name: HSI - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) + description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) value: 1 enum/SW: bit_size: 2 @@ -1214,7 +1214,7 @@ enum/UARTSEL: description: System clock selected as peripheral clock value: 1 - name: HSI - description: HSI16 clock selected as peripheral clock + description: HSI clock selected as peripheral clock value: 2 - name: LSE description: LSE clock selected as peripheral clock diff --git a/data/registers/rcc_l0_v2.yaml b/data/registers/rcc_l0_v2.yaml index 541a909..b11b209 100644 --- a/data/registers/rcc_l0_v2.yaml +++ b/data/registers/rcc_l0_v2.yaml @@ -601,8 +601,8 @@ fieldset/CICR: description: LSE ready Interrupt clear bit_offset: 1 bit_size: 1 - - name: HSI16RDYC - description: HSI16 ready Interrupt clear + - name: HSIRDYC + description: HSI ready Interrupt clear bit_offset: 2 bit_size: 1 - name: HSERDYC @@ -640,8 +640,8 @@ fieldset/CIER: description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - - name: HSI16RDYIE - description: HSI16 ready interrupt flag + - name: HSIRDYIE + description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYIE @@ -675,8 +675,8 @@ fieldset/CIFR: description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - - name: HSI16RDYF - description: HSI16 ready interrupt flag + - name: HSIRDYF + description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYF @@ -706,27 +706,27 @@ fieldset/CIFR: fieldset/CR: description: Clock control register fields: - - name: HSI16ON + - name: HSION description: 16 MHz high-speed internal clock enable bit_offset: 0 bit_size: 1 - - name: HSI16KERON + - name: HSIKERON description: High-speed internal clock enable bit for some IP kernels bit_offset: 1 bit_size: 1 - - name: HSI16RDY + - name: HSIRDY description: Internal high-speed clock ready flag bit_offset: 2 bit_size: 1 - - name: HSI16DIVEN - description: HSI16DIVEN + - name: HSIDIVEN + description: HSIDIVEN bit_offset: 3 bit_size: 1 - - name: HSI16DIVF - description: HSI16DIVF + - name: HSIDIVF + description: HSIDIVF bit_offset: 4 bit_size: 1 - - name: HSI16OUTEN + - name: HSIOUTEN description: 16 MHz high-speed internal clock output enable bit_offset: 5 bit_size: 1 @@ -955,11 +955,11 @@ fieldset/GPIOSMEN: fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSI16CAL + - name: HSICAL description: nternal high speed clock calibration bit_offset: 0 bit_size: 8 - - name: HSI16TRIM + - name: HSITRIM description: High speed internal clock trimming bit_offset: 8 bit_size: 5 @@ -1016,7 +1016,7 @@ enum/ICSEL: description: System clock selected as peripheral clock value: 1 - name: HSI - description: HSI16 clock selected as peripheral clock + description: HSI clock selected as peripheral clock value: 2 enum/LPTIMSEL: bit_size: 2 @@ -1028,7 +1028,7 @@ enum/LPTIMSEL: description: LSI clock selected as Timer clock value: 1 - name: HSI - description: HSI16 clock selected as Timer clock + description: HSI clock selected as Timer clock value: 2 - name: LSE description: LSE clock selected as Timer clock @@ -1226,7 +1226,7 @@ enum/STOPWUCK: description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock value: 0 - name: HSI - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) + description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1) value: 1 enum/SW: bit_size: 2 @@ -1253,7 +1253,7 @@ enum/UARTSEL: description: System clock selected as peripheral clock value: 1 - name: HSI - description: HSI16 clock selected as peripheral clock + description: HSI clock selected as peripheral clock value: 2 - name: LSE description: LSE clock selected as peripheral clock diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index 775d0df..62f86e7 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -624,8 +624,8 @@ fieldset/CIR: description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - - name: HSI16RDYF - description: HSI16 ready interrupt flag + - name: HSIRDYF + description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYF @@ -652,8 +652,8 @@ fieldset/CIR: description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 - - name: HSI16RDYIE - description: HSI16 ready interrupt enable + - name: HSIRDYIE + description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 - name: HSERDYIE @@ -676,8 +676,8 @@ fieldset/CIR: description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 - - name: HSI16RDYC - description: HSI16 ready interrupt clear + - name: HSIRDYC + description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 - name: HSERDYC @@ -699,11 +699,11 @@ fieldset/CIR: fieldset/CR: description: Clock control register fields: - - name: HSI16ON + - name: HSION description: Internal high-speed clock enable bit_offset: 0 bit_size: 1 - - name: HSI16RDY + - name: HSIRDY description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 @@ -811,11 +811,11 @@ fieldset/CSR: fieldset/ICSCR: description: Internal clock sources calibration register fields: - - name: HSI16CAL + - name: HSICAL description: nternal high speed clock calibration bit_offset: 0 bit_size: 8 - - name: HSI16TRIM + - name: HSITRIM description: High speed internal clock trimming bit_offset: 8 bit_size: 5 @@ -890,7 +890,7 @@ enum/MCOSEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 oscillator clock selected + description: HSI oscillator clock selected value: 2 - name: MSI description: MSI oscillator clock selected @@ -980,7 +980,7 @@ enum/PLLSRC: bit_size: 1 variants: - name: HSI - description: HSI16 selected as PLL input clock + description: HSI selected as PLL input clock value: 0 - name: HSE description: HSE selected as PLL input clock @@ -1040,7 +1040,7 @@ enum/SW: description: MSI oscillator used as system clock value: 0 - name: HSI - description: HSI16 oscillator used as system clock + description: HSI oscillator used as system clock value: 1 - name: HSE description: HSE oscillator used as system clock diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index c94aeae..35a5001 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -1623,7 +1623,7 @@ enum/I2C1SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/I2C2SEL: bit_size: 2 @@ -1635,7 +1635,7 @@ enum/I2C2SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/I2C3SEL: bit_size: 2 @@ -1647,7 +1647,7 @@ enum/I2C3SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/LPTIM1SEL: bit_size: 2 @@ -1659,7 +1659,7 @@ enum/LPTIM1SEL: description: LSI clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -1674,7 +1674,7 @@ enum/LPTIM2SEL: description: LSI clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -1689,7 +1689,7 @@ enum/LPUART1SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2287,7 +2287,7 @@ enum/UART4SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2302,7 +2302,7 @@ enum/UART5SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2317,7 +2317,7 @@ enum/USART1SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2332,7 +2332,7 @@ enum/USART2SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2347,7 +2347,7 @@ enum/USART3SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml index 10105cc..80f7fec 100644 --- a/data/registers/rcc_l4plus.yaml +++ b/data/registers/rcc_l4plus.yaml @@ -1759,7 +1759,7 @@ enum/I2C1SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/I2C2SEL: bit_size: 2 @@ -1771,7 +1771,7 @@ enum/I2C2SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/I2C3SEL: bit_size: 2 @@ -1783,7 +1783,7 @@ enum/I2C3SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/I2C4SEL: bit_size: 2 @@ -1795,7 +1795,7 @@ enum/I2C4SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 enum/LPTIM1SEL: bit_size: 2 @@ -1807,7 +1807,7 @@ enum/LPTIM1SEL: description: LSI clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -1822,7 +1822,7 @@ enum/LPTIM2SEL: description: LSI clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -1837,7 +1837,7 @@ enum/LPUART1SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2471,7 +2471,7 @@ enum/UART4SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2486,7 +2486,7 @@ enum/UART5SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2501,7 +2501,7 @@ enum/USART1SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2516,7 +2516,7 @@ enum/USART2SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected @@ -2531,7 +2531,7 @@ enum/USART3SEL: description: SYSCLK clock selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 2 - name: LSE description: LSE clock selected diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 790f6d9..9fb13e8 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -1548,57 +1548,57 @@ fieldset/CCIPR1: description: RCC peripherals independent clock configuration register 1 fields: - name: USART1SEL - description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 0 bit_size: 2 enum: USARTSEL - name: USART2SEL - description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 2 bit_size: 2 enum: USARTSEL - name: USART3SEL - description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 4 bit_size: 2 enum: USARTSEL - name: UART4SEL - description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 6 bit_size: 2 enum: UARTSEL - name: UART5SEL - description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 8 bit_size: 2 enum: UARTSEL - name: I2C1SEL - description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." bit_offset: 10 bit_size: 2 enum: ICSEL - name: I2C2SEL - description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." bit_offset: 12 bit_size: 2 enum: ICSEL - name: I2C4SEL - description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." bit_offset: 14 bit_size: 2 enum: ICSEL - name: SPI2SEL - description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." bit_offset: 16 bit_size: 2 enum: SPISEL - name: LPTIM2SEL - description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." + description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1." bit_offset: 18 bit_size: 2 enum: LPTIMSEL - name: SPI1SEL - description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK." + description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK." bit_offset: 20 bit_size: 2 enum: SPISEL @@ -1661,7 +1661,7 @@ fieldset/CCIPR2: bit_size: 1 enum: DSISEL - name: USART6SEL - description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." bit_offset: 16 bit_size: 2 enum: USARTSEL @@ -1681,12 +1681,12 @@ fieldset/CCIPR2: bit_size: 2 enum: HSPISEL - name: I2C5SEL - description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." bit_offset: 24 bit_size: 2 enum: ICSEL - name: I2C6SEL - description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." + description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value." bit_offset: 26 bit_size: 2 enum: ICSEL @@ -1699,32 +1699,32 @@ fieldset/CCIPR3: description: RCC peripherals independent clock configuration register 3 fields: - name: LPUART1SEL - description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK." + description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK." bit_offset: 0 bit_size: 3 enum: LPUARTSEL - name: SPI3SEL - description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." + description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK." bit_offset: 3 bit_size: 2 enum: SPISEL - name: I2C3SEL - description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK." + description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK." bit_offset: 6 bit_size: 2 enum: ICSEL - name: LPTIM34SEL - description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." + description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1." bit_offset: 8 bit_size: 2 enum: LPTIMSEL - name: LPTIM1SEL - description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1." + description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1." bit_offset: 10 bit_size: 2 enum: LPTIMSEL - name: ADCDACSEL - description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." + description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)." bit_offset: 12 bit_size: 3 enum: ADCDACSEL @@ -1742,7 +1742,7 @@ fieldset/CFGR1: description: RCC clock configuration register 1 fields: - name: SW - description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." + description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value." bit_offset: 0 bit_size: 2 enum: SW @@ -1846,7 +1846,7 @@ fieldset/CICR: bit_offset: 2 bit_size: 1 - name: HSIRDYC - description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." + description: "HSI ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect." bit_offset: 3 bit_size: 1 - name: HSERDYC @@ -1892,7 +1892,7 @@ fieldset/CIER: bit_offset: 2 bit_size: 1 - name: HSIRDYIE - description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization." + description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization." bit_offset: 3 bit_size: 1 - name: HSERDYIE @@ -1934,7 +1934,7 @@ fieldset/CIFR: bit_offset: 2 bit_size: 1 - name: HSIRDYF - description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." + description: "HSI ready interrupt flag\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." bit_offset: 3 bit_size: 1 - name: HSERDYF @@ -2002,15 +2002,15 @@ fieldset/CR: bit_size: 1 enum: MSIPLLFAST - name: HSION - description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock." + description: "HSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI is used directly or indirectly as system clock." bit_offset: 8 bit_size: 1 - name: HSIKERON - description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 ON even in Stop modes. Keeping the HSI16 ON in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." + description: "HSI enable for some peripheral kernels\r Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode." bit_offset: 9 bit_size: 1 - name: HSIRDY - description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." + description: "HSI clock ready flag\r Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles." bit_offset: 10 bit_size: 1 - name: HSI48ON @@ -2445,7 +2445,7 @@ enum/ADCDACSEL: description: HSE clock selected value: 3 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 4 - name: MSIK description: MSIK clock selected @@ -2595,7 +2595,7 @@ enum/ICSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: MSIK description: MSIK selected @@ -2610,7 +2610,7 @@ enum/LPTIMSEL: description: LSI selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected @@ -2625,7 +2625,7 @@ enum/LPUARTSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected @@ -2706,7 +2706,7 @@ enum/MCOSEL: description: MSIS clock selected value: 2 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 3 - name: HSE description: HSE clock selected @@ -4243,7 +4243,7 @@ enum/PLLSRC: description: MSIS clock selected as PLL3 clock entry value: 1 - name: HSI - description: HSI16 clock selected as PLL3 clock entry + description: HSI clock selected as PLL3 clock entry value: 2 - name: HSE description: HSE clock selected as PLL3 clock entry @@ -4285,7 +4285,7 @@ enum/RNGSEL: description: HSI48 / 2 selected, can be used in Range 4 value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 enum/RTCSEL: bit_size: 2 @@ -4327,7 +4327,7 @@ enum/SAISEL: description: input pin AUDIOCLK selected value: 3 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 4 enum/SDMMCSEL: bit_size: 1 @@ -4357,7 +4357,7 @@ enum/SPISEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: MSIK description: MSIK selected @@ -4369,7 +4369,7 @@ enum/STOPKERWUCK: description: MSIK oscillator automatically enabled when exiting Stop mode value: 0 - name: HSI - description: HSI16 oscillator automatically enabled when exiting Stop mode + description: HSI oscillator automatically enabled when exiting Stop mode value: 1 enum/STOPWUCK: bit_size: 1 @@ -4378,7 +4378,7 @@ enum/STOPWUCK: description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock value: 0 - name: HSI - description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock + description: HSI oscillator selected as wakeup from stop clock and CSS backup clock value: 1 enum/SW: bit_size: 2 @@ -4387,7 +4387,7 @@ enum/SW: description: MSIS selected as system clock value: 0 - name: HSI - description: HSI16 selected as system clock + description: HSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock @@ -4435,7 +4435,7 @@ enum/UARTSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected @@ -4450,7 +4450,7 @@ enum/USARTSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index fc09aea..fd2002b 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -2147,7 +2147,7 @@ enum/PLLSRC: description: MSI selected as PLL entry clock source value: 1 - name: HSI - description: HSI16 selected as PLL entry clock source + description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source diff --git a/data/registers/rcc_wba.yaml b/data/registers/rcc_wba.yaml index 1be8ea5..66479d2 100644 --- a/data/registers/rcc_wba.yaml +++ b/data/registers/rcc_wba.yaml @@ -762,27 +762,27 @@ fieldset/CCIPR1: description: RCC peripherals independent clock configuration register 1 fields: - name: USART1SEL - description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 0 bit_size: 2 enum: USARTSEL - name: USART2SEL - description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE." + description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE." bit_offset: 2 bit_size: 2 enum: USARTSEL - name: I2C1SEL - description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16." + description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI." bit_offset: 10 bit_size: 2 enum: ICSEL - name: LPTIM2SEL - description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1." + description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1." bit_offset: 18 bit_size: 2 enum: LPTIMSEL - name: SPI1SEL - description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16." + description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI." bit_offset: 20 bit_size: 2 enum: SPISEL @@ -792,7 +792,7 @@ fieldset/CCIPR1: bit_size: 2 enum: SYSTICKSEL - name: TIMICSEL - description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256. \r When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division." + description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. \r When TIMICSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division." bit_offset: 31 bit_size: 1 enum: TIMICSEL @@ -808,27 +808,27 @@ fieldset/CCIPR3: description: RCC peripherals independent clock configuration register 3 fields: - name: LPUART1SEL - description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE." + description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI or LSE." bit_offset: 0 bit_size: 2 enum: LPUARTSEL - name: SPI3SEL - description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16." + description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI." bit_offset: 3 bit_size: 2 enum: SPISEL - name: I2C3SEL - description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16" + description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI" bit_offset: 6 bit_size: 2 enum: ICSEL - name: LPTIM1SEL - description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1." + description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1." bit_offset: 10 bit_size: 2 enum: LPTIMSEL - name: ADCSEL - description: "ADC4 kernel clock source selection\r These bits are used to select the ADC4 kernel clock source.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r others: reserved\r Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16." + description: "ADC4 kernel clock source selection\r These bits are used to select the ADC4 kernel clock source.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r others: reserved\r Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI." bit_offset: 12 bit_size: 3 enum: ADCSEL @@ -890,7 +890,7 @@ fieldset/CFGR4: bit_size: 3 enum: HPRE5 - name: HDIV5 - description: "AHB5 divider when SWS select HSI16 or HSE\r Set and reset by software.\r Set to 1 by hardware when entering Stop 1 mode.\r When SYSCLK source indicated by SWS is HSI16 or HSE: HDIV5 is taken into account\r When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account\r Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account." + description: "AHB5 divider when SWS select HSI or HSE\r Set and reset by software.\r Set to 1 by hardware when entering Stop 1 mode.\r When SYSCLK source indicated by SWS is HSI or HSE: HDIV5 is taken into account\r When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account\r Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account." bit_offset: 4 bit_size: 1 enum: HDIV5 @@ -906,7 +906,7 @@ fieldset/CICR: bit_offset: 1 bit_size: 1 - name: HSIRDYC - description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\\\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + description: "HSI ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\\\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." bit_offset: 3 bit_size: 1 - name: HSERDYC @@ -933,7 +933,7 @@ fieldset/CIER: bit_offset: 1 bit_size: 1 - name: HSIRDYIE - description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." bit_offset: 3 bit_size: 1 - name: HSERDYIE @@ -956,7 +956,7 @@ fieldset/CIFR: bit_offset: 1 bit_size: 1 - name: HSIRDYF - description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Cleared by software setting the HSIRDYC bit." + description: "HSI ready interrupt flag\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Cleared by software setting the HSIRDYC bit." bit_offset: 3 bit_size: 1 - name: HSERDYF @@ -975,15 +975,15 @@ fieldset/CR: description: RCC clock control register fields: - name: HSION - description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware when entering Stop and Standby modes. \r Set by hardware to force the HSI16 oscillator on when exiting Stop and Standby modes.\r Set by hardware to force the HSI16 oscillator on in case of clock security failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + description: "HSI clock enable\r Set and cleared by software.\r Cleared by hardware when entering Stop and Standby modes. \r Set by hardware to force the HSI oscillator on when exiting Stop and Standby modes.\r Set by hardware to force the HSI oscillator on in case of clock security failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI is used directly or indirectly as system clock.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." bit_offset: 8 bit_size: 1 - name: HSIKERON - description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 oscillator on even in Stop modes. \r Keeping the HSI16 oscillator on in Stop modes allows the communication speed not to be reduced by the HSI16 oscillator startup time. This bit has no effect on register bit HSION value.\r Cleared by hardware when entering Standby modes. \r Refer to Peripherals clock gating and autonomous mode for more details.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." + description: "HSI enable for some peripheral kernels\r Set and cleared by software to force HSI oscillator on even in Stop modes. \r Keeping the HSI oscillator on in Stop modes allows the communication speed not to be reduced by the HSI oscillator startup time. This bit has no effect on register bit HSION value.\r Cleared by hardware when entering Standby modes. \r Refer to Peripherals clock gating and autonomous mode for more details.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV." bit_offset: 9 bit_size: 1 - name: HSIRDY - description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." + description: "HSI clock ready flag\r Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles." bit_offset: 10 bit_size: 1 - name: HSEON @@ -1057,11 +1057,11 @@ fieldset/ICSCR3: description: RCC internal clock sources calibration register 3 fields: - name: HSICAL - description: "HSI16 clock calibration\r These bits are initialized at startup with the factory-programmed HSI16 calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value." + description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value." bit_offset: 0 bit_size: 12 - name: HSITRIM - description: "HSI16 clock trimming \r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI16." + description: "HSI clock trimming \r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI." bit_offset: 16 bit_size: 5 fieldset/PLL1CFGR: @@ -1167,7 +1167,7 @@ fieldset/SECCFGR: description: RCC secure configuration register fields: - name: HSISEC - description: "HSI16 clock configuration and status bits security\r Set and reset by software." + description: "HSI clock configuration and status bits security\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: HSESEC @@ -1214,7 +1214,7 @@ enum/ADCSEL: description: HSE clock selected value: 3 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 4 enum/HDIV5: bit_size: 1 @@ -1280,7 +1280,7 @@ enum/ICSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 enum/LPTIMSEL: bit_size: 2 @@ -1292,7 +1292,7 @@ enum/LPTIMSEL: description: LSI selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected @@ -1307,7 +1307,7 @@ enum/LPUARTSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected @@ -1388,7 +1388,7 @@ enum/MCOSEL: description: sysclkpre system clock after PLL1RCLKPRE division selected value: 1 - name: HSI - description: HSI16 clock selected + description: HSI clock selected value: 3 - name: HSE description: HSE clock selected @@ -1445,7 +1445,7 @@ enum/PLLSRC: description: no clock sent to PLL1 value: 0 - name: HSI - description: HSI16 clock selected as PLL1 clock entry + description: HSI clock selected as PLL1 clock entry value: 2 - name: HSE description: HSE clock after HSEPRE divider selected as PLL1 clock entry @@ -1490,7 +1490,7 @@ enum/RNGSEL: description: LSI selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: PLL1_Q description: pll1qclk divide by 2 selected @@ -1520,13 +1520,13 @@ enum/SPISEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 enum/SW: bit_size: 2 variants: - name: HSI - description: HSI16 selected as system clock + description: HSI selected as system clock value: 0 - name: HSE description: HSE or HSE/2, as defined by HSEPRE, selected as system clock @@ -1550,10 +1550,10 @@ enum/TIMICSEL: bit_size: 1 variants: - name: HSI - description: HSI16 divider disabled + description: HSI divider disabled value: 0 - name: HSI_DIV_256 - description: HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture + description: HSI/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture value: 1 enum/USARTSEL: bit_size: 2 @@ -1565,7 +1565,7 @@ enum/USARTSEL: description: SYSCLK selected value: 1 - name: HSI - description: HSI16 selected + description: HSI selected value: 2 - name: LSE description: LSE selected diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index ba57b58..545c652 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -1135,7 +1135,7 @@ fieldset/CICR: bit_offset: 2 bit_size: 1 - name: HSIRDYC - description: HSI16 ready interrupt clear + description: HSI ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC @@ -1170,7 +1170,7 @@ fieldset/CIER: bit_offset: 2 bit_size: 1 - name: HSIRDYIE - description: HSI16 ready interrupt enable + description: HSI ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE @@ -1201,7 +1201,7 @@ fieldset/CIFR: bit_offset: 2 bit_size: 1 - name: HSIRDYF - description: HSI16 ready interrupt flag + description: HSI ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF @@ -1245,23 +1245,23 @@ fieldset/CR: bit_size: 4 enum: MSIRANGE - name: HSION - description: HSI16 clock enable + description: HSI clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON - description: HSI16 always enable for peripheral kernel clocks. + description: HSI always enable for peripheral kernel clocks. bit_offset: 9 bit_size: 1 - name: HSIRDY - description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + description: HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) bit_offset: 10 bit_size: 1 - name: HSIASFS - description: HSI16 automatic start from Stop + description: HSI automatic start from Stop bit_offset: 11 bit_size: 1 - name: HSIKERDY - description: HSI16 kernel clock ready flag for peripherals requests. + description: HSI kernel clock ready flag for peripherals requests. bit_offset: 12 bit_size: 1 - name: HSEON @@ -1388,11 +1388,11 @@ fieldset/ICSCR: bit_offset: 8 bit_size: 8 - name: HSICAL - description: HSI16 clock calibration + description: HSI clock calibration bit_offset: 16 bit_size: 8 - name: HSITRIM - description: HSI16 clock trimming + description: HSI clock trimming bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: @@ -1444,7 +1444,7 @@ enum/ADCSEL: bit_size: 2 variants: - name: HSI - description: HSI16 used as ADC clock source + description: HSI used as ADC clock source value: 1 - name: PLL1_P description: PLLPCLK used as ADC clock source @@ -1971,7 +1971,7 @@ enum/PLLSRC: description: MSI selected as PLL entry clock source value: 1 - name: HSI - description: HSI16 selected as PLL entry clock source + description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index f03a08e..bf6fb80 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -765,7 +765,7 @@ fieldset/CICR: bit_offset: 2 bit_size: 1 - name: HSIRDYC - description: HSI16 ready interrupt clear + description: HSI ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC @@ -800,7 +800,7 @@ fieldset/CIER: bit_offset: 2 bit_size: 1 - name: HSIRDYIE - description: HSI16 ready interrupt enable + description: HSI ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE @@ -831,7 +831,7 @@ fieldset/CIFR: bit_offset: 2 bit_size: 1 - name: HSIRDYF - description: HSI16 ready interrupt flag + description: HSI ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF @@ -875,23 +875,23 @@ fieldset/CR: bit_size: 4 enum: MSIRANGE - name: HSION - description: HSI16 clock enable + description: HSI clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON - description: HSI16 always enable for peripheral kernel clocks. + description: HSI always enable for peripheral kernel clocks. bit_offset: 9 bit_size: 1 - name: HSIRDY - description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + description: HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) bit_offset: 10 bit_size: 1 - name: HSIASFS - description: HSI16 automatic start from Stop + description: HSI automatic start from Stop bit_offset: 11 bit_size: 1 - name: HSIKERDY - description: HSI16 kernel clock ready flag for peripherals requests. + description: HSI kernel clock ready flag for peripherals requests. bit_offset: 12 bit_size: 1 - name: HSEON @@ -1009,11 +1009,11 @@ fieldset/ICSCR: bit_offset: 8 bit_size: 8 - name: HSICAL - description: HSI16 clock calibration + description: HSI clock calibration bit_offset: 16 bit_size: 8 - name: HSITRIM - description: HSI16 clock trimming + description: HSI clock trimming bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: @@ -1065,7 +1065,7 @@ enum/ADCSEL: bit_size: 2 variants: - name: HSI - description: HSI16 used as ADC clock source + description: HSI used as ADC clock source value: 1 - name: PLL1_P description: PLLPCLK used as ADC clock source @@ -1592,7 +1592,7 @@ enum/PLLSRC: description: MSI selected as PLL entry clock source value: 1 - name: HSI - description: HSI16 selected as PLL entry clock source + description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source diff --git a/data/registers/syscfg_wba.yaml b/data/registers/syscfg_wba.yaml index 9c46714..06c242c 100644 --- a/data/registers/syscfg_wba.yaml +++ b/data/registers/syscfg_wba.yaml @@ -68,7 +68,7 @@ fieldset/CCCSR: bit_offset: 1 bit_size: 1 - name: RDY1 - description: "VDD I/Os compensation cell ready flag\r This bit provides the compensation cell status of the I/Os supplied by VDD.\r Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION)." + description: "VDD I/Os compensation cell ready flag\r This bit provides the compensation cell status of the I/Os supplied by VDD.\r Note: The HSI clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI clock is not enabled (HSION)." bit_offset: 8 bit_size: 1 fieldset/CCVR: