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eZio Pan 2024-02-27 11:44:10 +08:00
parent 4e8b96a7f0
commit edad32f27e
1 changed files with 6 additions and 6 deletions
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data/registers/comp_h5.yaml
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@ -21,11 +21,11 @@ fieldset/CFGR1:
description: Comparator configuration register 1.
fields:
- name: EN
description: COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP<EFBFBD>Channel1.
description: COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP-Channel1.
bit_offset: 0
bit_size: 1
- name: BRGEN
description: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V<sub>REF_COMP</sub> (similar to V<sub>REFINT</sub>). If SCALEN and BRGEN are set, the four scaler outputs provide V<sub>REF_COMP</sub>, 3/4<EFBFBD>V<sub>REF_COMP</sub>, 1/2<>V<sub>REF_COMP</sub> and 1/4<>V<sub>REF_COMP</sub> levels, respectively.
description: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V<sub>REF_COMP</sub> (similar to V<sub>REFINT</sub>). If SCALEN and BRGEN are set, the four scaler outputs provide V<sub>REF_COMP</sub>, 3/4-V<sub>REF_COMP</sub>, 1/2-V<sub>REF_COMP</sub> and 1/4-V<sub>REF_COMP</sub> levels, respectively.
bit_offset: 1
bit_size: 1
- name: SCALEN
@ -51,16 +51,16 @@ fieldset/CFGR1:
bit_size: 2
enum: PWRMODE
- name: INMSEL
description: 'COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table<EFBFBD>146: COMP1 inverting input assignment for more details.'
description: 'COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table-146: COMP1 inverting input assignment for more details.'
bit_offset: 16
bit_size: 4
enum: INMSEL
- name: INPSEL1
description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table<EFBFBD>145: COMP1 noninverting input assignment for more details.'
description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table-145: COMP1 noninverting input assignment for more details.'
bit_offset: 20
bit_size: 1
- name: INPSEL2
description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table<EFBFBD>145: COMP1 noninverting input assignment for more details.'
description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table-145: COMP1 noninverting input assignment for more details.'
bit_offset: 22
bit_size: 1
- name: BLANKING
@ -76,7 +76,7 @@ fieldset/CFGR2:
description: Comparator configuration register 2.
fields:
- name: INPSEL0
description: 'COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table<EFBFBD>145: COMP1 noninverting input assignment for more details.'
description: 'COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table-145: COMP1 noninverting input assignment for more details.'
bit_offset: 4
bit_size: 1
- name: LOCK