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L5: fix RCC

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This commit is contained in:
Dario Nieuwenhuis 2022-04-08 02:54:37 +02:00
parent 1d5853be40
commit eb678443a3
2 changed files with 70 additions and 29 deletions
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12
data/registers/rcc_l4.yaml
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@ -1888,23 +1888,23 @@ enum/STOPWUCK:
bit_size: 1 bit_size: 1
variants: variants:
- name: MSI - name: MSI
description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock description: MSI oscillator selected as wake-up from Stop clock
value: 0 value: 0
- name: HSI16 - name: HSI16
description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) description: HSI oscillator selected as wake-up from Stop clock
value: 1 value: 1
enum/SW: enum/SW:
bit_size: 2 bit_size: 2
variants: variants:
- name: MSI - name: MSI
description: MSI oscillator used as system clock description: MSI selected as system clock
value: 0 value: 0
- name: HSI16 - name: HSI16
description: HSI oscillator used as system clock description: HSI selected as system clock
value: 1 value: 1
- name: HSE - name: HSE
description: HSE oscillator used as system clock description: HSE selected as system clock
value: 2 value: 2
- name: PLL - name: PLL
description: PLL used as system clock description: PLL selected as system clock
value: 3 value: 3

87
data/registers/rcc_l5.yaml
View File

@ -1426,14 +1426,14 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SW
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: HPRE enum: HPRE
- name: PPRE1 - name: PPRE1
description: PB low-speed prescaler (APB1) description: APB low-speed prescaler (APB1)
bit_offset: 8 bit_offset: 8
bit_size: 3 bit_size: 3
enum: PPRE enum: PPRE
@ -1448,7 +1448,7 @@ fieldset/CFGR:
bit_size: 1 bit_size: 1
enum: STOPWUCK enum: STOPWUCK
- name: MCOSEL - name: MCOSEL
description: Microcontroller clock output description: Microcontroller clock output selection
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
enum: MCOSEL enum: MCOSEL
@ -1617,6 +1617,7 @@ fieldset/CR:
description: MSI clock ranges description: MSI clock ranges
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: MSIRANGE
- name: HSION - name: HSION
description: HSI clock enable description: HSI clock enable
bit_offset: 8 bit_offset: 8
@ -1731,7 +1732,7 @@ fieldset/CSR:
description: Software reset flag description: Software reset flag
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
- name: IWWDGRSTF - name: IWDGRSTF
description: Independent window watchdog reset flag description: Independent window watchdog reset flag
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
@ -1769,6 +1770,7 @@ fieldset/PLLCFGR:
description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source" description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source"
bit_offset: 0 bit_offset: 0
bit_size: 2 bit_size: 2
enum: PLLSRC
- name: PLLM - name: PLLM
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bit_offset: 4 bit_offset: 4
@ -2087,6 +2089,60 @@ enum/MCOSEL:
- name: HSI48 - name: HSI48
description: Internal HSI48 clock selected description: Internal HSI48 clock selected
value: 8 value: 8
enum/MSIRANGE:
bit_size: 4
variants:
- name: Range100K
description: range 0 around 100 kHz
value: 0
- name: Range200K
description: range 1 around 200 kHz
value: 1
- name: Range400K
description: range 2 around 400 kHz
value: 2
- name: Range800K
description: range 3 around 800 kHz
value: 3
- name: Range1M
description: range 4 around 1 MHz
value: 4
- name: Range2M
description: range 5 around 2 MHz
value: 5
- name: Range4M
description: range 6 around 4 MHz
value: 6
- name: Range8M
description: range 7 around 8 MHz
value: 7
- name: Range16M
description: range 8 around 16 MHz
value: 8
- name: Range24M
description: range 9 around 24 MHz
value: 9
- name: Range32M
description: range 10 around 32 MHz
value: 10
- name: Range48M
description: range 11 around 48 MHz
value: 11
enum/PLLSRC:
bit_size: 2
variants:
- name: None
description: No clock sent to PLL
value: 0
- name: MSI
description: MSI selected as PLL input clock
value: 1
- name: HSI16
description: HSI selected as PLL input clock
value: 2
- name: HSE
description: HSE selected as PLL input clock
value: 3
enum/PPRE: enum/PPRE:
bit_size: 3 bit_size: 3
variants: variants:
@ -2124,10 +2180,10 @@ enum/STOPWUCK:
bit_size: 1 bit_size: 1
variants: variants:
- name: MSI - name: MSI
description: MSI oscillator selected as wakeup from stop clock and CSS backup clock description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock
value: 0 value: 0
- name: HSI - name: HSI16
description: HSI oscillator selected as wakeup from stop clock and CSS backup clock description: HSI oscillator selected as wake-up from stop clock and CSS backup clock
value: 1 value: 1
enum/SW: enum/SW:
bit_size: 2 bit_size: 2
@ -2135,7 +2191,7 @@ enum/SW:
- name: MSI - name: MSI
description: MSI selected as system clock description: MSI selected as system clock
value: 0 value: 0
- name: HSI - name: HSI16
description: HSI selected as system clock description: HSI selected as system clock
value: 1 value: 1
- name: HSE - name: HSE
@ -2144,18 +2200,3 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 3 value: 3
enum/SWSR:
bit_size: 2
variants:
- name: MSI
description: MSI oscillator used as system clock
value: 0
- name: HSI
description: HSI oscillator used as system clock
value: 1
- name: HSE
description: HSE used as system clock
value: 2
- name: PLL
description: PLL used as system clock
value: 3