Widen the bitsize on the EXTICR.

data/registers/syscfg_l4.yaml

@@ -107,7 +107,7 @@ fieldset/EXTICR:
     - name: EXTI
       description: EXTI12 configuration bits
       bit_offset: 0
-      bit_size: 3
+      bit_size: 4
       array:
         len: 4
         stride: 4

transform.yaml

@@ -15,16 +15,27 @@ transforms:
       from: ([A-Z]+)\d+
       to: $1
       allow_cursed: true
+  - MakeFieldArray:
+      fieldsets: .*
+      from: P\d+WP
+      to: PWP 
+#  - MakeRegisterArray:
+#      blocks: .*
+#      from: ([A-Z]+)\d+
+#      to: $1
   - MakeRegisterArray:
       blocks: .*
-      from: ([A-Z]+)\d+
-      to: $1
+      from: EXTICR\d+
+      to: EXTICR 
   - MergeEnums:
       from: '[HL](IFCR|ISR)_(.*)'
       to: $2
   - MergeFieldsets:
       from: '[HL](IFCR|ISR)'
       to: $1
+  - MergeFieldsets:
+      from: EXTICR\d 
+      to: EXTICR 
   - MakeRegisterArray:
       blocks: .*
       from: '[HL](IFCR|ISR)'