New peripherals: octospim_v1+v2, and octospi_v1-v4

data/registers/octospi_v1.yaml

@@ -0,0 +1,542 @@
+block/OCTOSPI:
+  description: OctoSPI
+  items:
+    - name: CR
+      description: control register
+      byte_offset: 0
+      fieldset: CR
+    - name: DCR1
+      description: device configuration register
+      byte_offset: 8
+      fieldset: DCR1
+    - name: DCR2
+      description: device configuration register 2
+      byte_offset: 12
+      fieldset: DCR2
+    - name: DCR3
+      description: device configuration register 3
+      byte_offset: 16
+      fieldset: DCR3
+    - name: SR
+      description: status register
+      byte_offset: 32
+      fieldset: SR
+    - name: FCR
+      description: flag clear register
+      byte_offset: 36
+      access: Write
+      fieldset: FCR
+    - name: DLR
+      description: data length register
+      byte_offset: 64
+      fieldset: DLR
+    - name: AR
+      description: address register
+      byte_offset: 72
+      fieldset: AR
+    - name: DR
+      description: data register
+      byte_offset: 80
+      fieldset: DR
+    - name: PSMKR
+      description: polling status mask register
+      byte_offset: 128
+      fieldset: PSMKR
+    - name: PSMAR
+      description: polling status match register
+      byte_offset: 136
+      fieldset: PSMAR
+    - name: PIR
+      description: polling interval register
+      byte_offset: 144
+      fieldset: PIR
+    - name: CCR
+      description: communication configuration register
+      byte_offset: 256
+      fieldset: CCR
+    - name: TCR
+      description: timing configuration register
+      byte_offset: 264
+      fieldset: TCR
+    - name: IR
+      description: instruction register
+      byte_offset: 272
+      fieldset: IR
+    - name: ABR
+      description: alternate bytes register
+      byte_offset: 288
+      fieldset: ABR
+    - name: LPTR
+      description: low-power timeout register
+      byte_offset: 304
+      fieldset: LPTR
+    - name: WCCR
+      description: write communication configuration register
+      byte_offset: 384
+      fieldset: WCCR
+    - name: WTCR
+      description: write timing configuration register
+      byte_offset: 392
+      fieldset: WTCR
+    - name: WIR
+      description: write instruction register
+      byte_offset: 400
+      fieldset: WIR
+    - name: WABR
+      description: write alternate bytes register
+      byte_offset: 416
+      fieldset: WABR
+    - name: HLCR
+      description: HyperBusTM latency configuration register
+      byte_offset: 512
+      fieldset: HLCR
+    - name: HWCFGR
+      description: HW configuration register
+      byte_offset: 1008
+      access: Read
+      fieldset: HWCFGR
+    - name: VER
+      description: version register
+      byte_offset: 1012
+      access: Read
+      fieldset: VER
+    - name: ID
+      description: identification
+      byte_offset: 1016
+      access: Read
+      fieldset: ID
+    - name: MID
+      description: magic ID
+      byte_offset: 1020
+      access: Read
+      fieldset: MID
+fieldset/ABR:
+  description: alternate bytes register
+  fields:
+    - name: ALTERNATE
+      description: Alternate bytes
+      bit_offset: 0
+      bit_size: 32
+fieldset/AR:
+  description: address register
+  fields:
+    - name: ADDRESS
+      description: ADDRESS
+      bit_offset: 0
+      bit_size: 32
+fieldset/CCR:
+  description: communication configuration register
+  fields:
+    - name: IMODE
+      description: Instruction mode
+      bit_offset: 0
+      bit_size: 3
+    - name: IDTR
+      description: Instruction double transfer rate
+      bit_offset: 3
+      bit_size: 1
+    - name: ISIZE
+      description: Instruction size
+      bit_offset: 4
+      bit_size: 2
+    - name: ADMODE
+      description: Address mode
+      bit_offset: 8
+      bit_size: 3
+    - name: ADDTR
+      description: Address double transfer rate
+      bit_offset: 11
+      bit_size: 1
+    - name: ADSIZE
+      description: Address size
+      bit_offset: 12
+      bit_size: 2
+    - name: ABMODE
+      description: Alternate byte mode
+      bit_offset: 16
+      bit_size: 3
+    - name: ABDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 19
+      bit_size: 1
+    - name: ABSIZE
+      description: Alternate bytes size
+      bit_offset: 20
+      bit_size: 2
+    - name: DMODE
+      description: Data mode
+      bit_offset: 24
+      bit_size: 3
+    - name: DDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 27
+      bit_size: 1
+    - name: DQSE
+      description: DQS enable
+      bit_offset: 29
+      bit_size: 1
+    - name: SIOO
+      description: Send instruction only once mode
+      bit_offset: 31
+      bit_size: 1
+fieldset/CR:
+  description: control register
+  fields:
+    - name: EN
+      description: Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: ABORT
+      description: Abort request
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAEN
+      description: DMA enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TCEN
+      description: Timeout counter enable
+      bit_offset: 3
+      bit_size: 1
+    - name: DQM
+      description: Dual-quad mode
+      bit_offset: 6
+      bit_size: 1
+    - name: FSEL
+      description: FLASH memory selection
+      bit_offset: 7
+      bit_size: 1
+    - name: FTHRES
+      description: IFO threshold level
+      bit_offset: 8
+      bit_size: 5
+    - name: TEIE
+      description: Transfer error interrupt enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TCIE
+      description: Transfer complete interrupt enable
+      bit_offset: 17
+      bit_size: 1
+    - name: FTIE
+      description: FIFO threshold interrupt enable
+      bit_offset: 18
+      bit_size: 1
+    - name: SMIE
+      description: Status match interrupt enable
+      bit_offset: 19
+      bit_size: 1
+    - name: TOIE
+      description: TimeOut interrupt enable
+      bit_offset: 20
+      bit_size: 1
+    - name: APMS
+      description: Automatic poll mode stop
+      bit_offset: 22
+      bit_size: 1
+    - name: PMM
+      description: Polling match mode
+      bit_offset: 23
+      bit_size: 1
+    - name: FMODE
+      description: Functional mode
+      bit_offset: 28
+      bit_size: 2
+fieldset/DCR1:
+  description: device configuration register
+  fields:
+    - name: CKMODE
+      description: Mode 0 / mode 3
+      bit_offset: 0
+      bit_size: 1
+    - name: FRCK
+      description: Free running clock
+      bit_offset: 1
+      bit_size: 1
+    - name: CSHT
+      description: Chip-select high time
+      bit_offset: 8
+      bit_size: 3
+    - name: DEVSIZE
+      description: Device size
+      bit_offset: 16
+      bit_size: 5
+    - name: MTYP
+      description: Memory type
+      bit_offset: 24
+      bit_size: 2
+fieldset/DCR2:
+  description: device configuration register 2
+  fields:
+    - name: PRESCALER
+      description: Clock prescaler
+      bit_offset: 0
+      bit_size: 8
+    - name: WRAPSIZE
+      description: Wrap size
+      bit_offset: 16
+      bit_size: 3
+fieldset/DCR3:
+  description: device configuration register 3
+  fields:
+    - name: CSBOUND
+      description: CS boundary
+      bit_offset: 16
+      bit_size: 5
+fieldset/DLR:
+  description: data length register
+  fields:
+    - name: DL
+      description: Data length
+      bit_offset: 0
+      bit_size: 32
+fieldset/DR:
+  description: data register
+  fields:
+    - name: DATA
+      description: Data
+      bit_offset: 0
+      bit_size: 32
+fieldset/FCR:
+  description: flag clear register
+  fields:
+    - name: CTEF
+      description: Clear transfer error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: CTCF
+      description: Clear transfer complete flag
+      bit_offset: 1
+      bit_size: 1
+    - name: CSMF
+      description: Clear status match flag
+      bit_offset: 3
+      bit_size: 1
+    - name: CTOF
+      description: Clear timeout flag
+      bit_offset: 4
+      bit_size: 1
+fieldset/HLCR:
+  description: HyperBusTM latency configuration register
+  fields:
+    - name: LM
+      description: Latency mode
+      bit_offset: 0
+      bit_size: 1
+    - name: WZL
+      description: Write zero latency
+      bit_offset: 1
+      bit_size: 1
+    - name: TACC
+      description: Access time
+      bit_offset: 8
+      bit_size: 8
+    - name: TRWR
+      description: Read write recovery time
+      bit_offset: 16
+      bit_size: 8
+fieldset/HWCFGR:
+  description: HW configuration register
+  fields:
+    - name: AXI
+      description: AXI interface
+      bit_offset: 0
+      bit_size: 4
+    - name: FIFO
+      description: FIFO depth
+      bit_offset: 4
+      bit_size: 8
+    - name: PRES
+      description: Prescaler
+      bit_offset: 12
+      bit_size: 8
+    - name: IDL
+      description: ID Length
+      bit_offset: 20
+      bit_size: 4
+    - name: MMW
+      description: Memory map write
+      bit_offset: 24
+      bit_size: 4
+    - name: MST
+      description: Master
+      bit_offset: 28
+      bit_size: 4
+fieldset/ID:
+  description: identification
+  fields:
+    - name: ID
+      description: Identification
+      bit_offset: 0
+      bit_size: 32
+fieldset/IR:
+  description: instruction register
+  fields:
+    - name: INSTRUCTION
+      description: INSTRUCTION
+      bit_offset: 0
+      bit_size: 32
+fieldset/LPTR:
+  description: low-power timeout register
+  fields:
+    - name: TIMEOUT
+      description: Timeout period
+      bit_offset: 0
+      bit_size: 16
+fieldset/MID:
+  description: magic ID
+  fields:
+    - name: MID
+      description: Magic ID
+      bit_offset: 0
+      bit_size: 32
+fieldset/PIR:
+  description: polling interval register
+  fields:
+    - name: INTERVAL
+      description: Polling interval
+      bit_offset: 0
+      bit_size: 16
+fieldset/PSMAR:
+  description: polling status match register
+  fields:
+    - name: MATCH
+      description: Status match
+      bit_offset: 0
+      bit_size: 32
+fieldset/PSMKR:
+  description: polling status mask register
+  fields:
+    - name: MASK
+      description: Status mask
+      bit_offset: 0
+      bit_size: 32
+fieldset/SR:
+  description: status register
+  fields:
+    - name: TEF
+      description: Transfer error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: TCF
+      description: Transfer complete flag
+      bit_offset: 1
+      bit_size: 1
+    - name: FTF
+      description: FIFO threshold flag
+      bit_offset: 2
+      bit_size: 1
+    - name: SMF
+      description: Status match flag
+      bit_offset: 3
+      bit_size: 1
+    - name: TOF
+      description: Timeout flag
+      bit_offset: 4
+      bit_size: 1
+    - name: BUSY
+      description: BUSY
+      bit_offset: 5
+      bit_size: 1
+    - name: FLEVEL
+      description: FIFO level
+      bit_offset: 8
+      bit_size: 6
+fieldset/TCR:
+  description: timing configuration register
+  fields:
+    - name: DCYC
+      description: Number of dummy cycles
+      bit_offset: 0
+      bit_size: 5
+    - name: DHQC
+      description: Delay hold quarter cycle
+      bit_offset: 28
+      bit_size: 1
+    - name: SSHIFT
+      description: Sample shift
+      bit_offset: 30
+      bit_size: 1
+fieldset/VER:
+  description: version register
+  fields:
+    - name: VER
+      description: Version
+      bit_offset: 0
+      bit_size: 8
+fieldset/WABR:
+  description: write alternate bytes register
+  fields:
+    - name: ALTERNATE
+      description: Alternate bytes
+      bit_offset: 0
+      bit_size: 32
+fieldset/WCCR:
+  description: write communication configuration register
+  fields:
+    - name: IMODE
+      description: Instruction mode
+      bit_offset: 0
+      bit_size: 3
+    - name: IDTR
+      description: Instruction double transfer rate
+      bit_offset: 3
+      bit_size: 1
+    - name: ISIZE
+      description: Instruction size
+      bit_offset: 4
+      bit_size: 2
+    - name: ADMODE
+      description: Address mode
+      bit_offset: 8
+      bit_size: 3
+    - name: ADDTR
+      description: Address double transfer rate
+      bit_offset: 11
+      bit_size: 1
+    - name: ADSIZE
+      description: Address size
+      bit_offset: 12
+      bit_size: 2
+    - name: ABMODE
+      description: Alternate byte mode
+      bit_offset: 16
+      bit_size: 3
+    - name: ABDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 19
+      bit_size: 1
+    - name: ABSIZE
+      description: Alternate bytes size
+      bit_offset: 20
+      bit_size: 2
+    - name: DMODE
+      description: Data mode
+      bit_offset: 24
+      bit_size: 3
+    - name: DDTR
+      description: alternate bytes double transfer rate
+      bit_offset: 27
+      bit_size: 1
+    - name: DQSE
+      description: DQS enable
+      bit_offset: 29
+      bit_size: 1
+    - name: SIOO
+      description: Send instruction only once mode
+      bit_offset: 31
+      bit_size: 1
+fieldset/WIR:
+  description: write instruction register
+  fields:
+    - name: INSTRUCTION
+      description: INSTRUCTION
+      bit_offset: 0
+      bit_size: 32
+fieldset/WTCR:
+  description: write timing configuration register
+  fields:
+    - name: DCYC
+      description: Number of dummy cycles
+      bit_offset: 0
+      bit_size: 5

data/registers/octospi_v2.yaml

@@ -0,0 +1,586 @@
+block/OCTOSPI:
+  description: OctoSPI
+  items:
+    - name: CR
+      description: control register
+      byte_offset: 0
+      fieldset: CR
+    - name: DCR1
+      description: device configuration register 1
+      byte_offset: 8
+      fieldset: DCR1
+    - name: DCR2
+      description: device configuration register 2
+      byte_offset: 12
+      fieldset: DCR2
+    - name: DCR3
+      description: device configuration register 3
+      byte_offset: 16
+      fieldset: DCR3
+    - name: DCR4
+      description: DCR4
+      byte_offset: 20
+      fieldset: DCR4
+    - name: SR
+      description: status register
+      byte_offset: 32
+      access: Read
+      fieldset: SR
+    - name: FCR
+      description: flag clear register
+      byte_offset: 36
+      access: Write
+      fieldset: FCR
+    - name: DLR
+      description: data length register
+      byte_offset: 64
+      fieldset: DLR
+    - name: AR
+      description: address register
+      byte_offset: 72
+      fieldset: AR
+    - name: DR
+      description: data register
+      byte_offset: 80
+      fieldset: DR
+    - name: PSMKR
+      description: polling status mask register
+      byte_offset: 128
+      fieldset: PSMKR
+    - name: PSMAR
+      description: polling status match register
+      byte_offset: 136
+      fieldset: PSMAR
+    - name: PIR
+      description: polling interval register
+      byte_offset: 144
+      fieldset: PIR
+    - name: CCR
+      description: communication configuration register
+      byte_offset: 256
+      fieldset: CCR
+    - name: TCR
+      description: timing configuration register
+      byte_offset: 264
+      fieldset: TCR
+    - name: IR
+      description: instruction register
+      byte_offset: 272
+      fieldset: IR
+    - name: ABR
+      description: alternate bytes register
+      byte_offset: 288
+      fieldset: ABR
+    - name: LPTR
+      description: low-power timeout register
+      byte_offset: 304
+      fieldset: LPTR
+    - name: WPCCR
+      description: wrap communication configuration register
+      byte_offset: 320
+      fieldset: WPCCR
+    - name: WPTCR
+      description: wrap timing configuration register
+      byte_offset: 328
+      fieldset: WPTCR
+    - name: WPIR
+      description: wrap instruction register
+      byte_offset: 336
+      fieldset: WPIR
+    - name: WPABR
+      description: wrap alternate bytes register
+      byte_offset: 352
+      fieldset: WPABR
+    - name: WCCR
+      description: write communication configuration register
+      byte_offset: 384
+      fieldset: WCCR
+    - name: WTCR
+      description: write timing configuration register
+      byte_offset: 392
+      fieldset: WTCR
+    - name: WIR
+      description: write instruction register
+      byte_offset: 400
+      fieldset: WIR
+    - name: WABR
+      description: write alternate bytes register
+      byte_offset: 416
+      fieldset: WABR
+    - name: HLCR
+      description: HyperBusTM latency configuration register
+      byte_offset: 512
+      fieldset: HLCR
+fieldset/ABR:
+  description: alternate bytes register
+  fields:
+    - name: ALTERNATE
+      description: Alternate bytes
+      bit_offset: 0
+      bit_size: 32
+fieldset/AR:
+  description: address register
+  fields:
+    - name: ADDRESS
+      description: Adress
+      bit_offset: 0
+      bit_size: 32
+fieldset/CCR:
+  description: communication configuration register
+  fields:
+    - name: IMODE
+      description: Instruction mode
+      bit_offset: 0
+      bit_size: 3
+    - name: IDTR
+      description: Instruction double transfer rate
+      bit_offset: 3
+      bit_size: 1
+    - name: ISIZE
+      description: Instruction size
+      bit_offset: 4
+      bit_size: 2
+    - name: ADMODE
+      description: Address mode
+      bit_offset: 8
+      bit_size: 3
+    - name: ADDTR
+      description: Address double transfer rate
+      bit_offset: 11
+      bit_size: 1
+    - name: ADSIZE
+      description: Address size
+      bit_offset: 12
+      bit_size: 2
+    - name: ABMODE
+      description: Alternate byte mode
+      bit_offset: 16
+      bit_size: 3
+    - name: ABDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 19
+      bit_size: 1
+    - name: ABSIZE
+      description: Alternate bytes size
+      bit_offset: 20
+      bit_size: 2
+    - name: DMODE
+      description: Data mode
+      bit_offset: 24
+      bit_size: 3
+    - name: DDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 27
+      bit_size: 1
+    - name: DQSE
+      description: DQS enable
+      bit_offset: 29
+      bit_size: 1
+    - name: SIOO
+      description: Send instruction only once mode
+      bit_offset: 31
+      bit_size: 1
+fieldset/CR:
+  description: control register
+  fields:
+    - name: EN
+      description: Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: ABORT
+      description: Abort request
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAEN
+      description: DMA enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TCEN
+      description: Timeout counter enable
+      bit_offset: 3
+      bit_size: 1
+    - name: DQM
+      description: Dual-quad mode
+      bit_offset: 6
+      bit_size: 1
+    - name: FSEL
+      description: FLASH memory selection
+      bit_offset: 7
+      bit_size: 1
+    - name: FTHRES
+      description: IFO threshold level
+      bit_offset: 8
+      bit_size: 5
+    - name: TEIE
+      description: Transfer error interrupt enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TCIE
+      description: Transfer complete interrupt enable
+      bit_offset: 17
+      bit_size: 1
+    - name: FTIE
+      description: FIFO threshold interrupt enable
+      bit_offset: 18
+      bit_size: 1
+    - name: SMIE
+      description: Status match interrupt enable
+      bit_offset: 19
+      bit_size: 1
+    - name: TOIE
+      description: TimeOut interrupt enable
+      bit_offset: 20
+      bit_size: 1
+    - name: APMS
+      description: Automatic poll mode stop
+      bit_offset: 22
+      bit_size: 1
+    - name: PMM
+      description: Polling match mode
+      bit_offset: 23
+      bit_size: 1
+    - name: FMODE
+      description: Functional mode
+      bit_offset: 28
+      bit_size: 2
+fieldset/DCR1:
+  description: device configuration register
+  fields:
+    - name: CKMODE
+      description: Mode 0 / mode 3
+      bit_offset: 0
+      bit_size: 1
+    - name: FRCK
+      description: Free running clock
+      bit_offset: 1
+      bit_size: 1
+    - name: DLYBYP
+      description: Delay block bypass
+      bit_offset: 3
+      bit_size: 1
+    - name: CSHT
+      description: Chip-select high time
+      bit_offset: 8
+      bit_size: 3
+    - name: DEVSIZE
+      description: Device size
+      bit_offset: 16
+      bit_size: 5
+    - name: MTYP
+      description: Memory type
+      bit_offset: 24
+      bit_size: 3
+fieldset/DCR2:
+  description: device configuration register 2
+  fields:
+    - name: PRESCALER
+      description: Clock prescaler
+      bit_offset: 0
+      bit_size: 8
+    - name: WRAPSIZE
+      description: Wrap size
+      bit_offset: 16
+      bit_size: 3
+fieldset/DCR3:
+  description: device configuration register 3
+  fields:
+    - name: MAXTRAN
+      description: Maximum transfer
+      bit_offset: 0
+      bit_size: 8
+    - name: CSBOUND
+      description: CS boundary
+      bit_offset: 16
+      bit_size: 5
+fieldset/DCR4:
+  description: DCR4
+  fields:
+    - name: REFRESH
+      description: Refresh rate
+      bit_offset: 0
+      bit_size: 32
+fieldset/DLR:
+  description: data length register
+  fields:
+    - name: DL
+      description: Data length
+      bit_offset: 0
+      bit_size: 32
+fieldset/DR:
+  description: data register
+  fields:
+    - name: DATA
+      description: Data
+      bit_offset: 0
+      bit_size: 32
+fieldset/FCR:
+  description: flag clear register
+  fields:
+    - name: CTEF
+      description: Clear transfer error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: CTCF
+      description: Clear transfer complete flag
+      bit_offset: 1
+      bit_size: 1
+    - name: CSMF
+      description: Clear status match flag
+      bit_offset: 3
+      bit_size: 1
+    - name: CTOF
+      description: Clear timeout flag
+      bit_offset: 4
+      bit_size: 1
+fieldset/HLCR:
+  description: HyperBusTM latency configuration register
+  fields:
+    - name: LM
+      description: Latency mode
+      bit_offset: 0
+      bit_size: 1
+    - name: WZL
+      description: Write zero latency
+      bit_offset: 1
+      bit_size: 1
+    - name: TACC
+      description: Access time
+      bit_offset: 8
+      bit_size: 8
+    - name: TRWR
+      description: Read write recovery time
+      bit_offset: 16
+      bit_size: 8
+fieldset/IR:
+  description: instruction register
+  fields:
+    - name: INSTRUCTION
+      description: INSTRUCTION
+      bit_offset: 0
+      bit_size: 32
+fieldset/LPTR:
+  description: low-power timeout register
+  fields:
+    - name: TIMEOUT
+      description: Timeout period
+      bit_offset: 0
+      bit_size: 16
+fieldset/PIR:
+  description: OCTOSPI polling interval register
+  fields:
+    - name: INTERVAL
+      description: Polling interval
+      bit_offset: 0
+      bit_size: 16
+fieldset/PSMAR:
+  description: polling status match register
+  fields:
+    - name: MATCH
+      description: Status match
+      bit_offset: 0
+      bit_size: 32
+fieldset/PSMKR:
+  description: polling status mask register
+  fields:
+    - name: MASK
+      description: Status mask
+      bit_offset: 0
+      bit_size: 32
+fieldset/SR:
+  description: status register
+  fields:
+    - name: TEF
+      description: Transfer error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: TCF
+      description: Transfer complete flag
+      bit_offset: 1
+      bit_size: 1
+    - name: FTF
+      description: FIFO threshold flag
+      bit_offset: 2
+      bit_size: 1
+    - name: SMF
+      description: Status match flag
+      bit_offset: 3
+      bit_size: 1
+    - name: TOF
+      description: Timeout flag
+      bit_offset: 4
+      bit_size: 1
+    - name: BUSY
+      description: Busy
+      bit_offset: 5
+      bit_size: 1
+    - name: FLEVEL
+      description: FIFO level
+      bit_offset: 8
+      bit_size: 6
+fieldset/TCR:
+  description: timing configuration register
+  fields:
+    - name: DCYC
+      description: Number of dummy cycles
+      bit_offset: 0
+      bit_size: 5
+    - name: DHQC
+      description: Delay hold quarter cycle
+      bit_offset: 28
+      bit_size: 1
+    - name: SSHIFT
+      description: Sample shift
+      bit_offset: 30
+      bit_size: 1
+fieldset/WABR:
+  description: write alternate bytes register
+  fields:
+    - name: ALTERNATE
+      description: Alternate bytes
+      bit_offset: 0
+      bit_size: 32
+fieldset/WCCR:
+  description: write communication configuration register
+  fields:
+    - name: IMODE
+      description: Instruction mode
+      bit_offset: 0
+      bit_size: 3
+    - name: IDTR
+      description: Instruction double transfer rate
+      bit_offset: 2
+      bit_size: 1
+    - name: ISIZE
+      description: Instruction size
+      bit_offset: 4
+      bit_size: 2
+    - name: ADMODE
+      description: Address mode
+      bit_offset: 8
+      bit_size: 3
+    - name: ADDTR
+      description: Address double transfer rate
+      bit_offset: 11
+      bit_size: 1
+    - name: ADSIZE
+      description: Address size
+      bit_offset: 12
+      bit_size: 2
+    - name: ABMODE
+      description: Alternate-byte mode
+      bit_offset: 16
+      bit_size: 3
+    - name: ABDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 19
+      bit_size: 1
+    - name: ABSIZE
+      description: Alternate bytes size
+      bit_offset: 20
+      bit_size: 2
+    - name: DMODE
+      description: Data mode
+      bit_offset: 24
+      bit_size: 3
+    - name: DDTR
+      description: alternate bytes double transfer rate
+      bit_offset: 27
+      bit_size: 1
+    - name: DQSE
+      description: DQS enable
+      bit_offset: 29
+      bit_size: 1
+fieldset/WIR:
+  description: write instruction register
+  fields:
+    - name: INSTRUCTION
+      description: INSTRUCTION
+      bit_offset: 0
+      bit_size: 32
+fieldset/WPABR:
+  description: wrap alternate bytes register
+  fields:
+    - name: ALTERNATE
+      description: Alternate bytes
+      bit_offset: 0
+      bit_size: 32
+fieldset/WPCCR:
+  description: Wrap communication configuration register
+  fields:
+    - name: IMODE
+      description: Instruction mode
+      bit_offset: 0
+      bit_size: 3
+    - name: IDTR
+      description: Instruction double transfer rate
+      bit_offset: 3
+      bit_size: 1
+    - name: ISIZE
+      description: Instruction size
+      bit_offset: 4
+      bit_size: 2
+    - name: ADMODE
+      description: Address mode
+      bit_offset: 8
+      bit_size: 3
+    - name: ADDTR
+      description: Address double transfer rate
+      bit_offset: 11
+      bit_size: 1
+    - name: ADSIZE
+      description: Address size
+      bit_offset: 12
+      bit_size: 2
+    - name: ABMODE
+      description: Alternate byte mode
+      bit_offset: 16
+      bit_size: 3
+    - name: ABDTR
+      description: Alternate bytes double transfer rate
+      bit_offset: 19
+      bit_size: 1
+    - name: ABSIZE
+      description: Alternate bytes size
+      bit_offset: 20
+      bit_size: 2
+    - name: DMODE
+      description: Data mode
+      bit_offset: 24
+      bit_size: 3
+    - name: DDTR
+      description: alternate bytes double transfer rate
+      bit_offset: 27
+      bit_size: 1
+    - name: DQSE
+      description: DQS enable
+      bit_offset: 29
+      bit_size: 1
+fieldset/WPIR:
+  description: wrap instruction register
+  fields:
+    - name: INSTRUCTION
+      description: INSTRUCTION
+      bit_offset: 0
+      bit_size: 32
+fieldset/WPTCR:
+  description: wrap timing configuration register
+  fields:
+    - name: DCYC
+      description: Number of dummy cycles
+      bit_offset: 0
+      bit_size: 5
+    - name: DHQC
+      description: Delay hold quarter cycle
+      bit_offset: 28
+      bit_size: 1
+    - name: SSHIFT
+      description: Sample shift
+      bit_offset: 30
+      bit_size: 1
+fieldset/WTCR:
+  description: write timing configuration register
+  fields:
+    - name: DCYC
+      description: Number of dummy cycles
+      bit_offset: 0
+      bit_size: 5

data/registers/octospi_v3.yaml

@@ -0,0 +1,578 @@
+block/OCTOSPI:
+  description: OctoSPI
+  items:
+  - name: CR
+    description: control register
+    byte_offset: 0
+    fieldset: CR
+  - name: DCR1
+    description: device configuration register 1
+    byte_offset: 8
+    fieldset: DCR1
+  - name: DCR2
+    description: device configuration register 2
+    byte_offset: 12
+    fieldset: DCR2
+  - name: DCR3
+    description: device configuration register 3
+    byte_offset: 16
+    fieldset: DCR3
+  - name: DCR4
+    description: DCR4
+    byte_offset: 20
+    fieldset: DCR4
+  - name: SR
+    description: status register
+    byte_offset: 32
+    access: Read
+    fieldset: SR
+  - name: FCR
+    description: flag clear register
+    byte_offset: 36
+    access: Write
+    fieldset: FCR
+  - name: DLR
+    description: data length register
+    byte_offset: 64
+    fieldset: DLR
+  - name: AR
+    description: address register
+    byte_offset: 72
+    fieldset: AR
+  - name: DR
+    description: data register
+    byte_offset: 80
+    fieldset: DR
+  - name: PSMKR
+    description: polling status mask register
+    byte_offset: 128
+    fieldset: PSMKR
+  - name: PSMAR
+    description: polling status match register
+    byte_offset: 136
+    fieldset: PSMAR
+  - name: PIR
+    description: polling interval register
+    byte_offset: 144
+    fieldset: PIR
+  - name: CCR
+    description: communication configuration register
+    byte_offset: 256
+    fieldset: CCR
+  - name: TCR
+    description: timing configuration register
+    byte_offset: 264
+    fieldset: TCR
+  - name: IR
+    description: instruction register
+    byte_offset: 272
+    fieldset: IR
+  - name: ABR
+    description: alternate bytes register
+    byte_offset: 288
+    fieldset: ABR
+  - name: LPTR
+    description: low-power timeout register
+    byte_offset: 304
+    fieldset: LPTR
+  - name: WPCCR
+    description: wrap communication configuration register
+    byte_offset: 320
+    fieldset: WPCCR
+  - name: WPTCR
+    description: wrap timing configuration register
+    byte_offset: 328
+    fieldset: WPTCR
+  - name: WPIR
+    description: wrap instruction register
+    byte_offset: 336
+    fieldset: WPIR
+  - name: WPABR
+    description: wrap alternate bytes register
+    byte_offset: 352
+    fieldset: WPABR
+  - name: WCCR
+    description: write communication configuration register
+    byte_offset: 384
+    fieldset: WCCR
+  - name: WTCR
+    description: write timing configuration register
+    byte_offset: 392
+    fieldset: WTCR
+  - name: WIR
+    description: write instruction register
+    byte_offset: 400
+    fieldset: WIR
+  - name: WABR
+    description: write alternate bytes register
+    byte_offset: 416
+    fieldset: WABR
+  - name: HLCR
+    description: HyperBusTM latency configuration register
+    byte_offset: 512
+    fieldset: HLCR
+fieldset/ABR:
+  description: alternate bytes register
+  fields:
+  - name: TIMEOUT
+    description: Timeout period
+    bit_offset: 0
+    bit_size: 16
+fieldset/AR:
+  description: address register
+  fields:
+  - name: DATA
+    description: Data
+    bit_offset: 0
+    bit_size: 32
+fieldset/CCR:
+  description: communication configuration register
+  fields:
+  - name: DCYC
+    description: Number of dummy cycles
+    bit_offset: 0
+    bit_size: 5
+  - name: DHQC
+    description: Delay hold quarter cycle
+    bit_offset: 28
+    bit_size: 1
+  - name: SSHIFT
+    description: Sample shift
+    bit_offset: 30
+    bit_size: 1
+fieldset/CR:
+  description: control register
+  fields:
+  - name: EN
+    description: Enable
+    bit_offset: 0
+    bit_size: 1
+  - name: ABORT
+    description: Abort request
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAEN
+    description: DMA enable
+    bit_offset: 2
+    bit_size: 1
+  - name: TCEN
+    description: Timeout counter enable
+    bit_offset: 3
+    bit_size: 1
+  - name: DQM
+    description: Dual-quad mode
+    bit_offset: 6
+    bit_size: 1
+  - name: FSEL
+    description: FLASH memory selection
+    bit_offset: 7
+    bit_size: 1
+  - name: FTHRES
+    description: IFO threshold level
+    bit_offset: 8
+    bit_size: 5
+  - name: TEIE
+    description: Transfer error interrupt enable
+    bit_offset: 16
+    bit_size: 1
+  - name: TCIE
+    description: Transfer complete interrupt enable
+    bit_offset: 17
+    bit_size: 1
+  - name: FTIE
+    description: FIFO threshold interrupt enable
+    bit_offset: 18
+    bit_size: 1
+  - name: SMIE
+    description: Status match interrupt enable
+    bit_offset: 19
+    bit_size: 1
+  - name: TOIE
+    description: TimeOut interrupt enable
+    bit_offset: 20
+    bit_size: 1
+  - name: APMS
+    description: Automatic poll mode stop
+    bit_offset: 22
+    bit_size: 1
+  - name: PMM
+    description: Polling match mode
+    bit_offset: 23
+    bit_size: 1
+  - name: FMODE
+    description: Functional mode
+    bit_offset: 28
+    bit_size: 2
+fieldset/DCR1:
+  description: device configuration register
+  fields:
+  - name: CKMODE
+    description: Mode 0 / mode 3
+    bit_offset: 0
+    bit_size: 1
+  - name: FRCK
+    description: Free running clock
+    bit_offset: 1
+    bit_size: 1
+  - name: CSHT
+    description: Chip-select high time
+    bit_offset: 8
+    bit_size: 3
+  - name: DEVSIZE
+    description: Device size
+    bit_offset: 16
+    bit_size: 5
+  - name: MTYP
+    description: Memory type
+    bit_offset: 24
+    bit_size: 2
+fieldset/DCR2:
+  description: device configuration register 2
+  fields:
+  - name: PRESCALER
+    description: Clock prescaler
+    bit_offset: 0
+    bit_size: 8
+  - name: WRAPSIZE
+    description: Wrap size
+    bit_offset: 16
+    bit_size: 3
+fieldset/DCR3:
+  description: device configuration register 3
+  fields:
+  - name: CSBOUND
+    description: CS boundary
+    bit_offset: 16
+    bit_size: 5
+fieldset/DCR4:
+  description: DCR4
+  fields:
+  - name: TEF
+    description: Transfer error flag
+    bit_offset: 0
+    bit_size: 1
+  - name: TCF
+    description: Transfer complete flag
+    bit_offset: 1
+    bit_size: 1
+  - name: FTF
+    description: FIFO threshold flag
+    bit_offset: 2
+    bit_size: 1
+  - name: SMF
+    description: Status match flag
+    bit_offset: 3
+    bit_size: 1
+  - name: TOF
+    description: Timeout flag
+    bit_offset: 4
+    bit_size: 1
+  - name: BUSY
+    description: Busy
+    bit_offset: 5
+    bit_size: 1
+  - name: FLEVEL
+    description: FIFO level
+    bit_offset: 8
+    bit_size: 6
+fieldset/DLR:
+  description: data length register
+  fields:
+  - name: ADDRESS
+    description: ADDRESS
+    bit_offset: 0
+    bit_size: 32
+fieldset/DR:
+  description: data register
+  fields:
+  - name: MASK
+    description: Status mask
+    bit_offset: 0
+    bit_size: 32
+fieldset/FCR:
+  description: flag clear register
+  fields:
+  - name: DL
+    description: Data length
+    bit_offset: 0
+    bit_size: 32
+fieldset/HLCR:
+  description: ' HyperBusTM latency configuration register '
+  fields:
+  - name: ALTERNATE
+    description: Alternate bytes
+    bit_offset: 0
+    bit_size: 32
+fieldset/IR:
+  description: instruction register
+  fields:
+  - name: ALTERNATE
+    description: Alternate bytes
+    bit_offset: 0
+    bit_size: 32
+fieldset/LPTR:
+  description: low-power timeout register
+  fields:
+  - name: IMODE
+    description: Instruction mode
+    bit_offset: 0
+    bit_size: 3
+  - name: IDTR
+    description: Instruction double transfer rate
+    bit_offset: 2
+    bit_size: 1
+  - name: ISIZE
+    description: Instruction size
+    bit_offset: 4
+    bit_size: 2
+  - name: ADMODE
+    description: Address mode
+    bit_offset: 8
+    bit_size: 3
+  - name: ADDTR
+    description: Address double transfer rate
+    bit_offset: 11
+    bit_size: 1
+  - name: ADSIZE
+    description: Address size
+    bit_offset: 12
+    bit_size: 2
+  - name: ABMODE
+    description: Alternate-byte mode
+    bit_offset: 16
+    bit_size: 3
+  - name: ABDTR
+    description: Alternate bytes double transfer rate
+    bit_offset: 19
+    bit_size: 1
+  - name: ABSIZE
+    description: Alternate bytes size
+    bit_offset: 20
+    bit_size: 2
+  - name: DMODE
+    description: Data mode
+    bit_offset: 24
+    bit_size: 3
+  - name: DDTR
+    description: alternate bytes double transfer rate
+    bit_offset: 27
+    bit_size: 1
+  - name: DQSE
+    description: DQS enable
+    bit_offset: 29
+    bit_size: 1
+fieldset/PIR:
+  description: polling interval register
+  fields:
+  - name: IMODE
+    description: Instruction mode
+    bit_offset: 0
+    bit_size: 3
+  - name: IDTR
+    description: Instruction double transfer rate
+    bit_offset: 3
+    bit_size: 1
+  - name: ISIZE
+    description: Instruction size
+    bit_offset: 4
+    bit_size: 2
+  - name: ADMODE
+    description: Address mode
+    bit_offset: 8
+    bit_size: 3
+  - name: ADDTR
+    description: Address double transfer rate
+    bit_offset: 11
+    bit_size: 1
+  - name: ADSIZE
+    description: Address size
+    bit_offset: 12
+    bit_size: 2
+  - name: ABMODE
+    description: Alternate byte mode
+    bit_offset: 16
+    bit_size: 3
+  - name: ABDTR
+    description: Alternate bytes double transfer rate
+    bit_offset: 19
+    bit_size: 1
+  - name: ABSIZE
+    description: Alternate bytes size
+    bit_offset: 20
+    bit_size: 2
+  - name: DMODE
+    description: Data mode
+    bit_offset: 24
+    bit_size: 3
+  - name: DDTR
+    description: alternate bytes double transfer rate
+    bit_offset: 27
+    bit_size: 1
+  - name: DQSE
+    description: DQS enable
+    bit_offset: 29
+    bit_size: 1
+  - name: SIOO
+    description: ' Send instruction only once mode '
+    bit_offset: 31
+    bit_size: 1
+fieldset/PSMAR:
+  description: polling status match register
+  fields:
+  - name: INTERVAL
+    description: Polling interval
+    bit_offset: 0
+    bit_size: 16
+fieldset/PSMKR:
+  description: polling status mask register
+  fields:
+  - name: MATCH
+    description: Status match
+    bit_offset: 0
+    bit_size: 32
+fieldset/SR:
+  description: status register
+  fields:
+  - name: CTEF
+    description: Clear transfer error flag
+    bit_offset: 0
+    bit_size: 1
+  - name: CTCF
+    description: ' Clear transfer complete flag '
+    bit_offset: 1
+    bit_size: 1
+  - name: CSMF
+    description: Clear status match flag
+    bit_offset: 3
+    bit_size: 1
+  - name: CTOF
+    description: Clear timeout flag
+    bit_offset: 4
+    bit_size: 1
+fieldset/TCR:
+  description: timing configuration register
+  fields:
+  - name: INSTRUCTION
+    description: INSTRUCTION
+    bit_offset: 0
+    bit_size: 32
+fieldset/WABR:
+  description: WABR
+  fields:
+  - name: INSTRUCTION
+    description: INSTRUCTION
+    bit_offset: 0
+    bit_size: 32
+fieldset/WCCR:
+  description: WCCR
+  fields:
+  - name: REFRESH
+    description: REFRESH
+    bit_offset: 0
+    bit_size: 16
+fieldset/WIR:
+  description: WIR
+  fields:
+  - name: DCYC
+    description: DCYC
+    bit_offset: 0
+    bit_size: 5
+fieldset/WPABR:
+  description: write alternate bytes register
+  fields:
+  - name: LM
+    description: Latency mode
+    bit_offset: 0
+    bit_size: 1
+  - name: WZL
+    description: Write zero latency
+    bit_offset: 1
+    bit_size: 1
+  - name: TACC
+    description: Access time
+    bit_offset: 8
+    bit_size: 8
+  - name: TRWR
+    description: Read write recovery time
+    bit_offset: 16
+    bit_size: 8
+fieldset/WPCCR:
+  description: ' write communication configuration register '
+  fields:
+  - name: DCYC
+    description: Number of dummy cycles
+    bit_offset: 0
+    bit_size: 5
+  - name: DHQC
+    description: Delay hold quarter cycle
+    bit_offset: 28
+    bit_size: 1
+  - name: SSHIFT
+    description: Sample shift
+    bit_offset: 30
+    bit_size: 1
+fieldset/WPIR:
+  description: write instruction register
+  fields:
+  - name: ALTERNATE
+    description: Alternate bytes
+    bit_offset: 0
+    bit_size: 32
+fieldset/WPTCR:
+  description: write timing configuration register
+  fields:
+  - name: INSTRUCTION
+    description: INSTRUCTION
+    bit_offset: 0
+    bit_size: 32
+fieldset/WTCR:
+  description: write timing configuration register
+  fields:
+  - name: IMODE
+    description: IMODE
+    bit_offset: 0
+    bit_size: 3
+  - name: IDTR
+    description: IDTR
+    bit_offset: 3
+    bit_size: 1
+  - name: ISIZE
+    description: ISIZE
+    bit_offset: 4
+    bit_size: 2
+  - name: ADMODE
+    description: ADMODE
+    bit_offset: 8
+    bit_size: 3
+  - name: ADDTR
+    description: ADDTR
+    bit_offset: 11
+    bit_size: 1
+  - name: ADSIZE
+    description: ADSIZE
+    bit_offset: 12
+    bit_size: 2
+  - name: ABMODE
+    description: ABMODE
+    bit_offset: 16
+    bit_size: 3
+  - name: ABDTR
+    description: ABDTR
+    bit_offset: 19
+    bit_size: 1
+  - name: ABSIZE
+    description: ABSIZE
+    bit_offset: 20
+    bit_size: 2
+  - name: DMODE
+    description: DMODE
+    bit_offset: 24
+    bit_size: 3
+  - name: DDTR
+    description: DDTR
+    bit_offset: 27
+    bit_size: 1
+  - name: DQSE
+    description: DQSE
+    bit_offset: 29
+    bit_size: 1

data/registers/octospim_v1.yaml

@@ -0,0 +1,97 @@
+block/OCTOSPIM:
+  description: OctoSPI IO Manager
+  items:
+  - name: P1CR
+    description: OctoSPI IO Manager Port 1 Configuration Register
+    byte_offset: 4
+    fieldset: P1CR
+  - name: P2CR
+    description: OctoSPI IO Manager Port 2 Configuration Register
+    byte_offset: 8
+    fieldset: P2CR
+fieldset/P1CR:
+  description: OctoSPI IO Manager Port 1 Configuration Register
+  fields:
+  - name: CLKEN
+    description: CLK/CLK Enable for Port
+    bit_offset: 0
+    bit_size: 1
+  - name: CLKSRC
+    description: CLK/CLK Source for Port
+    bit_offset: 1
+    bit_size: 1
+  - name: DQSEN
+    description: DQS Enable for Port
+    bit_offset: 4
+    bit_size: 1
+  - name: DQSSRC
+    description: DQS Source for Port
+    bit_offset: 5
+    bit_size: 1
+  - name: NCSEN
+    description: CS Enable for Port
+    bit_offset: 8
+    bit_size: 1
+  - name: NCSSRC
+    description: CS Source for Port
+    bit_offset: 9
+    bit_size: 1
+  - name: IOLEN
+    description: Enable for Port
+    bit_offset: 16
+    bit_size: 1
+  - name: IOLSRC
+    description: Source for Port
+    bit_offset: 17
+    bit_size: 2
+  - name: IOHEN
+    description: Enable for Port n
+    bit_offset: 24
+    bit_size: 1
+  - name: IOHSRC
+    description: Source for Port
+    bit_offset: 25
+    bit_size: 2
+fieldset/P2CR:
+  description: OctoSPI IO Manager Port 2 Configuration Register
+  fields:
+  - name: CLKEN
+    description: CLK/CLK Enable for Port
+    bit_offset: 0
+    bit_size: 1
+  - name: CLKSRC
+    description: CLK/CLK Source for Port
+    bit_offset: 1
+    bit_size: 1
+  - name: DQSEN
+    description: DQS Enable for Port
+    bit_offset: 4
+    bit_size: 1
+  - name: DQSSRC
+    description: DQS Source for Port
+    bit_offset: 5
+    bit_size: 1
+  - name: NCSEN
+    description: CS Enable for Port
+    bit_offset: 8
+    bit_size: 1
+  - name: NCSSRC
+    description: CS Source for Port
+    bit_offset: 9
+    bit_size: 1
+  - name: IOLEN
+    description: Enable for Port
+    bit_offset: 16
+    bit_size: 1
+  - name: IOLSRC
+    description: Source for Port
+    bit_offset: 17
+    bit_size: 2
+  - name: IOHEN
+    description: Enable for Port n
+    bit_offset: 24
+    bit_size: 1
+  - name: IOHSRC
+    description: Source for Port
+    bit_offset: 25
+    bit_size: 2

data/registers/octospim_v2.yaml

@@ -0,0 +1,112 @@
+block/OCTOSPIM:
+  description: OctoSPI IO Manager
+  items:
+  - name: CR
+    description: control register
+    byte_offset: 0
+    fieldset: CR
+  - name: P1CR
+    description: OctoSPI IO Manager Port 1 Configuration Register
+    byte_offset: 4
+    fieldset: P1CR
+  - name: P2CR
+    description: OctoSPI IO Manager Port 2 Configuration Register
+    byte_offset: 8
+    fieldset: P2CR
+fieldset/CR:
+  description: control register
+  fields:
+  - name: MUXEN
+    description: Multiplexed mode enable
+    bit_offset: 0
+    bit_size: 1
+  - name: REQ2ACK_TIME
+    description: REQ to ACK time
+    bit_offset: 16
+    bit_size: 8
+fieldset/P1CR:
+  description: OctoSPI IO Manager Port 1 Configuration Register
+  fields:
+  - name: CLKEN
+    description: CLK/CLK Enable for Port
+    bit_offset: 0
+    bit_size: 1
+  - name: CLKSRC
+    description: CLK/CLK Source for Port
+    bit_offset: 1
+    bit_size: 1
+  - name: DQSEN
+    description: DQS Enable for Port
+    bit_offset: 4
+    bit_size: 1
+  - name: DQSSRC
+    description: DQS Source for Port
+    bit_offset: 5
+    bit_size: 1
+  - name: NCSEN
+    description: CS Enable for Port
+    bit_offset: 8
+    bit_size: 1
+  - name: NCSSRC
+    description: CS Source for Port
+    bit_offset: 9
+    bit_size: 1
+  - name: IOLEN
+    description: Enable for Port
+    bit_offset: 16
+    bit_size: 1
+  - name: IOLSRC
+    description: Source for Port
+    bit_offset: 17
+    bit_size: 2
+  - name: IOHEN
+    description: Enable for Port n
+    bit_offset: 24
+    bit_size: 1
+  - name: IOHSRC
+    description: Source for Port
+    bit_offset: 25
+    bit_size: 2
+fieldset/P2CR:
+  description: OctoSPI IO Manager Port 2 Configuration Register
+  fields:
+  - name: CLKEN
+    description: CLK/CLK Enable for Port
+    bit_offset: 0
+    bit_size: 1
+  - name: CLKSRC
+    description: CLK/CLK Source for Port
+    bit_offset: 1
+    bit_size: 1
+  - name: DQSEN
+    description: DQS Enable for Port
+    bit_offset: 4
+    bit_size: 1
+  - name: DQSSRC
+    description: DQS Source for Port
+    bit_offset: 5
+    bit_size: 1
+  - name: NCSEN
+    description: CS Enable for Port
+    bit_offset: 8
+    bit_size: 1
+  - name: NCSSRC
+    description: CS Source for Port
+    bit_offset: 9
+    bit_size: 1
+  - name: IOLEN
+    description: Enable for Port
+    bit_offset: 16
+    bit_size: 1
+  - name: IOLSRC
+    description: Source for Port
+    bit_offset: 17
+    bit_size: 2
+  - name: IOHEN
+    description: Enable for Port n
+    bit_offset: 24
+    bit_size: 1
+  - name: IOHSRC
+    description: Source for Port
+    bit_offset: 25
+    bit_size: 2