New peripherals: octospim_v1+v2, and octospi_v1-v4
This commit is contained in:
JackN
parent
a40d19e6e9
commit
e933ee6cc4
542
data/registers/octospi_v1.yaml
Normal file
542
data/registers/octospi_v1.yaml
Normal file
@ -0,0 +1,542 @@
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block/OCTOSPI:
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description: OctoSPI
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items:
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- name: CR
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description: control register
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byte_offset: 0
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fieldset: CR
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- name: DCR1
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description: device configuration register
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byte_offset: 8
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fieldset: DCR1
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- name: DCR2
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description: device configuration register 2
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byte_offset: 12
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fieldset: DCR2
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- name: DCR3
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description: device configuration register 3
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byte_offset: 16
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fieldset: DCR3
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- name: SR
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description: status register
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byte_offset: 32
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fieldset: SR
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- name: FCR
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description: flag clear register
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byte_offset: 36
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access: Write
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fieldset: FCR
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- name: DLR
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description: data length register
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byte_offset: 64
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fieldset: DLR
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- name: AR
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description: address register
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byte_offset: 72
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fieldset: AR
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- name: DR
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description: data register
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byte_offset: 80
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fieldset: DR
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- name: PSMKR
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description: polling status mask register
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byte_offset: 128
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fieldset: PSMKR
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- name: PSMAR
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description: polling status match register
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byte_offset: 136
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fieldset: PSMAR
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- name: PIR
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description: polling interval register
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byte_offset: 144
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fieldset: PIR
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- name: CCR
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description: communication configuration register
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byte_offset: 256
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fieldset: CCR
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- name: TCR
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description: timing configuration register
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byte_offset: 264
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fieldset: TCR
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- name: IR
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description: instruction register
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byte_offset: 272
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fieldset: IR
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- name: ABR
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description: alternate bytes register
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byte_offset: 288
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fieldset: ABR
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- name: LPTR
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description: low-power timeout register
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byte_offset: 304
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fieldset: LPTR
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- name: WCCR
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description: write communication configuration register
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byte_offset: 384
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fieldset: WCCR
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- name: WTCR
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description: write timing configuration register
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byte_offset: 392
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fieldset: WTCR
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- name: WIR
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description: write instruction register
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byte_offset: 400
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fieldset: WIR
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- name: WABR
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description: write alternate bytes register
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byte_offset: 416
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fieldset: WABR
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- name: HLCR
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description: HyperBusTM latency configuration register
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byte_offset: 512
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fieldset: HLCR
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- name: HWCFGR
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description: HW configuration register
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byte_offset: 1008
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access: Read
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fieldset: HWCFGR
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- name: VER
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description: version register
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byte_offset: 1012
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access: Read
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fieldset: VER
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- name: ID
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description: identification
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byte_offset: 1016
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access: Read
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fieldset: ID
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- name: MID
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description: magic ID
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byte_offset: 1020
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access: Read
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fieldset: MID
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fieldset/ABR:
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description: alternate bytes register
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fields:
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- name: ALTERNATE
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description: Alternate bytes
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bit_offset: 0
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bit_size: 32
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fieldset/AR:
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description: address register
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fields:
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- name: ADDRESS
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description: ADDRESS
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bit_offset: 0
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bit_size: 32
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fieldset/CCR:
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description: communication configuration register
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fields:
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- name: IMODE
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description: Instruction mode
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bit_offset: 0
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bit_size: 3
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- name: IDTR
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description: Instruction double transfer rate
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bit_offset: 3
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bit_size: 1
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- name: ISIZE
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description: Instruction size
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bit_offset: 4
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bit_size: 2
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- name: ADMODE
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description: Address mode
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bit_offset: 8
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bit_size: 3
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- name: ADDTR
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description: Address double transfer rate
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bit_offset: 11
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bit_size: 1
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- name: ADSIZE
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description: Address size
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bit_offset: 12
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bit_size: 2
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- name: ABMODE
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description: Alternate byte mode
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bit_offset: 16
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bit_size: 3
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- name: ABDTR
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description: Alternate bytes double transfer rate
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bit_offset: 19
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bit_size: 1
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- name: ABSIZE
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description: Alternate bytes size
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bit_offset: 20
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bit_size: 2
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- name: DMODE
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description: Data mode
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bit_offset: 24
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bit_size: 3
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- name: DDTR
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description: Alternate bytes double transfer rate
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bit_offset: 27
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bit_size: 1
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- name: DQSE
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description: DQS enable
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bit_offset: 29
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bit_size: 1
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- name: SIOO
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description: Send instruction only once mode
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bit_offset: 31
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bit_size: 1
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fieldset/CR:
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description: control register
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fields:
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- name: EN
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description: Enable
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bit_offset: 0
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bit_size: 1
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- name: ABORT
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description: Abort request
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bit_offset: 1
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bit_size: 1
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- name: DMAEN
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description: DMA enable
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bit_offset: 2
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bit_size: 1
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- name: TCEN
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description: Timeout counter enable
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bit_offset: 3
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bit_size: 1
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- name: DQM
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description: Dual-quad mode
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bit_offset: 6
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bit_size: 1
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- name: FSEL
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description: FLASH memory selection
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bit_offset: 7
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bit_size: 1
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- name: FTHRES
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description: IFO threshold level
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bit_offset: 8
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bit_size: 5
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- name: TEIE
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description: Transfer error interrupt enable
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bit_offset: 16
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bit_size: 1
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- name: TCIE
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description: Transfer complete interrupt enable
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bit_offset: 17
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bit_size: 1
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- name: FTIE
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description: FIFO threshold interrupt enable
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bit_offset: 18
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bit_size: 1
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- name: SMIE
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description: Status match interrupt enable
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bit_offset: 19
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bit_size: 1
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- name: TOIE
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description: TimeOut interrupt enable
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bit_offset: 20
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bit_size: 1
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- name: APMS
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description: Automatic poll mode stop
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bit_offset: 22
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bit_size: 1
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- name: PMM
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description: Polling match mode
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bit_offset: 23
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bit_size: 1
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- name: FMODE
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description: Functional mode
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bit_offset: 28
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bit_size: 2
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fieldset/DCR1:
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description: device configuration register
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fields:
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- name: CKMODE
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description: Mode 0 / mode 3
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bit_offset: 0
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bit_size: 1
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- name: FRCK
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description: Free running clock
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bit_offset: 1
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bit_size: 1
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- name: CSHT
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description: Chip-select high time
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bit_offset: 8
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bit_size: 3
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- name: DEVSIZE
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description: Device size
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bit_offset: 16
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bit_size: 5
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- name: MTYP
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description: Memory type
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bit_offset: 24
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bit_size: 2
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fieldset/DCR2:
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description: device configuration register 2
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fields:
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- name: PRESCALER
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description: Clock prescaler
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bit_offset: 0
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bit_size: 8
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- name: WRAPSIZE
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description: Wrap size
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bit_offset: 16
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bit_size: 3
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fieldset/DCR3:
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description: device configuration register 3
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fields:
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- name: CSBOUND
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description: CS boundary
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bit_offset: 16
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bit_size: 5
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fieldset/DLR:
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description: data length register
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fields:
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- name: DL
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description: Data length
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bit_offset: 0
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bit_size: 32
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fieldset/DR:
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description: data register
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fields:
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- name: DATA
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description: Data
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bit_offset: 0
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bit_size: 32
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fieldset/FCR:
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description: flag clear register
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fields:
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- name: CTEF
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description: Clear transfer error flag
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bit_offset: 0
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bit_size: 1
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- name: CTCF
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description: Clear transfer complete flag
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bit_offset: 1
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bit_size: 1
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- name: CSMF
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description: Clear status match flag
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bit_offset: 3
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bit_size: 1
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- name: CTOF
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description: Clear timeout flag
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bit_offset: 4
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bit_size: 1
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fieldset/HLCR:
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description: HyperBusTM latency configuration register
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fields:
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- name: LM
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description: Latency mode
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bit_offset: 0
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bit_size: 1
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- name: WZL
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description: Write zero latency
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bit_offset: 1
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bit_size: 1
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- name: TACC
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description: Access time
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bit_offset: 8
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bit_size: 8
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- name: TRWR
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description: Read write recovery time
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bit_offset: 16
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bit_size: 8
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fieldset/HWCFGR:
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description: HW configuration register
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fields:
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- name: AXI
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description: AXI interface
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bit_offset: 0
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bit_size: 4
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- name: FIFO
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description: FIFO depth
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bit_offset: 4
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bit_size: 8
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- name: PRES
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description: Prescaler
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bit_offset: 12
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bit_size: 8
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- name: IDL
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description: ID Length
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bit_offset: 20
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bit_size: 4
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- name: MMW
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description: Memory map write
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bit_offset: 24
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bit_size: 4
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- name: MST
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description: Master
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bit_offset: 28
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bit_size: 4
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fieldset/ID:
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description: identification
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fields:
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- name: ID
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description: Identification
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bit_offset: 0
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bit_size: 32
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fieldset/IR:
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description: instruction register
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fields:
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- name: INSTRUCTION
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description: INSTRUCTION
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bit_offset: 0
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bit_size: 32
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fieldset/LPTR:
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description: low-power timeout register
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fields:
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- name: TIMEOUT
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description: Timeout period
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bit_offset: 0
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bit_size: 16
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fieldset/MID:
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description: magic ID
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fields:
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- name: MID
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description: Magic ID
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bit_offset: 0
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bit_size: 32
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fieldset/PIR:
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description: polling interval register
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fields:
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- name: INTERVAL
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description: Polling interval
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bit_offset: 0
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bit_size: 16
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fieldset/PSMAR:
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description: polling status match register
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fields:
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- name: MATCH
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description: Status match
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bit_offset: 0
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bit_size: 32
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fieldset/PSMKR:
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description: polling status mask register
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fields:
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- name: MASK
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description: Status mask
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bit_offset: 0
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bit_size: 32
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fieldset/SR:
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description: status register
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fields:
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- name: TEF
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description: Transfer error flag
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bit_offset: 0
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bit_size: 1
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- name: TCF
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description: Transfer complete flag
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bit_offset: 1
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bit_size: 1
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- name: FTF
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description: FIFO threshold flag
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bit_offset: 2
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bit_size: 1
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- name: SMF
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description: Status match flag
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bit_offset: 3
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bit_size: 1
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- name: TOF
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description: Timeout flag
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bit_offset: 4
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bit_size: 1
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- name: BUSY
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description: BUSY
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bit_offset: 5
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bit_size: 1
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- name: FLEVEL
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description: FIFO level
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bit_offset: 8
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bit_size: 6
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fieldset/TCR:
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||||||
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description: timing configuration register
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||||||
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fields:
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- name: DCYC
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description: Number of dummy cycles
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bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
- name: DHQC
|
||||||
|
description: Delay hold quarter cycle
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: SSHIFT
|
||||||
|
description: Sample shift
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/VER:
|
||||||
|
description: version register
|
||||||
|
fields:
|
||||||
|
- name: VER
|
||||||
|
description: Version
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
fieldset/WABR:
|
||||||
|
description: write alternate bytes register
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WCCR:
|
||||||
|
description: write communication configuration register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: Instruction mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: Instruction double transfer rate
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: Instruction size
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: Address mode
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: Address double transfer rate
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: Address size
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: Alternate byte mode
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: Alternate bytes size
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: Data mode
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: alternate bytes double transfer rate
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQS enable
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: SIOO
|
||||||
|
description: Send instruction only once mode
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WIR:
|
||||||
|
description: write instruction register
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WTCR:
|
||||||
|
description: write timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: Number of dummy cycles
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
586
data/registers/octospi_v2.yaml
Normal file
586
data/registers/octospi_v2.yaml
Normal file
@ -0,0 +1,586 @@
|
|||||||
|
block/OCTOSPI:
|
||||||
|
description: OctoSPI
|
||||||
|
items:
|
||||||
|
- name: CR
|
||||||
|
description: control register
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: CR
|
||||||
|
- name: DCR1
|
||||||
|
description: device configuration register 1
|
||||||
|
byte_offset: 8
|
||||||
|
fieldset: DCR1
|
||||||
|
- name: DCR2
|
||||||
|
description: device configuration register 2
|
||||||
|
byte_offset: 12
|
||||||
|
fieldset: DCR2
|
||||||
|
- name: DCR3
|
||||||
|
description: device configuration register 3
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: DCR3
|
||||||
|
- name: DCR4
|
||||||
|
description: DCR4
|
||||||
|
byte_offset: 20
|
||||||
|
fieldset: DCR4
|
||||||
|
- name: SR
|
||||||
|
description: status register
|
||||||
|
byte_offset: 32
|
||||||
|
access: Read
|
||||||
|
fieldset: SR
|
||||||
|
- name: FCR
|
||||||
|
description: flag clear register
|
||||||
|
byte_offset: 36
|
||||||
|
access: Write
|
||||||
|
fieldset: FCR
|
||||||
|
- name: DLR
|
||||||
|
description: data length register
|
||||||
|
byte_offset: 64
|
||||||
|
fieldset: DLR
|
||||||
|
- name: AR
|
||||||
|
description: address register
|
||||||
|
byte_offset: 72
|
||||||
|
fieldset: AR
|
||||||
|
- name: DR
|
||||||
|
description: data register
|
||||||
|
byte_offset: 80
|
||||||
|
fieldset: DR
|
||||||
|
- name: PSMKR
|
||||||
|
description: polling status mask register
|
||||||
|
byte_offset: 128
|
||||||
|
fieldset: PSMKR
|
||||||
|
- name: PSMAR
|
||||||
|
description: polling status match register
|
||||||
|
byte_offset: 136
|
||||||
|
fieldset: PSMAR
|
||||||
|
- name: PIR
|
||||||
|
description: polling interval register
|
||||||
|
byte_offset: 144
|
||||||
|
fieldset: PIR
|
||||||
|
- name: CCR
|
||||||
|
description: communication configuration register
|
||||||
|
byte_offset: 256
|
||||||
|
fieldset: CCR
|
||||||
|
- name: TCR
|
||||||
|
description: timing configuration register
|
||||||
|
byte_offset: 264
|
||||||
|
fieldset: TCR
|
||||||
|
- name: IR
|
||||||
|
description: instruction register
|
||||||
|
byte_offset: 272
|
||||||
|
fieldset: IR
|
||||||
|
- name: ABR
|
||||||
|
description: alternate bytes register
|
||||||
|
byte_offset: 288
|
||||||
|
fieldset: ABR
|
||||||
|
- name: LPTR
|
||||||
|
description: low-power timeout register
|
||||||
|
byte_offset: 304
|
||||||
|
fieldset: LPTR
|
||||||
|
- name: WPCCR
|
||||||
|
description: wrap communication configuration register
|
||||||
|
byte_offset: 320
|
||||||
|
fieldset: WPCCR
|
||||||
|
- name: WPTCR
|
||||||
|
description: wrap timing configuration register
|
||||||
|
byte_offset: 328
|
||||||
|
fieldset: WPTCR
|
||||||
|
- name: WPIR
|
||||||
|
description: wrap instruction register
|
||||||
|
byte_offset: 336
|
||||||
|
fieldset: WPIR
|
||||||
|
- name: WPABR
|
||||||
|
description: wrap alternate bytes register
|
||||||
|
byte_offset: 352
|
||||||
|
fieldset: WPABR
|
||||||
|
- name: WCCR
|
||||||
|
description: write communication configuration register
|
||||||
|
byte_offset: 384
|
||||||
|
fieldset: WCCR
|
||||||
|
- name: WTCR
|
||||||
|
description: write timing configuration register
|
||||||
|
byte_offset: 392
|
||||||
|
fieldset: WTCR
|
||||||
|
- name: WIR
|
||||||
|
description: write instruction register
|
||||||
|
byte_offset: 400
|
||||||
|
fieldset: WIR
|
||||||
|
- name: WABR
|
||||||
|
description: write alternate bytes register
|
||||||
|
byte_offset: 416
|
||||||
|
fieldset: WABR
|
||||||
|
- name: HLCR
|
||||||
|
description: HyperBusTM latency configuration register
|
||||||
|
byte_offset: 512
|
||||||
|
fieldset: HLCR
|
||||||
|
fieldset/ABR:
|
||||||
|
description: alternate bytes register
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/AR:
|
||||||
|
description: address register
|
||||||
|
fields:
|
||||||
|
- name: ADDRESS
|
||||||
|
description: Adress
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/CCR:
|
||||||
|
description: communication configuration register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: Instruction mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: Instruction double transfer rate
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: Instruction size
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: Address mode
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: Address double transfer rate
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: Address size
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: Alternate byte mode
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: Alternate bytes size
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: Data mode
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQS enable
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: SIOO
|
||||||
|
description: Send instruction only once mode
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CR:
|
||||||
|
description: control register
|
||||||
|
fields:
|
||||||
|
- name: EN
|
||||||
|
description: Enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABORT
|
||||||
|
description: Abort request
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DMAEN
|
||||||
|
description: DMA enable
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: TCEN
|
||||||
|
description: Timeout counter enable
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQM
|
||||||
|
description: Dual-quad mode
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: FSEL
|
||||||
|
description: FLASH memory selection
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: FTHRES
|
||||||
|
description: IFO threshold level
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 5
|
||||||
|
- name: TEIE
|
||||||
|
description: Transfer error interrupt enable
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: TCIE
|
||||||
|
description: Transfer complete interrupt enable
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: FTIE
|
||||||
|
description: FIFO threshold interrupt enable
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: SMIE
|
||||||
|
description: Status match interrupt enable
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: TOIE
|
||||||
|
description: TimeOut interrupt enable
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: APMS
|
||||||
|
description: Automatic poll mode stop
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: PMM
|
||||||
|
description: Polling match mode
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: FMODE
|
||||||
|
description: Functional mode
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/DCR1:
|
||||||
|
description: device configuration register
|
||||||
|
fields:
|
||||||
|
- name: CKMODE
|
||||||
|
description: Mode 0 / mode 3
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: FRCK
|
||||||
|
description: Free running clock
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DLYBYP
|
||||||
|
description: Delay block bypass
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSHT
|
||||||
|
description: Chip-select high time
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: DEVSIZE
|
||||||
|
description: Device size
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 5
|
||||||
|
- name: MTYP
|
||||||
|
description: Memory type
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/DCR2:
|
||||||
|
description: device configuration register 2
|
||||||
|
fields:
|
||||||
|
- name: PRESCALER
|
||||||
|
description: Clock prescaler
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
- name: WRAPSIZE
|
||||||
|
description: Wrap size
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/DCR3:
|
||||||
|
description: device configuration register 3
|
||||||
|
fields:
|
||||||
|
- name: MAXTRAN
|
||||||
|
description: Maximum transfer
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
- name: CSBOUND
|
||||||
|
description: CS boundary
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 5
|
||||||
|
fieldset/DCR4:
|
||||||
|
description: DCR4
|
||||||
|
fields:
|
||||||
|
- name: REFRESH
|
||||||
|
description: Refresh rate
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/DLR:
|
||||||
|
description: data length register
|
||||||
|
fields:
|
||||||
|
- name: DL
|
||||||
|
description: Data length
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/DR:
|
||||||
|
description: data register
|
||||||
|
fields:
|
||||||
|
- name: DATA
|
||||||
|
description: Data
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/FCR:
|
||||||
|
description: flag clear register
|
||||||
|
fields:
|
||||||
|
- name: CTEF
|
||||||
|
description: Clear transfer error flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: CTCF
|
||||||
|
description: Clear transfer complete flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSMF
|
||||||
|
description: Clear status match flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: CTOF
|
||||||
|
description: Clear timeout flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/HLCR:
|
||||||
|
description: HyperBusTM latency configuration register
|
||||||
|
fields:
|
||||||
|
- name: LM
|
||||||
|
description: Latency mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: WZL
|
||||||
|
description: Write zero latency
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: TACC
|
||||||
|
description: Access time
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: TRWR
|
||||||
|
description: Read write recovery time
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 8
|
||||||
|
fieldset/IR:
|
||||||
|
description: instruction register
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/LPTR:
|
||||||
|
description: low-power timeout register
|
||||||
|
fields:
|
||||||
|
- name: TIMEOUT
|
||||||
|
description: Timeout period
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/PIR:
|
||||||
|
description: OCTOSPI polling interval register
|
||||||
|
fields:
|
||||||
|
- name: INTERVAL
|
||||||
|
description: Polling interval
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/PSMAR:
|
||||||
|
description: polling status match register
|
||||||
|
fields:
|
||||||
|
- name: MATCH
|
||||||
|
description: Status match
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/PSMKR:
|
||||||
|
description: polling status mask register
|
||||||
|
fields:
|
||||||
|
- name: MASK
|
||||||
|
description: Status mask
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/SR:
|
||||||
|
description: status register
|
||||||
|
fields:
|
||||||
|
- name: TEF
|
||||||
|
description: Transfer error flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: TCF
|
||||||
|
description: Transfer complete flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: FTF
|
||||||
|
description: FIFO threshold flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: SMF
|
||||||
|
description: Status match flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: TOF
|
||||||
|
description: Timeout flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: BUSY
|
||||||
|
description: Busy
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: FLEVEL
|
||||||
|
description: FIFO level
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 6
|
||||||
|
fieldset/TCR:
|
||||||
|
description: timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: Number of dummy cycles
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
- name: DHQC
|
||||||
|
description: Delay hold quarter cycle
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: SSHIFT
|
||||||
|
description: Sample shift
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WABR:
|
||||||
|
description: write alternate bytes register
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WCCR:
|
||||||
|
description: write communication configuration register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: Instruction mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: Instruction double transfer rate
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: Instruction size
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: Address mode
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: Address double transfer rate
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: Address size
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: Alternate-byte mode
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: Alternate bytes size
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: Data mode
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: alternate bytes double transfer rate
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQS enable
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WIR:
|
||||||
|
description: write instruction register
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WPABR:
|
||||||
|
description: wrap alternate bytes register
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WPCCR:
|
||||||
|
description: Wrap communication configuration register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: Instruction mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: Instruction double transfer rate
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: Instruction size
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: Address mode
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: Address double transfer rate
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: Address size
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: Alternate byte mode
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: Alternate bytes size
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: Data mode
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: alternate bytes double transfer rate
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQS enable
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WPIR:
|
||||||
|
description: wrap instruction register
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WPTCR:
|
||||||
|
description: wrap timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: Number of dummy cycles
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
- name: DHQC
|
||||||
|
description: Delay hold quarter cycle
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: SSHIFT
|
||||||
|
description: Sample shift
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WTCR:
|
||||||
|
description: write timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: Number of dummy cycles
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
578
data/registers/octospi_v3.yaml
Normal file
578
data/registers/octospi_v3.yaml
Normal file
@ -0,0 +1,578 @@
|
|||||||
|
block/OCTOSPI:
|
||||||
|
description: OctoSPI
|
||||||
|
items:
|
||||||
|
- name: CR
|
||||||
|
description: control register
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: CR
|
||||||
|
- name: DCR1
|
||||||
|
description: device configuration register 1
|
||||||
|
byte_offset: 8
|
||||||
|
fieldset: DCR1
|
||||||
|
- name: DCR2
|
||||||
|
description: device configuration register 2
|
||||||
|
byte_offset: 12
|
||||||
|
fieldset: DCR2
|
||||||
|
- name: DCR3
|
||||||
|
description: device configuration register 3
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: DCR3
|
||||||
|
- name: DCR4
|
||||||
|
description: DCR4
|
||||||
|
byte_offset: 20
|
||||||
|
fieldset: DCR4
|
||||||
|
- name: SR
|
||||||
|
description: status register
|
||||||
|
byte_offset: 32
|
||||||
|
access: Read
|
||||||
|
fieldset: SR
|
||||||
|
- name: FCR
|
||||||
|
description: flag clear register
|
||||||
|
byte_offset: 36
|
||||||
|
access: Write
|
||||||
|
fieldset: FCR
|
||||||
|
- name: DLR
|
||||||
|
description: data length register
|
||||||
|
byte_offset: 64
|
||||||
|
fieldset: DLR
|
||||||
|
- name: AR
|
||||||
|
description: address register
|
||||||
|
byte_offset: 72
|
||||||
|
fieldset: AR
|
||||||
|
- name: DR
|
||||||
|
description: data register
|
||||||
|
byte_offset: 80
|
||||||
|
fieldset: DR
|
||||||
|
- name: PSMKR
|
||||||
|
description: polling status mask register
|
||||||
|
byte_offset: 128
|
||||||
|
fieldset: PSMKR
|
||||||
|
- name: PSMAR
|
||||||
|
description: polling status match register
|
||||||
|
byte_offset: 136
|
||||||
|
fieldset: PSMAR
|
||||||
|
- name: PIR
|
||||||
|
description: polling interval register
|
||||||
|
byte_offset: 144
|
||||||
|
fieldset: PIR
|
||||||
|
- name: CCR
|
||||||
|
description: communication configuration register
|
||||||
|
byte_offset: 256
|
||||||
|
fieldset: CCR
|
||||||
|
- name: TCR
|
||||||
|
description: timing configuration register
|
||||||
|
byte_offset: 264
|
||||||
|
fieldset: TCR
|
||||||
|
- name: IR
|
||||||
|
description: instruction register
|
||||||
|
byte_offset: 272
|
||||||
|
fieldset: IR
|
||||||
|
- name: ABR
|
||||||
|
description: alternate bytes register
|
||||||
|
byte_offset: 288
|
||||||
|
fieldset: ABR
|
||||||
|
- name: LPTR
|
||||||
|
description: low-power timeout register
|
||||||
|
byte_offset: 304
|
||||||
|
fieldset: LPTR
|
||||||
|
- name: WPCCR
|
||||||
|
description: wrap communication configuration register
|
||||||
|
byte_offset: 320
|
||||||
|
fieldset: WPCCR
|
||||||
|
- name: WPTCR
|
||||||
|
description: wrap timing configuration register
|
||||||
|
byte_offset: 328
|
||||||
|
fieldset: WPTCR
|
||||||
|
- name: WPIR
|
||||||
|
description: wrap instruction register
|
||||||
|
byte_offset: 336
|
||||||
|
fieldset: WPIR
|
||||||
|
- name: WPABR
|
||||||
|
description: wrap alternate bytes register
|
||||||
|
byte_offset: 352
|
||||||
|
fieldset: WPABR
|
||||||
|
- name: WCCR
|
||||||
|
description: write communication configuration register
|
||||||
|
byte_offset: 384
|
||||||
|
fieldset: WCCR
|
||||||
|
- name: WTCR
|
||||||
|
description: write timing configuration register
|
||||||
|
byte_offset: 392
|
||||||
|
fieldset: WTCR
|
||||||
|
- name: WIR
|
||||||
|
description: write instruction register
|
||||||
|
byte_offset: 400
|
||||||
|
fieldset: WIR
|
||||||
|
- name: WABR
|
||||||
|
description: write alternate bytes register
|
||||||
|
byte_offset: 416
|
||||||
|
fieldset: WABR
|
||||||
|
- name: HLCR
|
||||||
|
description: HyperBusTM latency configuration register
|
||||||
|
byte_offset: 512
|
||||||
|
fieldset: HLCR
|
||||||
|
fieldset/ABR:
|
||||||
|
description: alternate bytes register
|
||||||
|
fields:
|
||||||
|
- name: TIMEOUT
|
||||||
|
description: Timeout period
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/AR:
|
||||||
|
description: address register
|
||||||
|
fields:
|
||||||
|
- name: DATA
|
||||||
|
description: Data
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/CCR:
|
||||||
|
description: communication configuration register
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: Number of dummy cycles
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
- name: DHQC
|
||||||
|
description: Delay hold quarter cycle
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: SSHIFT
|
||||||
|
description: Sample shift
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CR:
|
||||||
|
description: control register
|
||||||
|
fields:
|
||||||
|
- name: EN
|
||||||
|
description: Enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABORT
|
||||||
|
description: Abort request
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DMAEN
|
||||||
|
description: DMA enable
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: TCEN
|
||||||
|
description: Timeout counter enable
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQM
|
||||||
|
description: Dual-quad mode
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: FSEL
|
||||||
|
description: FLASH memory selection
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: FTHRES
|
||||||
|
description: IFO threshold level
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 5
|
||||||
|
- name: TEIE
|
||||||
|
description: Transfer error interrupt enable
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: TCIE
|
||||||
|
description: Transfer complete interrupt enable
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: FTIE
|
||||||
|
description: FIFO threshold interrupt enable
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: SMIE
|
||||||
|
description: Status match interrupt enable
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: TOIE
|
||||||
|
description: TimeOut interrupt enable
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: APMS
|
||||||
|
description: Automatic poll mode stop
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: PMM
|
||||||
|
description: Polling match mode
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: FMODE
|
||||||
|
description: Functional mode
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/DCR1:
|
||||||
|
description: device configuration register
|
||||||
|
fields:
|
||||||
|
- name: CKMODE
|
||||||
|
description: Mode 0 / mode 3
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: FRCK
|
||||||
|
description: Free running clock
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSHT
|
||||||
|
description: Chip-select high time
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: DEVSIZE
|
||||||
|
description: Device size
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 5
|
||||||
|
- name: MTYP
|
||||||
|
description: Memory type
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/DCR2:
|
||||||
|
description: device configuration register 2
|
||||||
|
fields:
|
||||||
|
- name: PRESCALER
|
||||||
|
description: Clock prescaler
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
- name: WRAPSIZE
|
||||||
|
description: Wrap size
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/DCR3:
|
||||||
|
description: device configuration register 3
|
||||||
|
fields:
|
||||||
|
- name: CSBOUND
|
||||||
|
description: CS boundary
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 5
|
||||||
|
fieldset/DCR4:
|
||||||
|
description: DCR4
|
||||||
|
fields:
|
||||||
|
- name: TEF
|
||||||
|
description: Transfer error flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: TCF
|
||||||
|
description: Transfer complete flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: FTF
|
||||||
|
description: FIFO threshold flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: SMF
|
||||||
|
description: Status match flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: TOF
|
||||||
|
description: Timeout flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: BUSY
|
||||||
|
description: Busy
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: FLEVEL
|
||||||
|
description: FIFO level
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 6
|
||||||
|
fieldset/DLR:
|
||||||
|
description: data length register
|
||||||
|
fields:
|
||||||
|
- name: ADDRESS
|
||||||
|
description: ADDRESS
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/DR:
|
||||||
|
description: data register
|
||||||
|
fields:
|
||||||
|
- name: MASK
|
||||||
|
description: Status mask
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/FCR:
|
||||||
|
description: flag clear register
|
||||||
|
fields:
|
||||||
|
- name: DL
|
||||||
|
description: Data length
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/HLCR:
|
||||||
|
description: ' HyperBusTM latency configuration register '
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/IR:
|
||||||
|
description: instruction register
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/LPTR:
|
||||||
|
description: low-power timeout register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: Instruction mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: Instruction double transfer rate
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: Instruction size
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: Address mode
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: Address double transfer rate
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: Address size
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: Alternate-byte mode
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: Alternate bytes size
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: Data mode
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: alternate bytes double transfer rate
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQS enable
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PIR:
|
||||||
|
description: polling interval register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: Instruction mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: Instruction double transfer rate
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: Instruction size
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: Address mode
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: Address double transfer rate
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: Address size
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: Alternate byte mode
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: Alternate bytes double transfer rate
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: Alternate bytes size
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: Data mode
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: alternate bytes double transfer rate
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQS enable
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: SIOO
|
||||||
|
description: ' Send instruction only once mode '
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PSMAR:
|
||||||
|
description: polling status match register
|
||||||
|
fields:
|
||||||
|
- name: INTERVAL
|
||||||
|
description: Polling interval
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/PSMKR:
|
||||||
|
description: polling status mask register
|
||||||
|
fields:
|
||||||
|
- name: MATCH
|
||||||
|
description: Status match
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/SR:
|
||||||
|
description: status register
|
||||||
|
fields:
|
||||||
|
- name: CTEF
|
||||||
|
description: Clear transfer error flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: CTCF
|
||||||
|
description: ' Clear transfer complete flag '
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSMF
|
||||||
|
description: Clear status match flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: CTOF
|
||||||
|
description: Clear timeout flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/TCR:
|
||||||
|
description: timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WABR:
|
||||||
|
description: WABR
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WCCR:
|
||||||
|
description: WCCR
|
||||||
|
fields:
|
||||||
|
- name: REFRESH
|
||||||
|
description: REFRESH
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/WIR:
|
||||||
|
description: WIR
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: DCYC
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
fieldset/WPABR:
|
||||||
|
description: write alternate bytes register
|
||||||
|
fields:
|
||||||
|
- name: LM
|
||||||
|
description: Latency mode
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: WZL
|
||||||
|
description: Write zero latency
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: TACC
|
||||||
|
description: Access time
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: TRWR
|
||||||
|
description: Read write recovery time
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 8
|
||||||
|
fieldset/WPCCR:
|
||||||
|
description: ' write communication configuration register '
|
||||||
|
fields:
|
||||||
|
- name: DCYC
|
||||||
|
description: Number of dummy cycles
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
- name: DHQC
|
||||||
|
description: Delay hold quarter cycle
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: SSHIFT
|
||||||
|
description: Sample shift
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WPIR:
|
||||||
|
description: write instruction register
|
||||||
|
fields:
|
||||||
|
- name: ALTERNATE
|
||||||
|
description: Alternate bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WPTCR:
|
||||||
|
description: write timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: INSTRUCTION
|
||||||
|
description: INSTRUCTION
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/WTCR:
|
||||||
|
description: write timing configuration register
|
||||||
|
fields:
|
||||||
|
- name: IMODE
|
||||||
|
description: IMODE
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: IDTR
|
||||||
|
description: IDTR
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ISIZE
|
||||||
|
description: ISIZE
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: ADMODE
|
||||||
|
description: ADMODE
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
- name: ADDTR
|
||||||
|
description: ADDTR
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: ADSIZE
|
||||||
|
description: ADSIZE
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
- name: ABMODE
|
||||||
|
description: ABMODE
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
- name: ABDTR
|
||||||
|
description: ABDTR
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ABSIZE
|
||||||
|
description: ABSIZE
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: DMODE
|
||||||
|
description: DMODE
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
- name: DDTR
|
||||||
|
description: DDTR
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSE
|
||||||
|
description: DQSE
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
1449
data/registers/octospi_v4.yaml
Normal file
1449
data/registers/octospi_v4.yaml
Normal file
File diff suppressed because it is too large
Load Diff
97
data/registers/octospim_v1.yaml
Normal file
97
data/registers/octospim_v1.yaml
Normal file
@ -0,0 +1,97 @@
|
|||||||
|
block/OCTOSPIM:
|
||||||
|
description: OctoSPI IO Manager
|
||||||
|
items:
|
||||||
|
- name: P1CR
|
||||||
|
description: OctoSPI IO Manager Port 1 Configuration Register
|
||||||
|
byte_offset: 4
|
||||||
|
fieldset: P1CR
|
||||||
|
- name: P2CR
|
||||||
|
description: OctoSPI IO Manager Port 2 Configuration Register
|
||||||
|
byte_offset: 8
|
||||||
|
fieldset: P2CR
|
||||||
|
fieldset/P1CR:
|
||||||
|
description: OctoSPI IO Manager Port 1 Configuration Register
|
||||||
|
fields:
|
||||||
|
- name: CLKEN
|
||||||
|
description: CLK/CLK Enable for Port
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLKSRC
|
||||||
|
description: CLK/CLK Source for Port
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSEN
|
||||||
|
description: DQS Enable for Port
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSSRC
|
||||||
|
description: DQS Source for Port
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSEN
|
||||||
|
description: CS Enable for Port
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSSRC
|
||||||
|
description: CS Source for Port
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLEN
|
||||||
|
description: Enable for Port
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 2
|
||||||
|
- name: IOHEN
|
||||||
|
description: Enable for Port n
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOHSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/P2CR:
|
||||||
|
description: OctoSPI IO Manager Port 2 Configuration Register
|
||||||
|
fields:
|
||||||
|
- name: CLKEN
|
||||||
|
description: CLK/CLK Enable for Port
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLKSRC
|
||||||
|
description: CLK/CLK Source for Port
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSEN
|
||||||
|
description: DQS Enable for Port
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSSRC
|
||||||
|
description: DQS Source for Port
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSEN
|
||||||
|
description: CS Enable for Port
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSSRC
|
||||||
|
description: CS Source for Port
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLEN
|
||||||
|
description: Enable for Port
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 2
|
||||||
|
- name: IOHEN
|
||||||
|
description: Enable for Port n
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOHSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 2
|
||||||
112
data/registers/octospim_v2.yaml
Normal file
112
data/registers/octospim_v2.yaml
Normal file
@ -0,0 +1,112 @@
|
|||||||
|
block/OCTOSPIM:
|
||||||
|
description: OctoSPI IO Manager
|
||||||
|
items:
|
||||||
|
- name: CR
|
||||||
|
description: control register
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: CR
|
||||||
|
- name: P1CR
|
||||||
|
description: OctoSPI IO Manager Port 1 Configuration Register
|
||||||
|
byte_offset: 4
|
||||||
|
fieldset: P1CR
|
||||||
|
- name: P2CR
|
||||||
|
description: OctoSPI IO Manager Port 2 Configuration Register
|
||||||
|
byte_offset: 8
|
||||||
|
fieldset: P2CR
|
||||||
|
fieldset/CR:
|
||||||
|
description: control register
|
||||||
|
fields:
|
||||||
|
- name: MUXEN
|
||||||
|
description: Multiplexed mode enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: REQ2ACK_TIME
|
||||||
|
description: REQ to ACK time
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 8
|
||||||
|
fieldset/P1CR:
|
||||||
|
description: OctoSPI IO Manager Port 1 Configuration Register
|
||||||
|
fields:
|
||||||
|
- name: CLKEN
|
||||||
|
description: CLK/CLK Enable for Port
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLKSRC
|
||||||
|
description: CLK/CLK Source for Port
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSEN
|
||||||
|
description: DQS Enable for Port
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSSRC
|
||||||
|
description: DQS Source for Port
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSEN
|
||||||
|
description: CS Enable for Port
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSSRC
|
||||||
|
description: CS Source for Port
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLEN
|
||||||
|
description: Enable for Port
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 2
|
||||||
|
- name: IOHEN
|
||||||
|
description: Enable for Port n
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOHSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/P2CR:
|
||||||
|
description: OctoSPI IO Manager Port 2 Configuration Register
|
||||||
|
fields:
|
||||||
|
- name: CLKEN
|
||||||
|
description: CLK/CLK Enable for Port
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLKSRC
|
||||||
|
description: CLK/CLK Source for Port
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSEN
|
||||||
|
description: DQS Enable for Port
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: DQSSRC
|
||||||
|
description: DQS Source for Port
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSEN
|
||||||
|
description: CS Enable for Port
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: NCSSRC
|
||||||
|
description: CS Source for Port
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLEN
|
||||||
|
description: Enable for Port
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOLSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 2
|
||||||
|
- name: IOHEN
|
||||||
|
description: Enable for Port n
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: IOHSRC
|
||||||
|
description: Source for Port
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 2
|
||||||
Loading…
x
Reference in New Issue
Block a user