guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rcc: add PLL enums.

Browse Source
This commit is contained in:
Dario Nieuwenhuis 2023-10-09 02:44:42 +02:00
parent eecd80c34d
commit e89b8cfc30
19 changed files with 13401 additions and 320 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
data/registers/rcc_f0.yaml
View File

@ -484,11 +484,11 @@ fieldset/CFGR:
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: MCOPRE enum: MCOPRE
- name: PLLNODIV - name: PLLMCODIV
description: PLL clock not divided for MCO description: PLL clock not divided for MCO
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
enum: PLLNODIV enum: PLLMCODIV
fieldset/CFGR2: fieldset/CFGR2:
description: Clock configuration register 2 description: Clock configuration register 2
fields: fields:
@ -869,11 +869,20 @@ enum/MCOSEL:
description: External 4-32 MHz (HSE) oscillator clock selected description: External 4-32 MHz (HSE) oscillator clock selected
value: 6 value: 6
- name: PLL - name: PLL
description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) description: PLL clock selected (divided by 1 or 2, depending en PLLMCODIV)
value: 7 value: 7
- name: HSI48 - name: HSI48
description: Internal RC 48 MHz (HSI48) oscillator clock selected description: Internal RC 48 MHz (HSI48) oscillator clock selected
value: 8 value: 8
enum/PLLMCODIV:
bit_size: 1
variants:
- name: Div2
description: PLL is divided by 2 for MCO
value: 0
- name: Div1
description: PLL is not divided for MCO
value: 1
enum/PLLMUL: enum/PLLMUL:
bit_size: 4 bit_size: 4
variants: variants:
@ -922,18 +931,6 @@ enum/PLLMUL:
- name: Mul16 - name: Mul16
description: PLL input clock x16 description: PLL input clock x16
value: 14 value: 14
- name: Mul16x
description: PLL input clock x16
value: 15
enum/PLLNODIV:
bit_size: 1
variants:
- name: Div2
description: PLL is divided by 2 for MCO
value: 0
- name: Div1
description: PLL is not divided for MCO
value: 1
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

3
data/registers/rcc_f1.yaml
View File

@ -762,9 +762,6 @@ enum/PLLMUL:
- name: Mul16 - name: Mul16
description: PLL input clock x16 description: PLL input clock x16
value: 14 value: 14
- name: Mul16x
description: PLL input clock x16
value: 15
enum/PLLSRC: enum/PLLSRC:
bit_size: 1 bit_size: 1
variants: variants:

3
data/registers/rcc_f100.yaml
View File

@ -733,9 +733,6 @@ enum/PLLMUL:
- name: Mul16 - name: Mul16
description: PLL input clock x16 description: PLL input clock x16
value: 14 value: 14
- name: Mul16x
description: PLL input clock x16
value: 15
enum/PLLSRC: enum/PLLSRC:
bit_size: 1 bit_size: 1
variants: variants:

646
data/registers/rcc_f2.yaml
View File

@ -1123,10 +1123,12 @@ fieldset/PLLCFGR:
description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL (PLL) multiplication factor for VCO description: Main PLL (PLL) multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
enum: PLLN
- name: PLLP - name: PLLP
description: Main PLL (PLL) division factor for main system clock description: Main PLL (PLL) division factor for main system clock
bit_offset: 16 bit_offset: 16
@ -1141,6 +1143,7 @@ fieldset/PLLCFGR:
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
enum: PLLQ
fieldset/PLLI2SCFGR: fieldset/PLLI2SCFGR:
description: PLLI2S configuration register description: PLLI2S configuration register
fields: fields:
@ -1259,6 +1262,618 @@ enum/MCOPRE:
- name: Div5 - name: Div5
description: Division by 5 description: Division by 5
value: 7 value: 7
enum/PLLM:
bit_size: 6
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
- name: Div32
value: 32
- name: Div33
value: 33
- name: Div34
value: 34
- name: Div35
value: 35
- name: Div36
value: 36
- name: Div37
value: 37
- name: Div38
value: 38
- name: Div39
value: 39
- name: Div40
value: 40
- name: Div41
value: 41
- name: Div42
value: 42
- name: Div43
value: 43
- name: Div44
value: 44
- name: Div45
value: 45
- name: Div46
value: 46
- name: Div47
value: 47
- name: Div48
value: 48
- name: Div49
value: 49
- name: Div50
value: 50
- name: Div51
value: 51
- name: Div52
value: 52
- name: Div53
value: 53
- name: Div54
value: 54
- name: Div55
value: 55
- name: Div56
value: 56
- name: Div57
value: 57
- name: Div58
value: 58
- name: Div59
value: 59
- name: Div60
value: 60
- name: Div61
value: 61
- name: Div62
value: 62
- name: Div63
value: 63
enum/PLLN:
bit_size: 9
variants:
- name: Mul192
value: 192
- name: Mul193
value: 193
- name: Mul194
value: 194
- name: Mul195
value: 195
- name: Mul196
value: 196
- name: Mul197
value: 197
- name: Mul198
value: 198
- name: Mul199
value: 199
- name: Mul200
value: 200
- name: Mul201
value: 201
- name: Mul202
value: 202
- name: Mul203
value: 203
- name: Mul204
value: 204
- name: Mul205
value: 205
- name: Mul206
value: 206
- name: Mul207
value: 207
- name: Mul208
value: 208
- name: Mul209
value: 209
- name: Mul210
value: 210
- name: Mul211
value: 211
- name: Mul212
value: 212
- name: Mul213
value: 213
- name: Mul214
value: 214
- name: Mul215
value: 215
- name: Mul216
value: 216
- name: Mul217
value: 217
- name: Mul218
value: 218
- name: Mul219
value: 219
- name: Mul220
value: 220
- name: Mul221
value: 221
- name: Mul222
value: 222
- name: Mul223
value: 223
- name: Mul224
value: 224
- name: Mul225
value: 225
- name: Mul226
value: 226
- name: Mul227
value: 227
- name: Mul228
value: 228
- name: Mul229
value: 229
- name: Mul230
value: 230
- name: Mul231
value: 231
- name: Mul232
value: 232
- name: Mul233
value: 233
- name: Mul234
value: 234
- name: Mul235
value: 235
- name: Mul236
value: 236
- name: Mul237
value: 237
- name: Mul238
value: 238
- name: Mul239
value: 239
- name: Mul240
value: 240
- name: Mul241
value: 241
- name: Mul242
value: 242
- name: Mul243
value: 243
- name: Mul244
value: 244
- name: Mul245
value: 245
- name: Mul246
value: 246
- name: Mul247
value: 247
- name: Mul248
value: 248
- name: Mul249
value: 249
- name: Mul250
value: 250
- name: Mul251
value: 251
- name: Mul252
value: 252
- name: Mul253
value: 253
- name: Mul254
value: 254
- name: Mul255
value: 255
- name: Mul256
value: 256
- name: Mul257
value: 257
- name: Mul258
value: 258
- name: Mul259
value: 259
- name: Mul260
value: 260
- name: Mul261
value: 261
- name: Mul262
value: 262
- name: Mul263
value: 263
- name: Mul264
value: 264
- name: Mul265
value: 265
- name: Mul266
value: 266
- name: Mul267
value: 267
- name: Mul268
value: 268
- name: Mul269
value: 269
- name: Mul270
value: 270
- name: Mul271
value: 271
- name: Mul272
value: 272
- name: Mul273
value: 273
- name: Mul274
value: 274
- name: Mul275
value: 275
- name: Mul276
value: 276
- name: Mul277
value: 277
- name: Mul278
value: 278
- name: Mul279
value: 279
- name: Mul280
value: 280
- name: Mul281
value: 281
- name: Mul282
value: 282
- name: Mul283
value: 283
- name: Mul284
value: 284
- name: Mul285
value: 285
- name: Mul286
value: 286
- name: Mul287
value: 287
- name: Mul288
value: 288
- name: Mul289
value: 289
- name: Mul290
value: 290
- name: Mul291
value: 291
- name: Mul292
value: 292
- name: Mul293
value: 293
- name: Mul294
value: 294
- name: Mul295
value: 295
- name: Mul296
value: 296
- name: Mul297
value: 297
- name: Mul298
value: 298
- name: Mul299
value: 299
- name: Mul300
value: 300
- name: Mul301
value: 301
- name: Mul302
value: 302
- name: Mul303
value: 303
- name: Mul304
value: 304
- name: Mul305
value: 305
- name: Mul306
value: 306
- name: Mul307
value: 307
- name: Mul308
value: 308
- name: Mul309
value: 309
- name: Mul310
value: 310
- name: Mul311
value: 311
- name: Mul312
value: 312
- name: Mul313
value: 313
- name: Mul314
value: 314
- name: Mul315
value: 315
- name: Mul316
value: 316
- name: Mul317
value: 317
- name: Mul318
value: 318
- name: Mul319
value: 319
- name: Mul320
value: 320
- name: Mul321
value: 321
- name: Mul322
value: 322
- name: Mul323
value: 323
- name: Mul324
value: 324
- name: Mul325
value: 325
- name: Mul326
value: 326
- name: Mul327
value: 327
- name: Mul328
value: 328
- name: Mul329
value: 329
- name: Mul330
value: 330
- name: Mul331
value: 331
- name: Mul332
value: 332
- name: Mul333
value: 333
- name: Mul334
value: 334
- name: Mul335
value: 335
- name: Mul336
value: 336
- name: Mul337
value: 337
- name: Mul338
value: 338
- name: Mul339
value: 339
- name: Mul340
value: 340
- name: Mul341
value: 341
- name: Mul342
value: 342
- name: Mul343
value: 343
- name: Mul344
value: 344
- name: Mul345
value: 345
- name: Mul346
value: 346
- name: Mul347
value: 347
- name: Mul348
value: 348
- name: Mul349
value: 349
- name: Mul350
value: 350
- name: Mul351
value: 351
- name: Mul352
value: 352
- name: Mul353
value: 353
- name: Mul354
value: 354
- name: Mul355
value: 355
- name: Mul356
value: 356
- name: Mul357
value: 357
- name: Mul358
value: 358
- name: Mul359
value: 359
- name: Mul360
value: 360
- name: Mul361
value: 361
- name: Mul362
value: 362
- name: Mul363
value: 363
- name: Mul364
value: 364
- name: Mul365
value: 365
- name: Mul366
value: 366
- name: Mul367
value: 367
- name: Mul368
value: 368
- name: Mul369
value: 369
- name: Mul370
value: 370
- name: Mul371
value: 371
- name: Mul372
value: 372
- name: Mul373
value: 373
- name: Mul374
value: 374
- name: Mul375
value: 375
- name: Mul376
value: 376
- name: Mul377
value: 377
- name: Mul378
value: 378
- name: Mul379
value: 379
- name: Mul380
value: 380
- name: Mul381
value: 381
- name: Mul382
value: 382
- name: Mul383
value: 383
- name: Mul384
value: 384
- name: Mul385
value: 385
- name: Mul386
value: 386
- name: Mul387
value: 387
- name: Mul388
value: 388
- name: Mul389
value: 389
- name: Mul390
value: 390
- name: Mul391
value: 391
- name: Mul392
value: 392
- name: Mul393
value: 393
- name: Mul394
value: 394
- name: Mul395
value: 395
- name: Mul396
value: 396
- name: Mul397
value: 397
- name: Mul398
value: 398
- name: Mul399
value: 399
- name: Mul400
value: 400
- name: Mul401
value: 401
- name: Mul402
value: 402
- name: Mul403
value: 403
- name: Mul404
value: 404
- name: Mul405
value: 405
- name: Mul406
value: 406
- name: Mul407
value: 407
- name: Mul408
value: 408
- name: Mul409
value: 409
- name: Mul410
value: 410
- name: Mul411
value: 411
- name: Mul412
value: 412
- name: Mul413
value: 413
- name: Mul414
value: 414
- name: Mul415
value: 415
- name: Mul416
value: 416
- name: Mul417
value: 417
- name: Mul418
value: 418
- name: Mul419
value: 419
- name: Mul420
value: 420
- name: Mul421
value: 421
- name: Mul422
value: 422
- name: Mul423
value: 423
- name: Mul424
value: 424
- name: Mul425
value: 425
- name: Mul426
value: 426
- name: Mul427
value: 427
- name: Mul428
value: 428
- name: Mul429
value: 429
- name: Mul430
value: 430
- name: Mul431
value: 431
- name: Mul432
value: 432
enum/PLLP: enum/PLLP:
bit_size: 2 bit_size: 2
variants: variants:
@ -1274,6 +1889,37 @@ enum/PLLP:
- name: Div8 - name: Div8
description: PLLP=8 description: PLLP=8
value: 3 value: 3
enum/PLLQ:
bit_size: 4
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
enum/PLLSRC: enum/PLLSRC:
bit_size: 1 bit_size: 1
variants: variants:

27
data/registers/rcc_f3.yaml
View File

@ -557,11 +557,11 @@ fieldset/CFGR:
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: MCOPRE enum: MCOPRE
- name: PLLNODIV - name: PLLMCODIV
description: Do not divide PLL to MCO description: Do not divide PLL to MCO
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
enum: PLLNODIV enum: PLLMCODIV
fieldset/CFGR2: fieldset/CFGR2:
description: Clock configuration register 2 description: Clock configuration register 2
fields: fields:
@ -1017,8 +1017,17 @@ enum/MCOSEL:
description: External 4-32 MHz (HSE) oscillator clock selected description: External 4-32 MHz (HSE) oscillator clock selected
value: 6 value: 6
- name: PLL - name: PLL
description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) description: PLL clock selected (divided by 1 or 2, depending en PLLMCODIV)
value: 7 value: 7
enum/PLLMCODIV:
bit_size: 1
variants:
- name: Div2
description: PLL is divided by 2 for MCO
value: 0
- name: Div1
description: PLL is not divided for MCO
value: 1
enum/PLLMUL: enum/PLLMUL:
bit_size: 4 bit_size: 4
variants: variants:
@ -1067,18 +1076,6 @@ enum/PLLMUL:
- name: Mul16 - name: Mul16
description: PLL input clock x16 description: PLL input clock x16
value: 14 value: 14
- name: Mul16x
description: PLL input clock x16
value: 15
enum/PLLNODIV:
bit_size: 1
variants:
- name: Div2
description: PLL is divided by 2 for MCO
value: 0
- name: Div1
description: PLL is not divided for MCO
value: 1
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

27
data/registers/rcc_f3_v2.yaml
View File

@ -533,11 +533,11 @@ fieldset/CFGR:
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: MCOPRE enum: MCOPRE
- name: PLLNODIV - name: PLLMCODIV
description: Do not divide PLL to MCO description: Do not divide PLL to MCO
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
enum: PLLNODIV enum: PLLMCODIV
fieldset/CFGR2: fieldset/CFGR2:
description: Clock configuration register 2 description: Clock configuration register 2
fields: fields:
@ -993,8 +993,17 @@ enum/MCOSEL:
description: External 4-32 MHz (HSE) oscillator clock selected description: External 4-32 MHz (HSE) oscillator clock selected
value: 6 value: 6
- name: PLL - name: PLL
description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) description: PLL clock selected (divided by 1 or 2, depending en PLLMCODIV)
value: 7 value: 7
enum/PLLMCODIV:
bit_size: 1
variants:
- name: Div2
description: PLL is divided by 2 for MCO
value: 0
- name: Div1
description: PLL is not divided for MCO
value: 1
enum/PLLMUL: enum/PLLMUL:
bit_size: 4 bit_size: 4
variants: variants:
@ -1043,18 +1052,6 @@ enum/PLLMUL:
- name: Mul16 - name: Mul16
description: PLL input clock x16 description: PLL input clock x16
value: 14 value: 14
- name: Mul16x
description: PLL input clock x16
value: 15
enum/PLLNODIV:
bit_size: 1
variants:
- name: Div2
description: PLL is divided by 2 for MCO
value: 0
- name: Div1
description: PLL is not divided for MCO
value: 1
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

962
data/registers/rcc_f4.yaml
View File

File diff suppressed because it is too large Load Diff

946
data/registers/rcc_f410.yaml
View File

@ -746,10 +746,12 @@ fieldset/PLLCFGR:
description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL (PLL) multiplication factor for VCO description: Main PLL (PLL) multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
enum: PLLN
- name: PLLP - name: PLLP
description: Main PLL (PLL) division factor for main system clock description: Main PLL (PLL) division factor for main system clock
bit_offset: 16 bit_offset: 16
@ -764,10 +766,12 @@ fieldset/PLLCFGR:
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
enum: PLLQ
- name: PLLR - name: PLLR
description: PLL division factor for I2S and System clocks description: PLL division factor for I2S and System clocks
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: PLLR
fieldset/SSCGR: fieldset/SSCGR:
description: spread spectrum clock generation register description: spread spectrum clock generation register
fields: fields:
@ -905,6 +909,902 @@ enum/MCOPRE:
- name: Div5 - name: Div5
description: Division by 5 description: Division by 5
value: 7 value: 7
enum/PLLM:
bit_size: 6
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
- name: Div32
value: 32
- name: Div33
value: 33
- name: Div34
value: 34
- name: Div35
value: 35
- name: Div36
value: 36
- name: Div37
value: 37
- name: Div38
value: 38
- name: Div39
value: 39
- name: Div40
value: 40
- name: Div41
value: 41
- name: Div42
value: 42
- name: Div43
value: 43
- name: Div44
value: 44
- name: Div45
value: 45
- name: Div46
value: 46
- name: Div47
value: 47
- name: Div48
value: 48
- name: Div49
value: 49
- name: Div50
value: 50
- name: Div51
value: 51
- name: Div52
value: 52
- name: Div53
value: 53
- name: Div54
value: 54
- name: Div55
value: 55
- name: Div56
value: 56
- name: Div57
value: 57
- name: Div58
value: 58
- name: Div59
value: 59
- name: Div60
value: 60
- name: Div61
value: 61
- name: Div62
value: 62
- name: Div63
value: 63
enum/PLLN:
bit_size: 9
variants:
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
- name: Mul87
value: 87
- name: Mul88
value: 88
- name: Mul89
value: 89
- name: Mul90
value: 90
- name: Mul91
value: 91
- name: Mul92
value: 92
- name: Mul93
value: 93
- name: Mul94
value: 94
- name: Mul95
value: 95
- name: Mul96
value: 96
- name: Mul97
value: 97
- name: Mul98
value: 98
- name: Mul99
value: 99
- name: Mul100
value: 100
- name: Mul101
value: 101
- name: Mul102
value: 102
- name: Mul103
value: 103
- name: Mul104
value: 104
- name: Mul105
value: 105
- name: Mul106
value: 106
- name: Mul107
value: 107
- name: Mul108
value: 108
- name: Mul109
value: 109
- name: Mul110
value: 110
- name: Mul111
value: 111
- name: Mul112
value: 112
- name: Mul113
value: 113
- name: Mul114
value: 114
- name: Mul115
value: 115
- name: Mul116
value: 116
- name: Mul117
value: 117
- name: Mul118
value: 118
- name: Mul119
value: 119
- name: Mul120
value: 120
- name: Mul121
value: 121
- name: Mul122
value: 122
- name: Mul123
value: 123
- name: Mul124
value: 124
- name: Mul125
value: 125
- name: Mul126
value: 126
- name: Mul127
value: 127
- name: Mul128
value: 128
- name: Mul129
value: 129
- name: Mul130
value: 130
- name: Mul131
value: 131
- name: Mul132
value: 132
- name: Mul133
value: 133
- name: Mul134
value: 134
- name: Mul135
value: 135
- name: Mul136
value: 136
- name: Mul137
value: 137
- name: Mul138
value: 138
- name: Mul139
value: 139
- name: Mul140
value: 140
- name: Mul141
value: 141
- name: Mul142
value: 142
- name: Mul143
value: 143
- name: Mul144
value: 144
- name: Mul145
value: 145
- name: Mul146
value: 146
- name: Mul147
value: 147
- name: Mul148
value: 148
- name: Mul149
value: 149
- name: Mul150
value: 150
- name: Mul151
value: 151
- name: Mul152
value: 152
- name: Mul153
value: 153
- name: Mul154
value: 154
- name: Mul155
value: 155
- name: Mul156
value: 156
- name: Mul157
value: 157
- name: Mul158
value: 158
- name: Mul159
value: 159
- name: Mul160
value: 160
- name: Mul161
value: 161
- name: Mul162
value: 162
- name: Mul163
value: 163
- name: Mul164
value: 164
- name: Mul165
value: 165
- name: Mul166
value: 166
- name: Mul167
value: 167
- name: Mul168
value: 168
- name: Mul169
value: 169
- name: Mul170
value: 170
- name: Mul171
value: 171
- name: Mul172
value: 172
- name: Mul173
value: 173
- name: Mul174
value: 174
- name: Mul175
value: 175
- name: Mul176
value: 176
- name: Mul177
value: 177
- name: Mul178
value: 178
- name: Mul179
value: 179
- name: Mul180
value: 180
- name: Mul181
value: 181
- name: Mul182
value: 182
- name: Mul183
value: 183
- name: Mul184
value: 184
- name: Mul185
value: 185
- name: Mul186
value: 186
- name: Mul187
value: 187
- name: Mul188
value: 188
- name: Mul189
value: 189
- name: Mul190
value: 190
- name: Mul191
value: 191
- name: Mul192
value: 192
- name: Mul193
value: 193
- name: Mul194
value: 194
- name: Mul195
value: 195
- name: Mul196
value: 196
- name: Mul197
value: 197
- name: Mul198
value: 198
- name: Mul199
value: 199
- name: Mul200
value: 200
- name: Mul201
value: 201
- name: Mul202
value: 202
- name: Mul203
value: 203
- name: Mul204
value: 204
- name: Mul205
value: 205
- name: Mul206
value: 206
- name: Mul207
value: 207
- name: Mul208
value: 208
- name: Mul209
value: 209
- name: Mul210
value: 210
- name: Mul211
value: 211
- name: Mul212
value: 212
- name: Mul213
value: 213
- name: Mul214
value: 214
- name: Mul215
value: 215
- name: Mul216
value: 216
- name: Mul217
value: 217
- name: Mul218
value: 218
- name: Mul219
value: 219
- name: Mul220
value: 220
- name: Mul221
value: 221
- name: Mul222
value: 222
- name: Mul223
value: 223
- name: Mul224
value: 224
- name: Mul225
value: 225
- name: Mul226
value: 226
- name: Mul227
value: 227
- name: Mul228
value: 228
- name: Mul229
value: 229
- name: Mul230
value: 230
- name: Mul231
value: 231
- name: Mul232
value: 232
- name: Mul233
value: 233
- name: Mul234
value: 234
- name: Mul235
value: 235
- name: Mul236
value: 236
- name: Mul237
value: 237
- name: Mul238
value: 238
- name: Mul239
value: 239
- name: Mul240
value: 240
- name: Mul241
value: 241
- name: Mul242
value: 242
- name: Mul243
value: 243
- name: Mul244
value: 244
- name: Mul245
value: 245
- name: Mul246
value: 246
- name: Mul247
value: 247
- name: Mul248
value: 248
- name: Mul249
value: 249
- name: Mul250
value: 250
- name: Mul251
value: 251
- name: Mul252
value: 252
- name: Mul253
value: 253
- name: Mul254
value: 254
- name: Mul255
value: 255
- name: Mul256
value: 256
- name: Mul257
value: 257
- name: Mul258
value: 258
- name: Mul259
value: 259
- name: Mul260
value: 260
- name: Mul261
value: 261
- name: Mul262
value: 262
- name: Mul263
value: 263
- name: Mul264
value: 264
- name: Mul265
value: 265
- name: Mul266
value: 266
- name: Mul267
value: 267
- name: Mul268
value: 268
- name: Mul269
value: 269
- name: Mul270
value: 270
- name: Mul271
value: 271
- name: Mul272
value: 272
- name: Mul273
value: 273
- name: Mul274
value: 274
- name: Mul275
value: 275
- name: Mul276
value: 276
- name: Mul277
value: 277
- name: Mul278
value: 278
- name: Mul279
value: 279
- name: Mul280
value: 280
- name: Mul281
value: 281
- name: Mul282
value: 282
- name: Mul283
value: 283
- name: Mul284
value: 284
- name: Mul285
value: 285
- name: Mul286
value: 286
- name: Mul287
value: 287
- name: Mul288
value: 288
- name: Mul289
value: 289
- name: Mul290
value: 290
- name: Mul291
value: 291
- name: Mul292
value: 292
- name: Mul293
value: 293
- name: Mul294
value: 294
- name: Mul295
value: 295
- name: Mul296
value: 296
- name: Mul297
value: 297
- name: Mul298
value: 298
- name: Mul299
value: 299
- name: Mul300
value: 300
- name: Mul301
value: 301
- name: Mul302
value: 302
- name: Mul303
value: 303
- name: Mul304
value: 304
- name: Mul305
value: 305
- name: Mul306
value: 306
- name: Mul307
value: 307
- name: Mul308
value: 308
- name: Mul309
value: 309
- name: Mul310
value: 310
- name: Mul311
value: 311
- name: Mul312
value: 312
- name: Mul313
value: 313
- name: Mul314
value: 314
- name: Mul315
value: 315
- name: Mul316
value: 316
- name: Mul317
value: 317
- name: Mul318
value: 318
- name: Mul319
value: 319
- name: Mul320
value: 320
- name: Mul321
value: 321
- name: Mul322
value: 322
- name: Mul323
value: 323
- name: Mul324
value: 324
- name: Mul325
value: 325
- name: Mul326
value: 326
- name: Mul327
value: 327
- name: Mul328
value: 328
- name: Mul329
value: 329
- name: Mul330
value: 330
- name: Mul331
value: 331
- name: Mul332
value: 332
- name: Mul333
value: 333
- name: Mul334
value: 334
- name: Mul335
value: 335
- name: Mul336
value: 336
- name: Mul337
value: 337
- name: Mul338
value: 338
- name: Mul339
value: 339
- name: Mul340
value: 340
- name: Mul341
value: 341
- name: Mul342
value: 342
- name: Mul343
value: 343
- name: Mul344
value: 344
- name: Mul345
value: 345
- name: Mul346
value: 346
- name: Mul347
value: 347
- name: Mul348
value: 348
- name: Mul349
value: 349
- name: Mul350
value: 350
- name: Mul351
value: 351
- name: Mul352
value: 352
- name: Mul353
value: 353
- name: Mul354
value: 354
- name: Mul355
value: 355
- name: Mul356
value: 356
- name: Mul357
value: 357
- name: Mul358
value: 358
- name: Mul359
value: 359
- name: Mul360
value: 360
- name: Mul361
value: 361
- name: Mul362
value: 362
- name: Mul363
value: 363
- name: Mul364
value: 364
- name: Mul365
value: 365
- name: Mul366
value: 366
- name: Mul367
value: 367
- name: Mul368
value: 368
- name: Mul369
value: 369
- name: Mul370
value: 370
- name: Mul371
value: 371
- name: Mul372
value: 372
- name: Mul373
value: 373
- name: Mul374
value: 374
- name: Mul375
value: 375
- name: Mul376
value: 376
- name: Mul377
value: 377
- name: Mul378
value: 378
- name: Mul379
value: 379
- name: Mul380
value: 380
- name: Mul381
value: 381
- name: Mul382
value: 382
- name: Mul383
value: 383
- name: Mul384
value: 384
- name: Mul385
value: 385
- name: Mul386
value: 386
- name: Mul387
value: 387
- name: Mul388
value: 388
- name: Mul389
value: 389
- name: Mul390
value: 390
- name: Mul391
value: 391
- name: Mul392
value: 392
- name: Mul393
value: 393
- name: Mul394
value: 394
- name: Mul395
value: 395
- name: Mul396
value: 396
- name: Mul397
value: 397
- name: Mul398
value: 398
- name: Mul399
value: 399
- name: Mul400
value: 400
- name: Mul401
value: 401
- name: Mul402
value: 402
- name: Mul403
value: 403
- name: Mul404
value: 404
- name: Mul405
value: 405
- name: Mul406
value: 406
- name: Mul407
value: 407
- name: Mul408
value: 408
- name: Mul409
value: 409
- name: Mul410
value: 410
- name: Mul411
value: 411
- name: Mul412
value: 412
- name: Mul413
value: 413
- name: Mul414
value: 414
- name: Mul415
value: 415
- name: Mul416
value: 416
- name: Mul417
value: 417
- name: Mul418
value: 418
- name: Mul419
value: 419
- name: Mul420
value: 420
- name: Mul421
value: 421
- name: Mul422
value: 422
- name: Mul423
value: 423
- name: Mul424
value: 424
- name: Mul425
value: 425
- name: Mul426
value: 426
- name: Mul427
value: 427
- name: Mul428
value: 428
- name: Mul429
value: 429
- name: Mul430
value: 430
- name: Mul431
value: 431
- name: Mul432
value: 432
enum/PLLP: enum/PLLP:
bit_size: 2 bit_size: 2
variants: variants:
@ -920,6 +1820,52 @@ enum/PLLP:
- name: Div8 - name: Div8
description: PLLP=8 description: PLLP=8
value: 3 value: 3
enum/PLLQ:
bit_size: 4
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
enum/PLLR:
bit_size: 3
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
enum/PLLSRC: enum/PLLSRC:
bit_size: 1 bit_size: 1
variants: variants:

946
data/registers/rcc_f7.yaml
View File

@ -1600,10 +1600,12 @@ fieldset/PLLCFGR:
description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL (PLL) multiplication factor for VCO description: Main PLL (PLL) multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
enum: PLLN
- name: PLLP - name: PLLP
description: Main PLL (PLL) division factor for main system clock description: Main PLL (PLL) division factor for main system clock
bit_offset: 16 bit_offset: 16
@ -1618,10 +1620,12 @@ fieldset/PLLCFGR:
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
enum: PLLQ
- name: PLLR - name: PLLR
description: PLL division factor for DSI clock description: PLL division factor for DSI clock
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: PLLR
fieldset/PLLI2SCFGR: fieldset/PLLI2SCFGR:
description: PLLI2S configuration register description: PLLI2S configuration register
fields: fields:
@ -1970,6 +1974,902 @@ enum/PLLISP:
- name: Div8 - name: Div8
description: PLL*P=8 description: PLL*P=8
value: 3 value: 3
enum/PLLM:
bit_size: 6
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
- name: Div32
value: 32
- name: Div33
value: 33
- name: Div34
value: 34
- name: Div35
value: 35
- name: Div36
value: 36
- name: Div37
value: 37
- name: Div38
value: 38
- name: Div39
value: 39
- name: Div40
value: 40
- name: Div41
value: 41
- name: Div42
value: 42
- name: Div43
value: 43
- name: Div44
value: 44
- name: Div45
value: 45
- name: Div46
value: 46
- name: Div47
value: 47
- name: Div48
value: 48
- name: Div49
value: 49
- name: Div50
value: 50
- name: Div51
value: 51
- name: Div52
value: 52
- name: Div53
value: 53
- name: Div54
value: 54
- name: Div55
value: 55
- name: Div56
value: 56
- name: Div57
value: 57
- name: Div58
value: 58
- name: Div59
value: 59
- name: Div60
value: 60
- name: Div61
value: 61
- name: Div62
value: 62
- name: Div63
value: 63
enum/PLLN:
bit_size: 9
variants:
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
- name: Mul87
value: 87
- name: Mul88
value: 88
- name: Mul89
value: 89
- name: Mul90
value: 90
- name: Mul91
value: 91
- name: Mul92
value: 92
- name: Mul93
value: 93
- name: Mul94
value: 94
- name: Mul95
value: 95
- name: Mul96
value: 96
- name: Mul97
value: 97
- name: Mul98
value: 98
- name: Mul99
value: 99
- name: Mul100
value: 100
- name: Mul101
value: 101
- name: Mul102
value: 102
- name: Mul103
value: 103
- name: Mul104
value: 104
- name: Mul105
value: 105
- name: Mul106
value: 106
- name: Mul107
value: 107
- name: Mul108
value: 108
- name: Mul109
value: 109
- name: Mul110
value: 110
- name: Mul111
value: 111
- name: Mul112
value: 112
- name: Mul113
value: 113
- name: Mul114
value: 114
- name: Mul115
value: 115
- name: Mul116
value: 116
- name: Mul117
value: 117
- name: Mul118
value: 118
- name: Mul119
value: 119
- name: Mul120
value: 120
- name: Mul121
value: 121
- name: Mul122
value: 122
- name: Mul123
value: 123
- name: Mul124
value: 124
- name: Mul125
value: 125
- name: Mul126
value: 126
- name: Mul127
value: 127
- name: Mul128
value: 128
- name: Mul129
value: 129
- name: Mul130
value: 130
- name: Mul131
value: 131
- name: Mul132
value: 132
- name: Mul133
value: 133
- name: Mul134
value: 134
- name: Mul135
value: 135
- name: Mul136
value: 136
- name: Mul137
value: 137
- name: Mul138
value: 138
- name: Mul139
value: 139
- name: Mul140
value: 140
- name: Mul141
value: 141
- name: Mul142
value: 142
- name: Mul143
value: 143
- name: Mul144
value: 144
- name: Mul145
value: 145
- name: Mul146
value: 146
- name: Mul147
value: 147
- name: Mul148
value: 148
- name: Mul149
value: 149
- name: Mul150
value: 150
- name: Mul151
value: 151
- name: Mul152
value: 152
- name: Mul153
value: 153
- name: Mul154
value: 154
- name: Mul155
value: 155
- name: Mul156
value: 156
- name: Mul157
value: 157
- name: Mul158
value: 158
- name: Mul159
value: 159
- name: Mul160
value: 160
- name: Mul161
value: 161
- name: Mul162
value: 162
- name: Mul163
value: 163
- name: Mul164
value: 164
- name: Mul165
value: 165
- name: Mul166
value: 166
- name: Mul167
value: 167
- name: Mul168
value: 168
- name: Mul169
value: 169
- name: Mul170
value: 170
- name: Mul171
value: 171
- name: Mul172
value: 172
- name: Mul173
value: 173
- name: Mul174
value: 174
- name: Mul175
value: 175
- name: Mul176
value: 176
- name: Mul177
value: 177
- name: Mul178
value: 178
- name: Mul179
value: 179
- name: Mul180
value: 180
- name: Mul181
value: 181
- name: Mul182
value: 182
- name: Mul183
value: 183
- name: Mul184
value: 184
- name: Mul185
value: 185
- name: Mul186
value: 186
- name: Mul187
value: 187
- name: Mul188
value: 188
- name: Mul189
value: 189
- name: Mul190
value: 190
- name: Mul191
value: 191
- name: Mul192
value: 192
- name: Mul193
value: 193
- name: Mul194
value: 194
- name: Mul195
value: 195
- name: Mul196
value: 196
- name: Mul197
value: 197
- name: Mul198
value: 198
- name: Mul199
value: 199
- name: Mul200
value: 200
- name: Mul201
value: 201
- name: Mul202
value: 202
- name: Mul203
value: 203
- name: Mul204
value: 204
- name: Mul205
value: 205
- name: Mul206
value: 206
- name: Mul207
value: 207
- name: Mul208
value: 208
- name: Mul209
value: 209
- name: Mul210
value: 210
- name: Mul211
value: 211
- name: Mul212
value: 212
- name: Mul213
value: 213
- name: Mul214
value: 214
- name: Mul215
value: 215
- name: Mul216
value: 216
- name: Mul217
value: 217
- name: Mul218
value: 218
- name: Mul219
value: 219
- name: Mul220
value: 220
- name: Mul221
value: 221
- name: Mul222
value: 222
- name: Mul223
value: 223
- name: Mul224
value: 224
- name: Mul225
value: 225
- name: Mul226
value: 226
- name: Mul227
value: 227
- name: Mul228
value: 228
- name: Mul229
value: 229
- name: Mul230
value: 230
- name: Mul231
value: 231
- name: Mul232
value: 232
- name: Mul233
value: 233
- name: Mul234
value: 234
- name: Mul235
value: 235
- name: Mul236
value: 236
- name: Mul237
value: 237
- name: Mul238
value: 238
- name: Mul239
value: 239
- name: Mul240
value: 240
- name: Mul241
value: 241
- name: Mul242
value: 242
- name: Mul243
value: 243
- name: Mul244
value: 244
- name: Mul245
value: 245
- name: Mul246
value: 246
- name: Mul247
value: 247
- name: Mul248
value: 248
- name: Mul249
value: 249
- name: Mul250
value: 250
- name: Mul251
value: 251
- name: Mul252
value: 252
- name: Mul253
value: 253
- name: Mul254
value: 254
- name: Mul255
value: 255
- name: Mul256
value: 256
- name: Mul257
value: 257
- name: Mul258
value: 258
- name: Mul259
value: 259
- name: Mul260
value: 260
- name: Mul261
value: 261
- name: Mul262
value: 262
- name: Mul263
value: 263
- name: Mul264
value: 264
- name: Mul265
value: 265
- name: Mul266
value: 266
- name: Mul267
value: 267
- name: Mul268
value: 268
- name: Mul269
value: 269
- name: Mul270
value: 270
- name: Mul271
value: 271
- name: Mul272
value: 272
- name: Mul273
value: 273
- name: Mul274
value: 274
- name: Mul275
value: 275
- name: Mul276
value: 276
- name: Mul277
value: 277
- name: Mul278
value: 278
- name: Mul279
value: 279
- name: Mul280
value: 280
- name: Mul281
value: 281
- name: Mul282
value: 282
- name: Mul283
value: 283
- name: Mul284
value: 284
- name: Mul285
value: 285
- name: Mul286
value: 286
- name: Mul287
value: 287
- name: Mul288
value: 288
- name: Mul289
value: 289
- name: Mul290
value: 290
- name: Mul291
value: 291
- name: Mul292
value: 292
- name: Mul293
value: 293
- name: Mul294
value: 294
- name: Mul295
value: 295
- name: Mul296
value: 296
- name: Mul297
value: 297
- name: Mul298
value: 298
- name: Mul299
value: 299
- name: Mul300
value: 300
- name: Mul301
value: 301
- name: Mul302
value: 302
- name: Mul303
value: 303
- name: Mul304
value: 304
- name: Mul305
value: 305
- name: Mul306
value: 306
- name: Mul307
value: 307
- name: Mul308
value: 308
- name: Mul309
value: 309
- name: Mul310
value: 310
- name: Mul311
value: 311
- name: Mul312
value: 312
- name: Mul313
value: 313
- name: Mul314
value: 314
- name: Mul315
value: 315
- name: Mul316
value: 316
- name: Mul317
value: 317
- name: Mul318
value: 318
- name: Mul319
value: 319
- name: Mul320
value: 320
- name: Mul321
value: 321
- name: Mul322
value: 322
- name: Mul323
value: 323
- name: Mul324
value: 324
- name: Mul325
value: 325
- name: Mul326
value: 326
- name: Mul327
value: 327
- name: Mul328
value: 328
- name: Mul329
value: 329
- name: Mul330
value: 330
- name: Mul331
value: 331
- name: Mul332
value: 332
- name: Mul333
value: 333
- name: Mul334
value: 334
- name: Mul335
value: 335
- name: Mul336
value: 336
- name: Mul337
value: 337
- name: Mul338
value: 338
- name: Mul339
value: 339
- name: Mul340
value: 340
- name: Mul341
value: 341
- name: Mul342
value: 342
- name: Mul343
value: 343
- name: Mul344
value: 344
- name: Mul345
value: 345
- name: Mul346
value: 346
- name: Mul347
value: 347
- name: Mul348
value: 348
- name: Mul349
value: 349
- name: Mul350
value: 350
- name: Mul351
value: 351
- name: Mul352
value: 352
- name: Mul353
value: 353
- name: Mul354
value: 354
- name: Mul355
value: 355
- name: Mul356
value: 356
- name: Mul357
value: 357
- name: Mul358
value: 358
- name: Mul359
value: 359
- name: Mul360
value: 360
- name: Mul361
value: 361
- name: Mul362
value: 362
- name: Mul363
value: 363
- name: Mul364
value: 364
- name: Mul365
value: 365
- name: Mul366
value: 366
- name: Mul367
value: 367
- name: Mul368
value: 368
- name: Mul369
value: 369
- name: Mul370
value: 370
- name: Mul371
value: 371
- name: Mul372
value: 372
- name: Mul373
value: 373
- name: Mul374
value: 374
- name: Mul375
value: 375
- name: Mul376
value: 376
- name: Mul377
value: 377
- name: Mul378
value: 378
- name: Mul379
value: 379
- name: Mul380
value: 380
- name: Mul381
value: 381
- name: Mul382
value: 382
- name: Mul383
value: 383
- name: Mul384
value: 384
- name: Mul385
value: 385
- name: Mul386
value: 386
- name: Mul387
value: 387
- name: Mul388
value: 388
- name: Mul389
value: 389
- name: Mul390
value: 390
- name: Mul391
value: 391
- name: Mul392
value: 392
- name: Mul393
value: 393
- name: Mul394
value: 394
- name: Mul395
value: 395
- name: Mul396
value: 396
- name: Mul397
value: 397
- name: Mul398
value: 398
- name: Mul399
value: 399
- name: Mul400
value: 400
- name: Mul401
value: 401
- name: Mul402
value: 402
- name: Mul403
value: 403
- name: Mul404
value: 404
- name: Mul405
value: 405
- name: Mul406
value: 406
- name: Mul407
value: 407
- name: Mul408
value: 408
- name: Mul409
value: 409
- name: Mul410
value: 410
- name: Mul411
value: 411
- name: Mul412
value: 412
- name: Mul413
value: 413
- name: Mul414
value: 414
- name: Mul415
value: 415
- name: Mul416
value: 416
- name: Mul417
value: 417
- name: Mul418
value: 418
- name: Mul419
value: 419
- name: Mul420
value: 420
- name: Mul421
value: 421
- name: Mul422
value: 422
- name: Mul423
value: 423
- name: Mul424
value: 424
- name: Mul425
value: 425
- name: Mul426
value: 426
- name: Mul427
value: 427
- name: Mul428
value: 428
- name: Mul429
value: 429
- name: Mul430
value: 430
- name: Mul431
value: 431
- name: Mul432
value: 432
enum/PLLP: enum/PLLP:
bit_size: 2 bit_size: 2
variants: variants:
@ -1985,6 +2885,52 @@ enum/PLLP:
- name: Div8 - name: Div8
description: PLLP=8 description: PLLP=8
value: 3 value: 3
enum/PLLQ:
bit_size: 4
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
enum/PLLR:
bit_size: 3
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
enum/PLLSAIDIVQ: enum/PLLSAIDIVQ:
bit_size: 5 bit_size: 5
variants: variants:

290
data/registers/rcc_g0.yaml
View File

@ -13,10 +13,10 @@ block/RCC:
description: Clock configuration register description: Clock configuration register
byte_offset: 8 byte_offset: 8
fieldset: CFGR fieldset: CFGR
- name: PLLSYSCFGR - name: PLLCFGR
description: PLL configuration register description: PLL configuration register
byte_offset: 12 byte_offset: 12
fieldset: PLLSYSCFGR fieldset: PLLCFGR
- name: CRRCR - name: CRRCR
description: RCC clock recovery RC register description: RCC clock recovery RC register
byte_offset: 20 byte_offset: 20
@ -1131,7 +1131,7 @@ fieldset/ICSCR:
description: HSI16 clock trimming description: HSI16 clock trimming
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
fieldset/PLLSYSCFGR: fieldset/PLLCFGR:
description: PLL configuration register description: PLL configuration register
fields: fields:
- name: PLLSRC - name: PLLSRC
@ -1143,10 +1143,12 @@ fieldset/PLLSYSCFGR:
description: Division factor M of the PLL input clock divider description: Division factor M of the PLL input clock divider
bit_offset: 4 bit_offset: 4
bit_size: 3 bit_size: 3
enum: PLLM
- name: PLLN - name: PLLN
description: PLL frequency multiplication factor N description: PLL frequency multiplication factor N
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
enum: PLLN
- name: PLLPEN - name: PLLPEN
description: PLLPCLK clock output enable description: PLLPCLK clock output enable
bit_offset: 16 bit_offset: 16
@ -1155,6 +1157,7 @@ fieldset/PLLSYSCFGR:
description: PLL VCO division factor P for PLLPCLK clock output description: PLL VCO division factor P for PLLPCLK clock output
bit_offset: 17 bit_offset: 17
bit_size: 5 bit_size: 5
enum: PLLP
- name: PLLQEN - name: PLLQEN
description: PLLQCLK clock output enable description: PLLQCLK clock output enable
bit_offset: 24 bit_offset: 24
@ -1163,6 +1166,7 @@ fieldset/PLLSYSCFGR:
description: PLL VCO division factor Q for PLLQCLK clock output description: PLL VCO division factor Q for PLLQCLK clock output
bit_offset: 25 bit_offset: 25
bit_size: 3 bit_size: 3
enum: PLLQ
- name: PLLREN - name: PLLREN
description: PLLRCLK clock output enable description: PLLRCLK clock output enable
bit_offset: 28 bit_offset: 28
@ -1171,6 +1175,7 @@ fieldset/PLLSYSCFGR:
description: PLL VCO division factor R for PLLRCLK clock output description: PLL VCO division factor R for PLLRCLK clock output
bit_offset: 29 bit_offset: 29
bit_size: 3 bit_size: 3
enum: PLLR
enum/ADCSEL: enum/ADCSEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -1468,6 +1473,285 @@ enum/MCOSEL:
- name: RTC_WKUP - name: RTC_WKUP
description: RTC_Wakeup selected as MCO source description: RTC_Wakeup selected as MCO source
value: 11 value: 11
enum/PLLM:
bit_size: 3
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
enum/PLLN:
bit_size: 7
variants:
- name: Mul8
value: 8
- name: Mul9
value: 9
- name: Mul10
value: 10
- name: Mul11
value: 11
- name: Mul12
value: 12
- name: Mul13
value: 13
- name: Mul14
value: 14
- name: Mul15
value: 15
- name: Mul16
value: 16
- name: Mul17
value: 17
- name: Mul18
value: 18
- name: Mul19
value: 19
- name: Mul20
value: 20
- name: Mul21
value: 21
- name: Mul22
value: 22
- name: Mul23
value: 23
- name: Mul24
value: 24
- name: Mul25
value: 25
- name: Mul26
value: 26
- name: Mul27
value: 27
- name: Mul28
value: 28
- name: Mul29
value: 29
- name: Mul30
value: 30
- name: Mul31
value: 31
- name: Mul32
value: 32
- name: Mul33
value: 33
- name: Mul34
value: 34
- name: Mul35
value: 35
- name: Mul36
value: 36
- name: Mul37
value: 37
- name: Mul38
value: 38
- name: Mul39
value: 39
- name: Mul40
value: 40
- name: Mul41
value: 41
- name: Mul42
value: 42
- name: Mul43
value: 43
- name: Mul44
value: 44
- name: Mul45
value: 45
- name: Mul46
value: 46
- name: Mul47
value: 47
- name: Mul48
value: 48
- name: Mul49
value: 49
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
enum/PLLP:
bit_size: 5
variants:
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
- name: Div17
value: 16
- name: Div18
value: 17
- name: Div19
value: 18
- name: Div20
value: 19
- name: Div21
value: 20
- name: Div22
value: 21
- name: Div23
value: 22
- name: Div24
value: 23
- name: Div25
value: 24
- name: Div26
value: 25
- name: Div27
value: 26
- name: Div28
value: 27
- name: Div29
value: 28
- name: Div30
value: 29
- name: Div31
value: 30
- name: Div32
value: 31
enum/PLLQ:
bit_size: 3
variants:
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
enum/PLLR:
bit_size: 3
variants:
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

380
data/registers/rcc_g4.yaml
View File

@ -1302,18 +1302,21 @@ fieldset/PLLCFGR:
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL multiplication factor for VCO description: Main PLL multiplication factor for VCO
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
enum: PLLN
- name: PLLPEN - name: PLLPEN
description: Main PLL PLLSAI3CLK output enable description: Main PLL PLLSAI3CLK output enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: PLLP - name: PLLPBIT
description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum: PLLPBIT
- name: PLLQEN - name: PLLQEN
description: Main PLL PLLUSB1CLK output enable description: Main PLL PLLUSB1CLK output enable
bit_offset: 20 bit_offset: 20
@ -1322,6 +1325,7 @@ fieldset/PLLCFGR:
description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) description: Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
enum: PLLQ
- name: PLLREN - name: PLLREN
description: Main PLL PLLCLK output enable description: Main PLL PLLCLK output enable
bit_offset: 24 bit_offset: 24
@ -1330,10 +1334,12 @@ fieldset/PLLCFGR:
description: Main PLL division factor for PLLCLK (system clock) description: Main PLL division factor for PLLCLK (system clock)
bit_offset: 25 bit_offset: 25
bit_size: 2 bit_size: 2
- name: PLLPDIV enum: PLLR
- name: PLLP
description: Main PLL division factor for PLLSAI2CLK description: Main PLL division factor for PLLSAI2CLK
bit_offset: 27 bit_offset: 27
bit_size: 5 bit_size: 5
enum: PLLP
enum/ADCSEL: enum/ADCSEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -1445,6 +1451,376 @@ enum/MCOSEL:
- name: HSI48 - name: HSI48
description: HSI48 selected as MCO source description: HSI48 selected as MCO source
value: 8 value: 8
enum/PLLM:
bit_size: 4
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
enum/PLLN:
bit_size: 7
variants:
- name: Mul8
value: 8
- name: Mul9
value: 9
- name: Mul10
value: 10
- name: Mul11
value: 11
- name: Mul12
value: 12
- name: Mul13
value: 13
- name: Mul14
value: 14
- name: Mul15
value: 15
- name: Mul16
value: 16
- name: Mul17
value: 17
- name: Mul18
value: 18
- name: Mul19
value: 19
- name: Mul20
value: 20
- name: Mul21
value: 21
- name: Mul22
value: 22
- name: Mul23
value: 23
- name: Mul24
value: 24
- name: Mul25
value: 25
- name: Mul26
value: 26
- name: Mul27
value: 27
- name: Mul28
value: 28
- name: Mul29
value: 29
- name: Mul30
value: 30
- name: Mul31
value: 31
- name: Mul32
value: 32
- name: Mul33
value: 33
- name: Mul34
value: 34
- name: Mul35
value: 35
- name: Mul36
value: 36
- name: Mul37
value: 37
- name: Mul38
value: 38
- name: Mul39
value: 39
- name: Mul40
value: 40
- name: Mul41
value: 41
- name: Mul42
value: 42
- name: Mul43
value: 43
- name: Mul44
value: 44
- name: Mul45
value: 45
- name: Mul46
value: 46
- name: Mul47
value: 47
- name: Mul48
value: 48
- name: Mul49
value: 49
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
- name: Mul87
value: 87
- name: Mul88
value: 88
- name: Mul89
value: 89
- name: Mul90
value: 90
- name: Mul91
value: 91
- name: Mul92
value: 92
- name: Mul93
value: 93
- name: Mul94
value: 94
- name: Mul95
value: 95
- name: Mul96
value: 96
- name: Mul97
value: 97
- name: Mul98
value: 98
- name: Mul99
value: 99
- name: Mul100
value: 100
- name: Mul101
value: 101
- name: Mul102
value: 102
- name: Mul103
value: 103
- name: Mul104
value: 104
- name: Mul105
value: 105
- name: Mul106
value: 106
- name: Mul107
value: 107
- name: Mul108
value: 108
- name: Mul109
value: 109
- name: Mul110
value: 110
- name: Mul111
value: 111
- name: Mul112
value: 112
- name: Mul113
value: 113
- name: Mul114
value: 114
- name: Mul115
value: 115
- name: Mul116
value: 116
- name: Mul117
value: 117
- name: Mul118
value: 118
- name: Mul119
value: 119
- name: Mul120
value: 120
- name: Mul121
value: 121
- name: Mul122
value: 122
- name: Mul123
value: 123
- name: Mul124
value: 124
- name: Mul125
value: 125
- name: Mul126
value: 126
- name: Mul127
value: 127
enum/PLLP:
bit_size: 7
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
enum/PLLPBIT:
bit_size: 1
variants:
- name: Div7
value: 0
- name: Div17
value: 1
enum/PLLQ:
bit_size: 2
variants:
- name: Div2
value: 0
- name: Div4
value: 1
- name: Div6
value: 2
- name: Div8
value: 3
enum/PLLR:
bit_size: 2
variants:
- name: Div2
value: 0
- name: Div4
value: 1
- name: Div6
value: 2
- name: Div8
value: 3
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

1412
data/registers/rcc_h5.yaml
View File

File diff suppressed because it is too large Load Diff

1412
data/registers/rcc_h50.yaml
View File

File diff suppressed because it is too large Load Diff

1412
data/registers/rcc_h7.yaml
View File

File diff suppressed because it is too large Load Diff

1412
data/registers/rcc_h7ab.yaml
View File

File diff suppressed because it is too large Load Diff

1414
data/registers/rcc_h7rm0433.yaml
View File

File diff suppressed because it is too large Load Diff

465
data/registers/rcc_l4.yaml
View File

@ -20,11 +20,11 @@ block/RCC:
- name: PLLSAI1CFGR - name: PLLSAI1CFGR
description: PLLSAI1 configuration register description: PLLSAI1 configuration register
byte_offset: 16 byte_offset: 16
fieldset: PLLSAI1CFGR fieldset: PLLSAICFGR
- name: PLLSAI2CFGR - name: PLLSAI2CFGR
description: PLLSAI2 configuration register description: PLLSAI2 configuration register
byte_offset: 20 byte_offset: 20
fieldset: PLLSAI2CFGR fieldset: PLLSAICFGR
- name: CIER - name: CIER
description: Clock interrupt enable register description: Clock interrupt enable register
byte_offset: 24 byte_offset: 24
@ -1593,18 +1593,21 @@ fieldset/PLLCFGR:
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL multiplication factor for VCO description: Main PLL multiplication factor for VCO
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
enum: PLLN
- name: PLLPEN - name: PLLPEN
description: Main PLL PLLSAI3CLK output enable description: Main PLL PLLSAI3CLK output enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: PLLP - name: PLLPBIT
description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum: PLLPBIT
- name: PLLQEN - name: PLLQEN
description: Main PLL PLLUSB1CLK output enable description: Main PLL PLLUSB1CLK output enable
bit_offset: 20 bit_offset: 20
@ -1613,6 +1616,7 @@ fieldset/PLLCFGR:
description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) description: Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
enum: PLLQ
- name: PLLREN - name: PLLREN
description: Main PLL PLLCLK output enable description: Main PLL PLLCLK output enable
bit_offset: 24 bit_offset: 24
@ -1621,88 +1625,57 @@ fieldset/PLLCFGR:
description: Main PLL division factor for PLLCLK (system clock) description: Main PLL division factor for PLLCLK (system clock)
bit_offset: 25 bit_offset: 25
bit_size: 2 bit_size: 2
- name: PLLPDIV enum: PLLR
- name: PLLP
description: Main PLL division factor for PLLSAI2CLK description: Main PLL division factor for PLLSAI2CLK
bit_offset: 27 bit_offset: 27
bit_size: 5 bit_size: 5
fieldset/PLLSAI1CFGR: enum: PLLP
description: PLLSAI1 configuration register fieldset/PLLSAICFGR:
description: PLLSAI configuration register
fields: fields:
- name: PLLSAI1M - name: PLLM
description: Division factor for PLLSAI1 input clock description: Division factor for PLLSAI input clock
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
- name: PLLSAI1N enum: PLLM
- name: PLLN
description: SAI1PLL multiplication factor for VCO description: SAI1PLL multiplication factor for VCO
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
- name: PLLSAI1PEN enum: PLLN
description: SAI1PLL PLLSAI1CLK output enable - name: PLLPEN
description: SAI1PLL PLLSAICLK output enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: PLLSAI1P - name: PLLPBIT
description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) description: SAI1PLL division factor for PLLSAICLK
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: PLLSAI1QEN enum: PLLPBIT
- name: PLLQEN
description: SAI1PLL PLLUSB2CLK output enable description: SAI1PLL PLLUSB2CLK output enable
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: PLLSAI1Q - name: PLLQ
description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) description: SAI1PLL division factor for PLLUSB2CLK
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
- name: PLLSAI1REN enum: PLLQ
description: PLLSAI1 PLLADC1CLK output enable - name: PLLREN
description: PLLSAI PLLADC1CLK output enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: PLLSAI1R - name: PLLR
description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) description: PLLSAI division factor for PLLADC1CLK
bit_offset: 25 bit_offset: 25
bit_size: 2 bit_size: 2
- name: PLLSAI1PDIV enum: PLLR
description: PLLSAI1 division factor for PLLSAI1CLK - name: PLLP
bit_offset: 27 description: PLLSAI division factor for PLLSAICLK
bit_size: 5
fieldset/PLLSAI2CFGR:
description: PLLSAI2 configuration register
fields:
- name: PLLSAI2M
description: Division factor for PLLSAI2 input clock
bit_offset: 4
bit_size: 4
- name: PLLSAI2N
description: SAI2PLL multiplication factor for VCO
bit_offset: 8
bit_size: 7
- name: PLLSAI2PEN
description: SAI2PLL PLLSAI2CLK output enable
bit_offset: 16
bit_size: 1
- name: PLLSAI2P
description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
bit_offset: 17
bit_size: 1
- name: PLLSAI2QEN
description: PLLSAI2 division factor for PLLDISCLK
bit_offset: 20
bit_size: 1
- name: PLLSAI2Q
description: SAI2PLL PLLSAI2CLK output enable
bit_offset: 21
bit_size: 2
- name: PLLSAI2REN
description: PLLSAI2 PLLADC2CLK output enable
bit_offset: 24
bit_size: 1
- name: PLLSAI2R
description: PLLSAI2 division factor for PLLADC2CLK (ADC clock)
bit_offset: 25
bit_size: 2
- name: PLLSAI2PDIV
description: PLLSAI2 division factor for PLLSAI2CLK
bit_offset: 27 bit_offset: 27
bit_size: 5 bit_size: 5
enum: PLLP
enum/HPRE: enum/HPRE:
bit_size: 4 bit_size: 4
variants: variants:
@ -1835,6 +1808,376 @@ enum/MSIRANGE:
- name: Range48M - name: Range48M
description: range 11 around 48 MHz description: range 11 around 48 MHz
value: 11 value: 11
enum/PLLM:
bit_size: 4
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
enum/PLLN:
bit_size: 7
variants:
- name: Mul8
value: 8
- name: Mul9
value: 9
- name: Mul10
value: 10
- name: Mul11
value: 11
- name: Mul12
value: 12
- name: Mul13
value: 13
- name: Mul14
value: 14
- name: Mul15
value: 15
- name: Mul16
value: 16
- name: Mul17
value: 17
- name: Mul18
value: 18
- name: Mul19
value: 19
- name: Mul20
value: 20
- name: Mul21
value: 21
- name: Mul22
value: 22
- name: Mul23
value: 23
- name: Mul24
value: 24
- name: Mul25
value: 25
- name: Mul26
value: 26
- name: Mul27
value: 27
- name: Mul28
value: 28
- name: Mul29
value: 29
- name: Mul30
value: 30
- name: Mul31
value: 31
- name: Mul32
value: 32
- name: Mul33
value: 33
- name: Mul34
value: 34
- name: Mul35
value: 35
- name: Mul36
value: 36
- name: Mul37
value: 37
- name: Mul38
value: 38
- name: Mul39
value: 39
- name: Mul40
value: 40
- name: Mul41
value: 41
- name: Mul42
value: 42
- name: Mul43
value: 43
- name: Mul44
value: 44
- name: Mul45
value: 45
- name: Mul46
value: 46
- name: Mul47
value: 47
- name: Mul48
value: 48
- name: Mul49
value: 49
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
- name: Mul87
value: 87
- name: Mul88
value: 88
- name: Mul89
value: 89
- name: Mul90
value: 90
- name: Mul91
value: 91
- name: Mul92
value: 92
- name: Mul93
value: 93
- name: Mul94
value: 94
- name: Mul95
value: 95
- name: Mul96
value: 96
- name: Mul97
value: 97
- name: Mul98
value: 98
- name: Mul99
value: 99
- name: Mul100
value: 100
- name: Mul101
value: 101
- name: Mul102
value: 102
- name: Mul103
value: 103
- name: Mul104
value: 104
- name: Mul105
value: 105
- name: Mul106
value: 106
- name: Mul107
value: 107
- name: Mul108
value: 108
- name: Mul109
value: 109
- name: Mul110
value: 110
- name: Mul111
value: 111
- name: Mul112
value: 112
- name: Mul113
value: 113
- name: Mul114
value: 114
- name: Mul115
value: 115
- name: Mul116
value: 116
- name: Mul117
value: 117
- name: Mul118
value: 118
- name: Mul119
value: 119
- name: Mul120
value: 120
- name: Mul121
value: 121
- name: Mul122
value: 122
- name: Mul123
value: 123
- name: Mul124
value: 124
- name: Mul125
value: 125
- name: Mul126
value: 126
- name: Mul127
value: 127
enum/PLLP:
bit_size: 7
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
enum/PLLPBIT:
bit_size: 1
variants:
- name: Div7
value: 0
- name: Div17
value: 1
enum/PLLQ:
bit_size: 2
variants:
- name: Div2
value: 0
- name: Div4
value: 1
- name: Div6
value: 2
- name: Div8
value: 3
enum/PLLR:
bit_size: 2
variants:
- name: Div2
value: 0
- name: Div4
value: 1
- name: Div6
value: 2
- name: Div8
value: 3
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

457
data/registers/rcc_l5.yaml
View File

@ -20,11 +20,11 @@ block/RCC:
- name: PLLSAI1CFGR - name: PLLSAI1CFGR
description: PLLSAI1 configuration register description: PLLSAI1 configuration register
byte_offset: 16 byte_offset: 16
fieldset: PLLSAI1CFGR fieldset: PLLSAICFGR
- name: PLLSAI2CFGR - name: PLLSAI2CFGR
description: PLLSAI2 configuration register description: PLLSAI2 configuration register
byte_offset: 20 byte_offset: 20
fieldset: PLLSAI2CFGR fieldset: PLLSAICFGR
- name: CIER - name: CIER
description: Clock interrupt enable register description: Clock interrupt enable register
byte_offset: 24 byte_offset: 24
@ -1774,18 +1774,21 @@ fieldset/PLLCFGR:
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL multiplication factor for VCO description: Main PLL multiplication factor for VCO
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
enum: PLLN
- name: PLLPEN - name: PLLPEN
description: Main PLL PLLSAI3CLK output enable description: Main PLL PLLSAI3CLK output enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: PLLP - name: PLLPBIT
description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum: PLLPBIT
- name: PLLQEN - name: PLLQEN
description: Main PLL PLLUSB1CLK output enable description: Main PLL PLLUSB1CLK output enable
bit_offset: 20 bit_offset: 20
@ -1794,6 +1797,7 @@ fieldset/PLLCFGR:
description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) description: Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
enum: PLLQ
- name: PLLREN - name: PLLREN
description: Main PLL PLLCLK output enable description: Main PLL PLLCLK output enable
bit_offset: 24 bit_offset: 24
@ -1802,80 +1806,57 @@ fieldset/PLLCFGR:
description: Main PLL division factor for PLLCLK (system clock) description: Main PLL division factor for PLLCLK (system clock)
bit_offset: 25 bit_offset: 25
bit_size: 2 bit_size: 2
- name: PLLPDIV enum: PLLR
- name: PLLP
description: Main PLL division factor for PLLSAI2CLK description: Main PLL division factor for PLLSAI2CLK
bit_offset: 27 bit_offset: 27
bit_size: 5 bit_size: 5
fieldset/PLLSAI1CFGR: enum: PLLP
description: PLLSAI1 configuration register fieldset/PLLSAICFGR:
description: PLLSAI configuration register
fields: fields:
- name: PLLSAI1SRC - name: PLLM
description: PLLSAI1SRC description: Division factor for PLLSAI input clock
bit_offset: 0
bit_size: 2
- name: PLLSAI1M
description: Division factor for PLLSAI1 input clock
bit_offset: 4 bit_offset: 4
bit_size: 4 bit_size: 4
- name: PLLSAI1N enum: PLLM
- name: PLLN
description: SAI1PLL multiplication factor for VCO description: SAI1PLL multiplication factor for VCO
bit_offset: 8 bit_offset: 8
bit_size: 7 bit_size: 7
- name: PLLSAI1PEN enum: PLLN
description: SAI1PLL PLLSAI1CLK output enable - name: PLLPEN
description: SAI1PLL PLLSAICLK output enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: PLLSAI1P - name: PLLPBIT
description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) description: SAI1PLL division factor for PLLSAICLK
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: PLLSAI1QEN enum: PLLPBIT
- name: PLLQEN
description: SAI1PLL PLLUSB2CLK output enable description: SAI1PLL PLLUSB2CLK output enable
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: PLLSAI1Q - name: PLLQ
description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) description: SAI1PLL division factor for PLLUSB2CLK
bit_offset: 21 bit_offset: 21
bit_size: 2 bit_size: 2
- name: PLLSAI1REN enum: PLLQ
description: PLLSAI1 PLLADC1CLK output enable - name: PLLREN
description: PLLSAI PLLADC1CLK output enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: PLLSAI1R - name: PLLR
description: PLLSAI1 division factor for PLLADC1CLK (ADC clock) description: PLLSAI division factor for PLLADC1CLK
bit_offset: 25 bit_offset: 25
bit_size: 2 bit_size: 2
- name: PLLSAI1PDIV enum: PLLR
description: PLLSAI1 division factor for PLLSAI1CLK - name: PLLP
bit_offset: 27 description: PLLSAI division factor for PLLSAICLK
bit_size: 5
fieldset/PLLSAI2CFGR:
description: PLLSAI2 configuration register
fields:
- name: PLLSAI2SRC
description: PLLSAI2SRC
bit_offset: 0
bit_size: 2
- name: PLLSAI2M
description: Division factor for PLLSAI2 input clock
bit_offset: 4
bit_size: 4
- name: PLLSAI2N
description: SAI2PLL multiplication factor for VCO
bit_offset: 8
bit_size: 7
- name: PLLSAI2PEN
description: SAI2PLL PLLSAI2CLK output enable
bit_offset: 16
bit_size: 1
- name: PLLSAI2P
description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
bit_offset: 17
bit_size: 1
- name: PLLSAI2PDIV
description: PLLSAI2 division factor for PLLSAI2CLK
bit_offset: 27 bit_offset: 27
bit_size: 5 bit_size: 5
enum: PLLP
fieldset/SECCFGR: fieldset/SECCFGR:
description: RCC secure configuration register description: RCC secure configuration register
fields: fields:
@ -2127,6 +2108,376 @@ enum/MSIRANGE:
- name: Range48M - name: Range48M
description: range 11 around 48 MHz description: range 11 around 48 MHz
value: 11 value: 11
enum/PLLM:
bit_size: 4
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
enum/PLLN:
bit_size: 7
variants:
- name: Mul8
value: 8
- name: Mul9
value: 9
- name: Mul10
value: 10
- name: Mul11
value: 11
- name: Mul12
value: 12
- name: Mul13
value: 13
- name: Mul14
value: 14
- name: Mul15
value: 15
- name: Mul16
value: 16
- name: Mul17
value: 17
- name: Mul18
value: 18
- name: Mul19
value: 19
- name: Mul20
value: 20
- name: Mul21
value: 21
- name: Mul22
value: 22
- name: Mul23
value: 23
- name: Mul24
value: 24
- name: Mul25
value: 25
- name: Mul26
value: 26
- name: Mul27
value: 27
- name: Mul28
value: 28
- name: Mul29
value: 29
- name: Mul30
value: 30
- name: Mul31
value: 31
- name: Mul32
value: 32
- name: Mul33
value: 33
- name: Mul34
value: 34
- name: Mul35
value: 35
- name: Mul36
value: 36
- name: Mul37
value: 37
- name: Mul38
value: 38
- name: Mul39
value: 39
- name: Mul40
value: 40
- name: Mul41
value: 41
- name: Mul42
value: 42
- name: Mul43
value: 43
- name: Mul44
value: 44
- name: Mul45
value: 45
- name: Mul46
value: 46
- name: Mul47
value: 47
- name: Mul48
value: 48
- name: Mul49
value: 49
- name: Mul50
value: 50
- name: Mul51
value: 51
- name: Mul52
value: 52
- name: Mul53
value: 53
- name: Mul54
value: 54
- name: Mul55
value: 55
- name: Mul56
value: 56
- name: Mul57
value: 57
- name: Mul58
value: 58
- name: Mul59
value: 59
- name: Mul60
value: 60
- name: Mul61
value: 61
- name: Mul62
value: 62
- name: Mul63
value: 63
- name: Mul64
value: 64
- name: Mul65
value: 65
- name: Mul66
value: 66
- name: Mul67
value: 67
- name: Mul68
value: 68
- name: Mul69
value: 69
- name: Mul70
value: 70
- name: Mul71
value: 71
- name: Mul72
value: 72
- name: Mul73
value: 73
- name: Mul74
value: 74
- name: Mul75
value: 75
- name: Mul76
value: 76
- name: Mul77
value: 77
- name: Mul78
value: 78
- name: Mul79
value: 79
- name: Mul80
value: 80
- name: Mul81
value: 81
- name: Mul82
value: 82
- name: Mul83
value: 83
- name: Mul84
value: 84
- name: Mul85
value: 85
- name: Mul86
value: 86
- name: Mul87
value: 87
- name: Mul88
value: 88
- name: Mul89
value: 89
- name: Mul90
value: 90
- name: Mul91
value: 91
- name: Mul92
value: 92
- name: Mul93
value: 93
- name: Mul94
value: 94
- name: Mul95
value: 95
- name: Mul96
value: 96
- name: Mul97
value: 97
- name: Mul98
value: 98
- name: Mul99
value: 99
- name: Mul100
value: 100
- name: Mul101
value: 101
- name: Mul102
value: 102
- name: Mul103
value: 103
- name: Mul104
value: 104
- name: Mul105
value: 105
- name: Mul106
value: 106
- name: Mul107
value: 107
- name: Mul108
value: 108
- name: Mul109
value: 109
- name: Mul110
value: 110
- name: Mul111
value: 111
- name: Mul112
value: 112
- name: Mul113
value: 113
- name: Mul114
value: 114
- name: Mul115
value: 115
- name: Mul116
value: 116
- name: Mul117
value: 117
- name: Mul118
value: 118
- name: Mul119
value: 119
- name: Mul120
value: 120
- name: Mul121
value: 121
- name: Mul122
value: 122
- name: Mul123
value: 123
- name: Mul124
value: 124
- name: Mul125
value: 125
- name: Mul126
value: 126
- name: Mul127
value: 127
enum/PLLP:
bit_size: 7
variants:
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
enum/PLLPBIT:
bit_size: 1
variants:
- name: Div7
value: 0
- name: Div17
value: 1
enum/PLLQ:
bit_size: 2
variants:
- name: Div2
value: 0
- name: Div4
value: 1
- name: Div6
value: 2
- name: Div8
value: 3
enum/PLLR:
bit_size: 2
variants:
- name: Div2
value: 0
- name: Div4
value: 1
- name: Div6
value: 2
- name: Div8
value: 3
enum/PLLSRC: enum/PLLSRC:
bit_size: 2 bit_size: 2
variants: variants:

1480
data/registers/rcc_u5.yaml
View File

File diff suppressed because it is too large Load Diff