From e857c9cb94604fc1d34036b08fb44fa843e88410 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sat, 24 Feb 2024 19:18:09 +0800
Subject: [PATCH] add enum for `NAND` block

---
 data/registers/fmc_v4.yaml | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/data/registers/fmc_v4.yaml b/data/registers/fmc_v4.yaml
index cf57c2d..4a74e4f 100644
--- a/data/registers/fmc_v4.yaml
+++ b/data/registers/fmc_v4.yaml
@@ -257,10 +257,12 @@ fieldset/PCR:
     description: Memory type Defines the type of device attached to the corresponding memory bank:.
     bit_offset: 3
     bit_size: 1
+    enum: PTYP
   - name: PWID
     description: Data bus width Defines the external memory device width.
     bit_offset: 4
     bit_size: 2
+    enum: PWID
   - name: ECCEN
     description: ECC computation logic enable bit.
     bit_offset: 6
@@ -272,15 +274,12 @@ fieldset/PCR:
   - name: TAR
     description: 'ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.'
     bit_offset: 13
-    bit_size: 3
-  - name: TAR3
-    description: 'ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space.'
-    bit_offset: 16
-    bit_size: 1
+    bit_size: 4
   - name: ECCPS
     description: ECC page size Defines the page size for the extended ECC:.
     bit_offset: 17
     bit_size: 3
+    enum: ECCPS
 fieldset/PCSCNTR:
   description: PSRAM chip select counter register.
   fields:
@@ -644,6 +643,12 @@ enum/NR:
   - name: Bits13
     description: 13 bits
     value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+  - name: NAND
+    description: NAND flash
+    value: 1
 enum/PWID:
   bit_size: 2
   variants: