diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 8d4c422..a1eed1d 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -1626,11 +1626,11 @@ fieldset/CCIPR5: bit_offset: 19 bit_size: 3 enum: SAISEL - - name: CKPERSEL + - name: PERSEL description: per_ck clock source selection bit_offset: 30 bit_size: 2 - enum: CKPERSEL + enum: PERSEL fieldset/CFGR: description: RCC clock configuration register fields: @@ -2107,7 +2107,7 @@ fieldset/SECCFGR: description: "Remove reset flag security\r Set and reset by software." bit_offset: 12 bit_size: 1 - - name: CKPERSELSEC + - name: PERSELSEC description: "per_ck selection security\r Set and reset by software." bit_offset: 13 bit_size: 1 @@ -2144,18 +2144,6 @@ enum/CECSEL: - name: CSI_DIV_122 description: csi_ker_ck/122 selected as kernel clock value: 2 -enum/CKPERSEL: - bit_size: 2 - variants: - - name: HSI - description: hsi_ker_ck selected as kernel clock (default after reset) - value: 0 - - name: CSI - description: csi_ker_ck selected as kernel clock - value: 1 - - name: HSE - description: hse_ck selected as kernel clock - value: 2 enum/DACHOLDSEL: bit_size: 1 variants: @@ -2465,6 +2453,18 @@ enum/OCTOSPISEL: - name: PER description: per_ck selected as kernel clock value: 3 +enum/PERSEL: + bit_size: 2 + variants: + - name: HSI + description: hsi_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: CSI + description: csi_ker_ck selected as kernel clock + value: 1 + - name: HSE + description: hse_ck selected as kernel clock + value: 2 enum/PLLDIV: bit_size: 7 variants: diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 842b1ba..2bedff9 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -910,11 +910,11 @@ fieldset/CCIPR5: bit_offset: 8 bit_size: 2 enum: FDCANSEL - - name: CKPERSEL + - name: PERSEL description: per_ck clock source selection bit_offset: 30 bit_size: 2 - enum: CKPERSEL + enum: PERSEL fieldset/CFGR: description: RCC clock configuration register fields: @@ -1353,18 +1353,6 @@ enum/ADCDACSEL: - name: CSI description: csi_ker_ck selected as kernel clock value: 5 -enum/CKPERSEL: - bit_size: 2 - variants: - - name: HSI - description: hsi_ker_ck selected as kernel clock (default after reset) - value: 0 - - name: CSI - description: csi_ker_ck selected as kernel clock - value: 1 - - name: HSE - description: hse_ck selected as kernel clock - value: 2 enum/DACHOLDSEL: bit_size: 1 variants: @@ -1644,6 +1632,18 @@ enum/MCOPRE: - name: Div15 description: Divide by 15 value: 15 +enum/PERSEL: + bit_size: 2 + variants: + - name: HSI + description: hsi_ker_ck selected as kernel clock (default after reset) + value: 0 + - name: CSI + description: csi_ker_ck selected as kernel clock + value: 1 + - name: HSE + description: hse_ck selected as kernel clock + value: 2 enum/PLLDIV: bit_size: 7 variants: diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 5da553f..d3d5b62 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -3081,11 +3081,11 @@ fieldset/D1CCIPR: bit_offset: 16 bit_size: 1 enum: SDMMCSEL - - name: CKPERSEL + - name: PERSEL description: per_ck clock source selection bit_offset: 28 bit_size: 2 - enum: CKPERSEL + enum: PERSEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: @@ -3541,18 +3541,6 @@ enum/CECSEL: - name: CSI description: csi_ker selected as peripheral clock value: 2 -enum/CKPERSEL: - bit_size: 2 - variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 enum/DFSDMSEL: bit_size: 1 variants: @@ -3838,6 +3826,18 @@ enum/MCOPRE: - name: Div15 description: Divide by 15 value: 15 +enum/PERSEL: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 enum/PLLDIV: bit_size: 7 variants: diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 69230d0..c58645e 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -2027,11 +2027,11 @@ fieldset/D1CCIPR: bit_offset: 16 bit_size: 1 enum: SDMMCSEL - - name: CKPERSEL + - name: PERSEL description: per_ck clock source selection bit_offset: 28 bit_size: 2 - enum: CKPERSEL + enum: PERSEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: @@ -2455,18 +2455,6 @@ enum/CECSEL: - name: CSI description: csi_ker selected as peripheral clock value: 2 -enum/CKPERSEL: - bit_size: 2 - variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 enum/DFSDMSEL: bit_size: 1 variants: @@ -2752,6 +2740,18 @@ enum/MCOPRE: - name: Div15 description: Divide by 15 value: 15 +enum/PERSEL: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 enum/PLLDIV: bit_size: 7 variants: diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 38ae54b..90549fa 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -3064,11 +3064,11 @@ fieldset/D1CCIPR: bit_offset: 16 bit_size: 1 enum: SDMMCSEL - - name: CKPERSEL + - name: PERSEL description: per_ck clock source selection bit_offset: 28 bit_size: 2 - enum: CKPERSEL + enum: PERSEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: @@ -3524,18 +3524,6 @@ enum/CECSEL: - name: CSI description: csi_ker selected as peripheral clock value: 2 -enum/CKPERSEL: - bit_size: 2 - variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 enum/DFSDMSEL: bit_size: 1 variants: @@ -3821,6 +3809,18 @@ enum/MCOPRE: - name: Div15 description: Divide by 15 value: 15 +enum/PERSEL: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 enum/PLLDIV: bit_size: 7 variants: diff --git a/data/registers/vrefbuf_v2a1.yaml b/data/registers/vrefbuf_v2a1.yaml index f7be8a0..4d31550 100644 --- a/data/registers/vrefbuf_v2a1.yaml +++ b/data/registers/vrefbuf_v2a1.yaml @@ -60,4 +60,4 @@ enum/VRS: value: 2 - name: Vref3 description: Voltage reference set to VREF_OUT2 (around 2.5 V). - value: 3 \ No newline at end of file + value: 3 diff --git a/data/registers/vrefbuf_v2b.yaml b/data/registers/vrefbuf_v2b.yaml index 78b59b1..9802dba 100644 --- a/data/registers/vrefbuf_v2b.yaml +++ b/data/registers/vrefbuf_v2b.yaml @@ -57,4 +57,4 @@ enum/VRS: value: 1 - name: Vref2 description: Voltage reference set to VREF_OUT2 (around 2.5 V). - value: 2 \ No newline at end of file + value: 2 diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index fed750f..ed3d7b5 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -285,6 +285,9 @@ impl ParsedRccs { ("I2C2", &["I2C1235"]), ("I2C3", &["I2C1235"]), ("I2C5", &["I2C1235"]), + ("USB", &["USB", "CLK48", "ICLK"]), + ("USB_OTG_FS", &["USB", "CLK48", "ICLK"]), + ("USB_OTG_HS", &["USB", "CLK48", "ICLK"]), ]; let rcc = self.rccs.get(rcc_version)?; @@ -315,7 +318,20 @@ impl ParsedRccs { } rcc::KernelClock::Mux(mux.mux.clone()) } - None => rcc::KernelClock::Clock(maybe_kernel_clock), + None => { + if peri_name.starts_with("USB") { + if rcc_version.starts_with("f1") || rcc_version.starts_with("f3") { + maybe_kernel_clock = "USB".to_string(); + } else if rcc_version.starts_with("f2") { + maybe_kernel_clock = "PLL1_Q".to_string(); + } else if rcc_version.starts_with("l1") { + maybe_kernel_clock = "PLL1_VCO_DIV_2".to_string(); + } else { + panic!("rcc_{}: peripheral {} missing mux", rcc_version, peri_name) + } + } + rcc::KernelClock::Clock(maybe_kernel_clock) + } }; Some(peripheral::Rcc {