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add pwr_l4

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Philip A Reimer 2022-04-09 10:06:32 -06:00
parent c90234583e
commit e81eeb157e
2 changed files with 1273 additions and 0 deletions
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1272
data/registers/pwr_l4.yaml Normal file
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1
stm32data/__main__.py
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@ -212,6 +212,7 @@ perimap = [
('STM32F4.*:PWR:.*', ('pwr', 'f4', 'PWR')), ('STM32F4.*:PWR:.*', ('pwr', 'f4', 'PWR')),
('STM32F7.*:PWR:.*', ('pwr', 'f7', 'PWR')), ('STM32F7.*:PWR:.*', ('pwr', 'f7', 'PWR')),
('STM32L1.*:PWR:.*', ('pwr', 'l1', 'PWR')), ('STM32L1.*:PWR:.*', ('pwr', 'l1', 'PWR')),
('STM32L4.*:PWR:.*', ('pwr', 'l4', 'PWR')),
('STM32U5.*:PWR:.*', ('pwr', 'u5', 'PWR')), ('STM32U5.*:PWR:.*', ('pwr', 'u5', 'PWR')),
('STM32WL.*:PWR:.*', ('pwr', 'wl5', 'PWR')), ('STM32WL.*:PWR:.*', ('pwr', 'wl5', 'PWR')),
('STM32WB.*:PWR:.*', ('pwr', 'wb55', 'PWR')), ('STM32WB.*:PWR:.*', ('pwr', 'wb55', 'PWR')),