rcc/c0: sysdiv doesn't exist.

data/registers/rcc_c0.yaml

@@ -466,11 +466,6 @@ fieldset/CIFR:
 fieldset/CR:
   description: RCC clock control register
   fields:
-  - name: SYSDIV
-    description: "System clock division factor\r This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:"
-    bit_offset: 2
-    bit_size: 3
-    enum: SYSDIV
   - name: HSIKERDIV
     description: "HSI kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:"
     bit_offset: 5
@@ -919,33 +914,6 @@ enum/SW:
   - name: LSE
     description: LSE selected as system clock
     value: 4
-enum/SYSDIV:
-  bit_size: 3
-  variants:
-  - name: Div1
-    description: '1'
-    value: 0
-  - name: Div2
-    description: '2'
-    value: 1
-  - name: Div3
-    description: 3 (reset value)
-    value: 2
-  - name: Div4
-    description: '4'
-    value: 3
-  - name: Div5
-    description: '5'
-    value: 4
-  - name: Div6
-    description: '6'
-    value: 5
-  - name: Div7
-    description: '7'
-    value: 6
-  - name: Div8
-    description: '8'
-    value: 7
 enum/USART1SEL:
   bit_size: 2
   variants: