From ded4f5205162600b038db65919ab0d030f170ee8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Tue, 3 Aug 2021 10:51:07 +0200 Subject: [PATCH 1/5] rcc_f4: Remove duplicate USBF bit --- data/registers/rcc_l4.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 9e498ea..0b07812 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -644,10 +644,6 @@ fieldset/APB1ENR1: bit_size: 1 description: CAN1 clock enable name: CAN1EN - - bit_offset: 26 - bit_size: 1 - description: USB FS clock enable - name: USBF - bit_offset: 26 bit_size: 1 description: USB FS clock enable From d1597c646d2721b19732a4f91e0d294f85e2c43b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Tue, 3 Aug 2021 10:51:38 +0200 Subject: [PATCH 2/5] rcc_l0: Remove duplicate I2C3 reset bit --- data/registers/rcc_l0.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 11c0e42..a96b843 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -826,10 +826,6 @@ fieldset/APB1RSTR: description: Power interface reset enum_write: LPTIMRSTW name: PWRRST - - bit_offset: 30 - bit_size: 1 - description: I2C3 reset - name: I2C3 - bit_offset: 31 bit_size: 1 description: Low power timer reset From babbe782f3ff7c24ec5ffe9230c727726661f8a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Tue, 3 Aug 2021 14:31:36 +0200 Subject: [PATCH 3/5] rcc_l0: Remove non existing RCC bits ## firewall l0x0, l0x1: FWEN - Firewall clock enable bit l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit action: none ## watchdog peripheral: WWDG WWDGRST vs WWDRST action: remove ## CRS vs CRC l0x2, l0x3: CRC reset is wrong action: remove duplicate CRC bit ## LPUART12RST vs USART2RST action: rename, it sholud be USART2 --- data/registers/rcc_l0.yaml | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index a96b843..a692aac 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -816,11 +816,6 @@ fieldset/APB1RSTR: description: I2C2 reset enum_write: LPTIMRSTW name: I2C2RST - - bit_offset: 27 - bit_size: 1 - description: CRC reset - enum_write: LPTIMRSTW - name: CRCRST - bit_offset: 28 bit_size: 1 description: Power interface reset @@ -836,16 +831,6 @@ fieldset/APB1RSTR: description: I2C3 reset enum_write: LPTIMRSTW name: I2C3RST - - bit_offset: 11 - bit_size: 1 - description: Window watchdog reset - enum_write: LPTIMRSTW - name: WWDRST - - bit_offset: 17 - bit_size: 1 - description: UART2 reset - enum_write: LPTIMRSTW - name: LPUART12RST - bit_offset: 23 bit_size: 1 description: USB reset From f865878b4b6ff7cac30dea17162c4bd1dbd83917 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Tue, 3 Aug 2021 14:42:02 +0200 Subject: [PATCH 4/5] rcc_f4: Fix RCC bits ## LPTIM1EN / LPTIMER1EN Only stm32f413 has LPTIM1 peripheral, ref manual bit names: LPTIMER1EN, LPTIMER1RST, LPTIMER1LPEN, LPTIMER1SEL action: Rename to LPTIM1(EN|RST|...) for consistency (matches peripheral name) ## FMC / FSMC not available as peripheral in the YAML anyway.. TODO: why? EN and RST FSMC: f405, f407, f412, f413 FSC: f427, f429, f446, f469 action: none ## CECEN / CAN3EN mutually exclusive peripherals, alias ok? CECEN: f446 CAN3EN: f413 action: split off f4x3 yaml, f423 exists, but not available as svd ## USART / UART all over the place, register names in ref manual not always consistent stm32 follows a simple rule for the actual peripherals: USART 1-3, 6 UART 4, 5, 7-10 action: rename enable/rst bits to rules above --- data/registers/rcc_f4.yaml | 50 +------------------------------------- 1 file changed, 1 insertion(+), 49 deletions(-) diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index e6e749a..02ec8f2 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1565,10 +1565,6 @@ fieldset/APB1ENR: bit_size: 1 description: FMPI2C1 clock enable name: FMPI2C1EN - - bit_offset: 9 - bit_size: 1 - description: LPTimer 1 clock enable - name: LPTIMER1EN - bit_offset: 27 bit_size: 1 description: CAN 3 clock enable @@ -1696,18 +1692,6 @@ fieldset/APB1LPENR: bit_size: 1 description: FMPI2C1 clock enable during Sleep name: FMPI2C1LPEN - - bit_offset: 9 - bit_size: 1 - description: TIM14 clock enable during Sleep mode - name: LPTIMER1LPEN - - bit_offset: 19 - bit_size: 1 - description: USART4 clock enable during Sleep mode - name: USART4LPEN - - bit_offset: 20 - bit_size: 1 - description: USART5 clock enable during Sleep mode - name: USART5LPEN - bit_offset: 27 bit_size: 1 description: CAN3 clock enable during Sleep mode @@ -1802,7 +1786,7 @@ fieldset/APB1RSTR: - bit_offset: 18 bit_size: 1 description: USART 3 reset - name: UART3RST + name: USART3RST - bit_offset: 19 bit_size: 1 description: USART 4 reset @@ -1831,22 +1815,6 @@ fieldset/APB1RSTR: bit_size: 1 description: FMPI2C1 reset name: FMPI2C1RST - - bit_offset: 18 - bit_size: 1 - description: USART3RST - name: USART3RST - - bit_offset: 9 - bit_size: 1 - description: LPTimer1 reset - name: LPTIMER1RST - - bit_offset: 19 - bit_size: 1 - description: USART4 reset - name: USART4RST - - bit_offset: 20 - bit_size: 1 - description: USART5 reset - name: USART5RST - bit_offset: 27 bit_size: 1 description: CAN 3 reset @@ -2041,18 +2009,10 @@ fieldset/APB2LPENR: bit_size: 1 description: UART9 clock enable during Sleep mode name: UART9LPEN - - bit_offset: 6 - bit_size: 1 - description: USART9 clock enable during Sleep mode - name: USART9LPEN - bit_offset: 7 bit_size: 1 description: UART10 clock enable during Sleep mode name: UART10LPEN - - bit_offset: 7 - bit_size: 1 - description: USART10 clock enable during Sleep mode - name: USART10LPEN - bit_offset: 22 bit_size: 1 description: SAI1 clock enable during Sleep mode @@ -2140,14 +2100,6 @@ fieldset/APB2RSTR: bit_size: 1 description: UART9 reset name: UART9RST - - bit_offset: 6 - bit_size: 1 - description: USART9 reset - name: USART9RST - - bit_offset: 7 - bit_size: 1 - description: USART10 reset - name: SART10RST - bit_offset: 7 bit_size: 1 description: UART10 reset From 7506b50031fa4cad973539342275c8a506759ce7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timo=20Kr=C3=B6ger?= Date: Tue, 3 Aug 2021 15:23:54 +0200 Subject: [PATCH 5/5] rcc_l4: Remove duplicate bits --- data/registers/rcc_f4.yaml | 4 ++-- data/registers/rcc_l4.yaml | 26 +------------------------- 2 files changed, 3 insertions(+), 27 deletions(-) diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 02ec8f2..91d8ce1 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1789,11 +1789,11 @@ fieldset/APB1RSTR: name: USART3RST - bit_offset: 19 bit_size: 1 - description: USART 4 reset + description: UART 4 reset name: UART4RST - bit_offset: 20 bit_size: 1 - description: USART 5 reset + description: UART 5 reset name: UART5RST - bit_offset: 25 bit_size: 1 diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 0b07812..f469afd 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -338,10 +338,6 @@ fieldset/AHB2ENR: bit_size: 1 description: HASH clock enable name: HASHEN - - bit_offset: 17 - bit_size: 1 - description: HASH clock enable - name: HASH1EN - bit_offset: 18 bit_size: 1 description: Random Number Generator clock enable @@ -413,10 +409,6 @@ fieldset/AHB2RSTR: bit_size: 1 description: Hash reset name: HASHRST - - bit_offset: 17 - bit_size: 1 - description: Hash reset - name: HASH1RST - bit_offset: 18 bit_size: 1 description: Random number generator reset @@ -600,14 +592,10 @@ fieldset/APB1ENR1: bit_size: 1 description: SPI2 clock enable name: SPI2EN - - bit_offset: 15 - bit_size: 1 - description: SPI peripheral 3 clock enable - name: SPI3EN - bit_offset: 15 bit_size: 1 description: SPI3 clock enable - name: SP3EN + name: SPI3EN - bit_offset: 17 bit_size: 1 description: USART2 clock enable @@ -742,10 +730,6 @@ fieldset/APB1RSTR1: bit_size: 1 description: UART4 reset name: UART4RST - - bit_offset: 19 - bit_size: 1 - description: USART4 reset. - name: USART4RST - bit_offset: 20 bit_size: 1 description: UART5 reset @@ -872,10 +856,6 @@ fieldset/APB1SMENR1: bit_size: 1 description: UART4 clocks enable during Sleep and Stop modes name: UART4SMEN - - bit_offset: 19 - bit_size: 1 - description: USART4 clocks enable during Sleep and Stop modes - name: USART4SMEN - bit_offset: 20 bit_size: 1 description: UART5 clocks enable during Sleep and Stop modes @@ -1206,10 +1186,6 @@ fieldset/CCIPR: bit_size: 2 description: UART4 clock source selection name: UART4SEL - - bit_offset: 6 - bit_size: 2 - description: USART4 clock source selection - name: USART4SEL - bit_offset: 8 bit_size: 2 description: UART5 clock source selection