From 64a23e1213cd96da3269a9107fda44df942df3fd Mon Sep 17 00:00:00 2001 From: Karun Date: Tue, 23 Jan 2024 15:55:19 -0500 Subject: [PATCH 01/12] update perimap for stm32u5[34]5 octospi implementations --- stm32-data-gen/src/chips.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c1fe6cd..f1bb1ce 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -500,7 +500,11 @@ impl PeriMatcher { ("octospi", "v1", "OCTOSPI"), ), ( - "STM32U5.*:OCTOSPI[12]:OCTOSPI:octospi1_v3_0.*", + "STM32U5[34].*:OCTOSPI[12]:OCTOSPI:octospi_v1_0L5.*", + ("octospi", "v1", "OCTOSPI"), + ), + ( + "STM32U5[AFG789].*:OCTOSPI[12]:OCTOSPI:octospi1_v3_0.*", ("octospi", "v1", "OCTOSPI"), ), ( From 33331ec8e256320713964873bab6396c38e6c834 Mon Sep 17 00:00:00 2001 From: Cryowatt Date: Fri, 26 Jan 2024 15:11:08 -0800 Subject: [PATCH 02/12] Adding SAI 1.2 mapping to PERIMAP Adding registers for sai_v1_2 Transformed and cleaned Adding SAI 1.2 mapping to PERIMAP v5 was the same as v2, deleting v5 Removed trailing whitespace --- stm32-data-gen/src/chips.rs | 1 + transforms/SAI.yaml | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index f1bb1ce..c68fb43 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -274,6 +274,7 @@ impl PeriMatcher { (".*:RTC:rtc3_v3_0", ("rtc", "v3", "RTC")), (".*:SAI:sai1_v1_0", ("sai", "v1", "SAI")), (".*:SAI:sai1_v1_1", ("sai", "v2", "SAI")), + (".*:SAI:sai1_v1_2", ("sai", "v2", "SAI")), (".*:SAI:sai1_v2_0", ("sai", "v1", "SAI")), (".*:SAI:sai1_H7", ("sai", "v3", "SAI")), (".*:SAI:sai1_v2_1", ("sai", "v4", "SAI")), diff --git a/transforms/SAI.yaml b/transforms/SAI.yaml index 2f49573..93c4d1c 100644 --- a/transforms/SAI.yaml +++ b/transforms/SAI.yaml @@ -1,3 +1,3 @@ transforms: - !DeleteEnums - from: ^(AFSDET|AFSDET|FREQ|LFSDET|MUTEDET|OVRUDR|FFLUSH)$ + from: ^(C?AFSDET(IE)?|CCNRDY|CNRDYIE|COVRUDR|CWCKCFG|DMAEN|FFLUSH|FREQ(IE)?|C?LFSDET(IE)?|MUTE|C?MUTEDET(IE)?|OVRUDR(IE)?|SAIEN|WCKCFGIE)$ \ No newline at end of file From 505f4dabf5c6707033542637ef53fa54a13ead46 Mon Sep 17 00:00:00 2001 From: Karun Koppula Date: Fri, 26 Jan 2024 19:36:41 -0500 Subject: [PATCH 03/12] Fix register address mapping --- stm32-data-gen/src/header.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs index 50e4702..d3927a5 100644 --- a/stm32-data-gen/src/header.rs +++ b/stm32-data-gen/src/header.rs @@ -162,6 +162,14 @@ impl Defines { ("DBGMCU", &["DBGMCU_BASE", "DBG_BASE"]), ("QUADSPI", &["QUADSPI_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]), ("QUADSPI1", &["QUADSPI1_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]), + ( + "OCTOSPI", + &["OSPI_R", "OCTOSPI_R_BASE", "OCTOSPI_R_BASE_NS", "OCTOSPI_REG_BASE"], + ), + ( + "OCTOSPI1", + &["OSPI_R", "OCTOSPI1_R_BASE", "OCTOSPI1_R_BASE_NS", "OCTOSPI1_REG_BASE"], + ), ("FLASH", &["FLASH_R_BASE", "FLASH_REG_BASE"]), ( "ADC_COMMON", From 2acb6a4682ac9627554bf330f5cbab2016353754 Mon Sep 17 00:00:00 2001 From: Taylor Carpenter Date: Sat, 27 Jan 2024 00:43:53 -0500 Subject: [PATCH 04/12] Fix crc version mapping CRC version mapping is now done by family before failing back to the IP version listed in MCU XML Versions now match what is on spreadsheet --- stm32-data-gen/src/chips.rs | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c68fb43..3b1828e 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -471,13 +471,15 @@ impl PeriMatcher { (".*:FDCAN:fdcan1_v1_[01].*", ("can", "fdcan_v1", "FDCAN")), ("STM32H7.*:FDCANRAM.*", ("fdcanram", "h7", "FDCANRAM")), (".*:FDCANRAM.*", ("fdcanram", "v1", "FDCANRAM")), - // # stm32F4 CRC peripheral - // # ("STM32F4*:CRC:CRC:crc_f4") - // # v1: F1, F2, F4, L1 - // # v2, adds INIT reg: F0 - // # v3, adds POL reg: F3, F7, G0, G4, H7, L0, L4, L5, WB, WL - (".*:CRC:integtest1_v1_0", ("crc", "v1", "CRC")), - ("STM32L[04].*:CRC:integtest1_v2_0", ("crc", "v3", "CRC")), + ("STM32F[124].*:CRC:.*", ("crc", "v1", "CRC")), + ("STM32L1.*:CRC:.*", ("crc", "v1", "CRC")), + ("STM32F0.*:CRC:.*", ("crc", "v2", "CRC")), + ("STM32F[37].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32G[04].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32H[7].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32L[045].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32W[BL].*:CRC:.*", ("crc", "v3", "CRC")), + (".*:CRC:integtest1_v1_0", ("crc", "v1", "CRC")), // Fall back on the 'integtest' naming (".*:CRC:integtest1_v2_0", ("crc", "v2", "CRC")), (".*:CRC:integtest1_v2_2", ("crc", "v3", "CRC")), (".*:LCD:lcdc1_v1.0.*", ("lcd", "v1", "LCD")), From 136f53de04e6e34911dac3b16cda32d604f614dc Mon Sep 17 00:00:00 2001 From: Taylor Carpenter Date: Sun, 28 Jan 2024 20:11:54 -0500 Subject: [PATCH 05/12] Match all versions of CRC by chip family --- stm32-data-gen/src/chips.rs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 3b1828e..5c7a45e 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -476,12 +476,11 @@ impl PeriMatcher { ("STM32F0.*:CRC:.*", ("crc", "v2", "CRC")), ("STM32F[37].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32G[04].*:CRC:.*", ("crc", "v3", "CRC")), - ("STM32H[7].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32H[57].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32L[045].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32W[BL].*:CRC:.*", ("crc", "v3", "CRC")), - (".*:CRC:integtest1_v1_0", ("crc", "v1", "CRC")), // Fall back on the 'integtest' naming - (".*:CRC:integtest1_v2_0", ("crc", "v2", "CRC")), - (".*:CRC:integtest1_v2_2", ("crc", "v3", "CRC")), + ("STM32C[0].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32U[5].*:CRC:.*", ("crc", "v3", "CRC")), (".*:LCD:lcdc1_v1.0.*", ("lcd", "v1", "LCD")), (".*:LCD:lcdc1_v1.2.*", ("lcd", "v2", "LCD")), (".*:LCD:lcdc1_v1.3.*", ("lcd", "v2", "LCD")), From 6fae02614a020a890dc95d22465516573aa85389 Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Mon, 29 Jan 2024 18:48:07 -0500 Subject: [PATCH 06/12] Added hash registers and perimap. --- data/registers/hash_v1.yaml | 137 +++++++++++++++++++++++++++++ data/registers/hash_v2.yaml | 159 ++++++++++++++++++++++++++++++++++ data/registers/hash_v3.yaml | 167 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 4 + 4 files changed, 467 insertions(+) create mode 100644 data/registers/hash_v1.yaml create mode 100644 data/registers/hash_v2.yaml create mode 100644 data/registers/hash_v3.yaml diff --git a/data/registers/hash_v1.yaml b/data/registers/hash_v1.yaml new file mode 100644 index 0000000..1afddec --- /dev/null +++ b/data/registers/hash_v1.yaml @@ -0,0 +1,137 @@ +block/HASH: + description: Hash processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: DIN + description: data input register. + byte_offset: 4 + access: Write + fieldset: DIN + - name: STR + description: start register. + byte_offset: 8 + access: Write + fieldset: STR + - name: HR + description: digest registers. + array: + len: 5 + stride: 4 + byte_offset: 12 + access: Read + fieldset: HR + - name: IMR + description: interrupt enable register. + byte_offset: 32 + fieldset: IMR + - name: SR + description: status register. + byte_offset: 36 + fieldset: SR + - name: CSR + description: context swap registers. + array: + len: 51 + stride: 4 + byte_offset: 248 + fieldset: CSR +fieldset/CR: + description: control register. + fields: + - name: INIT + description: Initialize message digest calculation. + bit_offset: 2 + bit_size: 1 + - name: DMAE + description: DMA enable. + bit_offset: 3 + bit_size: 1 + - name: DATATYPE + description: Data type selection. + bit_offset: 4 + bit_size: 2 + - name: MODE + description: Mode selection. + bit_offset: 6 + bit_size: 1 + - name: ALGO + description: Algorithm selection. + bit_offset: 7 + bit_size: 1 + - name: NBW + description: Number of words already pushed. + bit_offset: 8 + bit_size: 4 + - name: DINNE + description: DIN not empty. + bit_offset: 12 + bit_size: 1 + - name: LKEY + description: Long key selection. + bit_offset: 16 + bit_size: 1 +fieldset/CSR: + description: context swap registers. + fields: + - name: CSR + description: CSR0. + bit_offset: 0 + bit_size: 32 +fieldset/DIN: + description: data input register. + fields: + - name: DATAIN + description: Data input. + bit_offset: 0 + bit_size: 32 +fieldset/HR: + description: digest registers. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/IMR: + description: interrupt enable register. + fields: + - name: DINIE + description: Data input interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: DCIE + description: Digest calculation completion interrupt enable. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: DINIS + description: Data input interrupt status. + bit_offset: 0 + bit_size: 1 + - name: DCIS + description: Digest calculation completion interrupt status. + bit_offset: 1 + bit_size: 1 + - name: DMAS + description: DMA Status. + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 3 + bit_size: 1 +fieldset/STR: + description: start register. + fields: + - name: NBLW + description: Number of valid bits in the last word of the message. + bit_offset: 0 + bit_size: 5 + - name: DCAL + description: Digest calculation. + bit_offset: 8 + bit_size: 1 diff --git a/data/registers/hash_v2.yaml b/data/registers/hash_v2.yaml new file mode 100644 index 0000000..cc3e2a0 --- /dev/null +++ b/data/registers/hash_v2.yaml @@ -0,0 +1,159 @@ +block/HASH: + description: Hash processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: DIN + description: data input register. + byte_offset: 4 + access: Write + fieldset: DIN + - name: STR + description: start register. + byte_offset: 8 + fieldset: STR + - name: HRA + description: digest registers. + array: + len: 5 + stride: 4 + byte_offset: 12 + access: Read + fieldset: HRA + - name: IMR + description: interrupt enable register. + byte_offset: 32 + fieldset: IMR + - name: SR + description: status register. + byte_offset: 36 + fieldset: SR + - name: CSR + description: context swap registers. + array: + len: 54 + stride: 4 + byte_offset: 248 + fieldset: CSR + - name: HR + description: HASH digest register. + array: + len: 8 + stride: 4 + byte_offset: 784 + access: Read + fieldset: HR +fieldset/CR: + description: control register. + fields: + - name: INIT + description: Initialize message digest calculation. + bit_offset: 2 + bit_size: 1 + - name: DMAE + description: DMA enable. + bit_offset: 3 + bit_size: 1 + - name: DATATYPE + description: Data type selection. + bit_offset: 4 + bit_size: 2 + - name: MODE + description: Mode selection. + bit_offset: 6 + bit_size: 1 + - name: ALGO0 + description: Algorithm selection. + bit_offset: 7 + bit_size: 1 + - name: NBW + description: Number of words already pushed. + bit_offset: 8 + bit_size: 4 + - name: DINNE + description: DIN not empty. + bit_offset: 12 + bit_size: 1 + - name: MDMAT + description: Multiple DMA Transfers. + bit_offset: 13 + bit_size: 1 + - name: LKEY + description: Long key selection. + bit_offset: 16 + bit_size: 1 + - name: ALGO1 + description: ALGO. + bit_offset: 18 + bit_size: 1 +fieldset/CSR: + description: context swap registers. + fields: + - name: CSR + description: CSR0. + bit_offset: 0 + bit_size: 32 +fieldset/DIN: + description: data input register. + fields: + - name: DATAIN + description: Data input. + bit_offset: 0 + bit_size: 32 +fieldset/HR: + description: HASH digest register. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/HRA: + description: digest registers. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/IMR: + description: interrupt enable register. + fields: + - name: DINIE + description: Data input interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: DCIE + description: Digest calculation completion interrupt enable. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: DINIS + description: Data input interrupt status. + bit_offset: 0 + bit_size: 1 + - name: DCIS + description: Digest calculation completion interrupt status. + bit_offset: 1 + bit_size: 1 + - name: DMAS + description: DMA Status. + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 3 + bit_size: 1 +fieldset/STR: + description: start register. + fields: + - name: NBLW + description: Number of valid bits in the last word of the message. + bit_offset: 0 + bit_size: 5 + - name: DCAL + description: Digest calculation. + bit_offset: 8 + bit_size: 1 diff --git a/data/registers/hash_v3.yaml b/data/registers/hash_v3.yaml new file mode 100644 index 0000000..d8a31f6 --- /dev/null +++ b/data/registers/hash_v3.yaml @@ -0,0 +1,167 @@ +block/HASH: + description: Hash processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: DIN + description: data input register. + byte_offset: 4 + access: Write + fieldset: DIN + - name: STR + description: start register. + byte_offset: 8 + fieldset: STR + - name: HRA + description: digest registers. + array: + len: 5 + stride: 4 + byte_offset: 12 + access: Read + fieldset: HRA + - name: IMR + description: interrupt enable register. + byte_offset: 32 + fieldset: IMR + - name: SR + description: status register. + byte_offset: 36 + fieldset: SR + - name: CSR + description: context swap registers. + array: + len: 54 + stride: 4 + byte_offset: 248 + fieldset: CSR + - name: HR + description: HASH digest register. + array: + len: 8 + stride: 4 + byte_offset: 784 + access: Read + fieldset: HR +fieldset/CR: + description: control register. + fields: + - name: INIT + description: Initialize message digest calculation. + bit_offset: 2 + bit_size: 1 + - name: DMAE + description: DMA enable. + bit_offset: 3 + bit_size: 1 + - name: DATATYPE + description: Data type selection. + bit_offset: 4 + bit_size: 2 + - name: MODE + description: Mode selection. + bit_offset: 6 + bit_size: 1 + - name: NBW + description: Number of words already pushed. + bit_offset: 8 + bit_size: 4 + - name: DINNE + description: DIN not empty. + bit_offset: 12 + bit_size: 1 + - name: MDMAT + description: Multiple DMA Transfers. + bit_offset: 13 + bit_size: 1 + - name: LKEY + description: Long key selection. + bit_offset: 16 + bit_size: 1 + - name: ALGO + description: Algorithm selection. + bit_offset: 17 + bit_size: 2 +fieldset/CSR: + description: context swap registers. + fields: + - name: CSR + description: CSR0. + bit_offset: 0 + bit_size: 32 +fieldset/DIN: + description: data input register. + fields: + - name: DATAIN + description: Data input. + bit_offset: 0 + bit_size: 32 +fieldset/HR: + description: HASH digest register. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/HRA: + description: digest registers. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/IMR: + description: interrupt enable register. + fields: + - name: DINIE + description: Data input interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: DCIE + description: Digest calculation completion interrupt enable. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: DINIS + description: Data input interrupt status. + bit_offset: 0 + bit_size: 1 + - name: DCIS + description: Digest calculation completion interrupt status. + bit_offset: 1 + bit_size: 1 + - name: DMAS + description: DMA Status. + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 3 + bit_size: 1 + - name: NBWP + description: Number of words already pushed. + bit_offset: 9 + bit_size: 5 + - name: DINNE + description: DIN not empty. + bit_offset: 15 + bit_size: 1 + - name: NBWE + description: Number of words expected. + bit_offset: 16 + bit_size: 5 +fieldset/STR: + description: start register. + fields: + - name: NBLW + description: Number of valid bits in the last word of the message. + bit_offset: 0 + bit_size: 5 + - name: DCAL + description: Digest calculation. + bit_offset: 8 + bit_size: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 5c7a45e..0b9df9e 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -528,6 +528,10 @@ impl PeriMatcher { ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")), ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")), ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")), + (".*:HASH:hash1_v1_0", ("hash", "v1", "HASH")), + (".*:HASH:hash1_v2_0", ("hash", "v2", "HASH")), + (".*:HASH:hash1_v2_2", ("hash", "v2", "HASH")), + (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")), ]; Self { From b14a4f1f18d2781b1aec7ee356720f645ad607e0 Mon Sep 17 00:00:00 2001 From: Carlos Barrales Ruiz Date: Tue, 30 Jan 2024 01:01:13 +0100 Subject: [PATCH 07/12] Fix UART definitions present in STM32F1 series (sci2_v1_1) --- stm32-data-gen/src/chips.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 5c7a45e..95ca041 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -122,6 +122,7 @@ impl PeriMatcher { (".*:USART:sci3_v1_2", ("usart", "v4", "USART")), (".*:USART:sci3_v2_0", ("usart", "v4", "USART")), (".*:USART:sci3_v2_1", ("usart", "v4", "USART")), + (".*:UART:sci2_v1_1", ("usart", "v1", "USART")), (".*:UART:sci2_v1_2_F4", ("usart", "v2", "USART")), (".*:UART:sci2_v2_1", ("usart", "v3", "USART")), (".*:UART:sci2_v3_0", ("usart", "v4", "USART")), From ab2bc2a739324793656ca1640e1caee2d88df72d Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 30 Jan 2024 02:22:27 +0100 Subject: [PATCH 08/12] rcc: fix h5 fdcan inconsistency. --- data/registers/rcc_h50.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index ae5d726..38dfa38 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -379,7 +379,7 @@ fieldset/APB1HENR: description: "LPTIM2 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - - name: FDCAN1EN + - name: FDCAN12EN description: "FDCAN1 peripheral clock enable\r Set and reset by software." bit_offset: 9 bit_size: 1 @@ -394,7 +394,7 @@ fieldset/APB1HLPENR: description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - - name: FDCAN1LPEN + - name: FDCAN12LPEN description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software." bit_offset: 9 bit_size: 1 @@ -409,7 +409,7 @@ fieldset/APB1HRSTR: description: "LPTIM2 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - - name: FDCAN1RST + - name: FDCAN12RST description: "FDCAN1 block reset\r Set and reset by software." bit_offset: 9 bit_size: 1 @@ -905,7 +905,7 @@ fieldset/CCIPR5: bit_offset: 4 bit_size: 2 enum: RNGSEL - - name: FDCAN1SEL + - name: FDCAN12SEL description: FDCAN1 kernel clock source selection bit_offset: 8 bit_size: 2 From 6ed714a195a342e0d7d13a446972535e661ca6fe Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Mon, 29 Jan 2024 20:46:56 -0500 Subject: [PATCH 09/12] Removed hash fieldsets for single 32-bit wide fields. --- data/registers/hash_v1.yaml | 24 ------------------------ data/registers/hash_v2.yaml | 32 -------------------------------- data/registers/hash_v3.yaml | 32 -------------------------------- 3 files changed, 88 deletions(-) diff --git a/data/registers/hash_v1.yaml b/data/registers/hash_v1.yaml index 1afddec..ef179b1 100644 --- a/data/registers/hash_v1.yaml +++ b/data/registers/hash_v1.yaml @@ -9,7 +9,6 @@ block/HASH: description: data input register. byte_offset: 4 access: Write - fieldset: DIN - name: STR description: start register. byte_offset: 8 @@ -22,7 +21,6 @@ block/HASH: stride: 4 byte_offset: 12 access: Read - fieldset: HR - name: IMR description: interrupt enable register. byte_offset: 32 @@ -37,7 +35,6 @@ block/HASH: len: 51 stride: 4 byte_offset: 248 - fieldset: CSR fieldset/CR: description: control register. fields: @@ -73,27 +70,6 @@ fieldset/CR: description: Long key selection. bit_offset: 16 bit_size: 1 -fieldset/CSR: - description: context swap registers. - fields: - - name: CSR - description: CSR0. - bit_offset: 0 - bit_size: 32 -fieldset/DIN: - description: data input register. - fields: - - name: DATAIN - description: Data input. - bit_offset: 0 - bit_size: 32 -fieldset/HR: - description: digest registers. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 fieldset/IMR: description: interrupt enable register. fields: diff --git a/data/registers/hash_v2.yaml b/data/registers/hash_v2.yaml index cc3e2a0..b80ef98 100644 --- a/data/registers/hash_v2.yaml +++ b/data/registers/hash_v2.yaml @@ -9,7 +9,6 @@ block/HASH: description: data input register. byte_offset: 4 access: Write - fieldset: DIN - name: STR description: start register. byte_offset: 8 @@ -21,7 +20,6 @@ block/HASH: stride: 4 byte_offset: 12 access: Read - fieldset: HRA - name: IMR description: interrupt enable register. byte_offset: 32 @@ -36,7 +34,6 @@ block/HASH: len: 54 stride: 4 byte_offset: 248 - fieldset: CSR - name: HR description: HASH digest register. array: @@ -44,7 +41,6 @@ block/HASH: stride: 4 byte_offset: 784 access: Read - fieldset: HR fieldset/CR: description: control register. fields: @@ -88,34 +84,6 @@ fieldset/CR: description: ALGO. bit_offset: 18 bit_size: 1 -fieldset/CSR: - description: context swap registers. - fields: - - name: CSR - description: CSR0. - bit_offset: 0 - bit_size: 32 -fieldset/DIN: - description: data input register. - fields: - - name: DATAIN - description: Data input. - bit_offset: 0 - bit_size: 32 -fieldset/HR: - description: HASH digest register. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 -fieldset/HRA: - description: digest registers. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 fieldset/IMR: description: interrupt enable register. fields: diff --git a/data/registers/hash_v3.yaml b/data/registers/hash_v3.yaml index d8a31f6..9d310d7 100644 --- a/data/registers/hash_v3.yaml +++ b/data/registers/hash_v3.yaml @@ -9,7 +9,6 @@ block/HASH: description: data input register. byte_offset: 4 access: Write - fieldset: DIN - name: STR description: start register. byte_offset: 8 @@ -21,7 +20,6 @@ block/HASH: stride: 4 byte_offset: 12 access: Read - fieldset: HRA - name: IMR description: interrupt enable register. byte_offset: 32 @@ -36,7 +34,6 @@ block/HASH: len: 54 stride: 4 byte_offset: 248 - fieldset: CSR - name: HR description: HASH digest register. array: @@ -44,7 +41,6 @@ block/HASH: stride: 4 byte_offset: 784 access: Read - fieldset: HR fieldset/CR: description: control register. fields: @@ -84,34 +80,6 @@ fieldset/CR: description: Algorithm selection. bit_offset: 17 bit_size: 2 -fieldset/CSR: - description: context swap registers. - fields: - - name: CSR - description: CSR0. - bit_offset: 0 - bit_size: 32 -fieldset/DIN: - description: data input register. - fields: - - name: DATAIN - description: Data input. - bit_offset: 0 - bit_size: 32 -fieldset/HR: - description: HASH digest register. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 -fieldset/HRA: - description: digest registers. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 fieldset/IMR: description: interrupt enable register. fields: From d7a1c8e2312befc2e2fbe636b6c9703b0a22f6db Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Mon, 29 Jan 2024 21:31:07 -0500 Subject: [PATCH 10/12] Added cryp registers. Removed fieldsets for single 32-bit fields. --- data/registers/cryp_v1.yaml | 165 ++++++++++++++++++++++++++++++++ data/registers/cryp_v2.yaml | 185 ++++++++++++++++++++++++++++++++++++ 2 files changed, 350 insertions(+) create mode 100644 data/registers/cryp_v1.yaml create mode 100644 data/registers/cryp_v2.yaml diff --git a/data/registers/cryp_v1.yaml b/data/registers/cryp_v1.yaml new file mode 100644 index 0000000..2832b52 --- /dev/null +++ b/data/registers/cryp_v1.yaml @@ -0,0 +1,165 @@ +block/CRYP: + description: Cryptographic processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: DIN + description: data input register. + byte_offset: 8 + - name: DOUT + description: data output register. + byte_offset: 12 + access: Read + - name: DMACR + description: DMA control register. + byte_offset: 16 + fieldset: DMACR + - name: IMSCR + description: interrupt mask set/clear register. + byte_offset: 20 + fieldset: IMSCR + - name: RISR + description: raw interrupt status register. + byte_offset: 24 + access: Read + fieldset: RISR + - name: MISR + description: masked interrupt status register. + byte_offset: 28 + access: Read + fieldset: MISR + - name: KEY + description: Cluster KEY%s, containing K?LR, K?RR. + array: + len: 4 + stride: 8 + byte_offset: 32 + block: KEY + - name: INIT + description: Cluster INIT%s, containing IV?LR, IV?RR. + array: + len: 2 + stride: 8 + byte_offset: 64 + block: INIT +block/INIT: + description: Cluster INIT%s, containing IV?LR, IV?RR. + items: + - name: IVLR + description: initialization vector registers. + byte_offset: 0 + - name: IVRR + description: initialization vector registers. + byte_offset: 4 +block/KEY: + description: Cluster KEY%s, containing K?LR, K?RR. + items: + - name: KLR + description: key registers. + byte_offset: 0 + access: Write + - name: KRR + description: key registers. + byte_offset: 4 + access: Write +fieldset/CR: + description: control register. + fields: + - name: ALGODIR + description: Algorithm direction. + bit_offset: 2 + bit_size: 1 + - name: ALGOMODE + description: Algorithm mode. + bit_offset: 3 + bit_size: 3 + - name: DATATYPE + description: Data type selection. + bit_offset: 6 + bit_size: 2 + - name: KEYSIZE + description: Key size selection (AES mode only). + bit_offset: 8 + bit_size: 2 + - name: FFLUSH + description: FIFO flush. + bit_offset: 14 + bit_size: 1 + - name: CRYPEN + description: Cryptographic processor enable. + bit_offset: 15 + bit_size: 1 +fieldset/DMACR: + description: DMA control register. + fields: + - name: DIEN + description: DMA input enable. + bit_offset: 0 + bit_size: 1 + - name: DOEN + description: DMA output enable. + bit_offset: 1 + bit_size: 1 +fieldset/IMSCR: + description: interrupt mask set/clear register. + fields: + - name: INIM + description: Input FIFO service interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: OUTIM + description: Output FIFO service interrupt mask. + bit_offset: 1 + bit_size: 1 +fieldset/MISR: + description: masked interrupt status register. + fields: + - name: INMIS + description: Input FIFO service masked interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTMIS + description: Output FIFO service masked interrupt status. + bit_offset: 1 + bit_size: 1 +fieldset/RISR: + description: raw interrupt status register. + fields: + - name: INRIS + description: Input FIFO service raw interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTRIS + description: Output FIFO service raw interrupt status. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: IFEM + description: Input FIFO empty. + bit_offset: 0 + bit_size: 1 + - name: IFNF + description: Input FIFO not full. + bit_offset: 1 + bit_size: 1 + - name: OFNE + description: Output FIFO not empty. + bit_offset: 2 + bit_size: 1 + - name: OFFU + description: Output FIFO full. + bit_offset: 3 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 4 + bit_size: 1 diff --git a/data/registers/cryp_v2.yaml b/data/registers/cryp_v2.yaml new file mode 100644 index 0000000..04df876 --- /dev/null +++ b/data/registers/cryp_v2.yaml @@ -0,0 +1,185 @@ +block/CRYP: + description: Cryptographic processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: DIN + description: data input register. + byte_offset: 8 + - name: DOUT + description: data output register. + byte_offset: 12 + access: Read + - name: DMACR + description: DMA control register. + byte_offset: 16 + fieldset: DMACR + - name: IMSCR + description: interrupt mask set/clear register. + byte_offset: 20 + fieldset: IMSCR + - name: RISR + description: raw interrupt status register. + byte_offset: 24 + access: Read + fieldset: RISR + - name: MISR + description: masked interrupt status register. + byte_offset: 28 + access: Read + fieldset: MISR + - name: KEY + description: Cluster KEY%s, containing K?LR, K?RR. + array: + len: 4 + stride: 8 + byte_offset: 32 + block: KEY + - name: INIT + description: Cluster INIT%s, containing IV?LR, IV?RR. + array: + len: 2 + stride: 8 + byte_offset: 64 + block: INIT + - name: CSGCMCCMR + description: context swap register. + array: + len: 8 + stride: 4 + byte_offset: 80 + - name: CSGCMR + description: context swap register. + array: + len: 8 + stride: 4 + byte_offset: 112 +block/INIT: + description: Cluster INIT%s, containing IV?LR, IV?RR. + items: + - name: IVLR + description: initialization vector registers. + byte_offset: 0 + - name: IVRR + description: initialization vector registers. + byte_offset: 4 +block/KEY: + description: Cluster KEY%s, containing K?LR, K?RR. + items: + - name: KLR + description: key registers. + byte_offset: 0 + access: Write + - name: KRR + description: key registers. + byte_offset: 4 + access: Write +fieldset/CR: + description: control register. + fields: + - name: ALGODIR + description: Algorithm direction. + bit_offset: 2 + bit_size: 1 + - name: ALGOMODE0 + description: Algorithm mode. + bit_offset: 3 + bit_size: 3 + - name: DATATYPE + description: Data type selection. + bit_offset: 6 + bit_size: 2 + - name: KEYSIZE + description: Key size selection (AES mode only). + bit_offset: 8 + bit_size: 2 + - name: FFLUSH + description: FIFO flush. + bit_offset: 14 + bit_size: 1 + - name: CRYPEN + description: Cryptographic processor enable. + bit_offset: 15 + bit_size: 1 + - name: GCM_CCMPH + description: GCM_CCMPH. + bit_offset: 16 + bit_size: 2 + - name: ALGOMODE3 + description: ALGOMODE. + bit_offset: 19 + bit_size: 1 +fieldset/DMACR: + description: DMA control register. + fields: + - name: DIEN + description: DMA input enable. + bit_offset: 0 + bit_size: 1 + - name: DOEN + description: DMA output enable. + bit_offset: 1 + bit_size: 1 +fieldset/IMSCR: + description: interrupt mask set/clear register. + fields: + - name: INIM + description: Input FIFO service interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: OUTIM + description: Output FIFO service interrupt mask. + bit_offset: 1 + bit_size: 1 +fieldset/MISR: + description: masked interrupt status register. + fields: + - name: INMIS + description: Input FIFO service masked interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTMIS + description: Output FIFO service masked interrupt status. + bit_offset: 1 + bit_size: 1 +fieldset/RISR: + description: raw interrupt status register. + fields: + - name: INRIS + description: Input FIFO service raw interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTRIS + description: Output FIFO service raw interrupt status. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: IFEM + description: Input FIFO empty. + bit_offset: 0 + bit_size: 1 + - name: IFNF + description: Input FIFO not full. + bit_offset: 1 + bit_size: 1 + - name: OFNE + description: Output FIFO not empty. + bit_offset: 2 + bit_size: 1 + - name: OFFU + description: Output FIFO full. + bit_offset: 3 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 4 + bit_size: 1 From d3663f608b60e1dbaa0e341534d8e432d540c591 Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Mon, 29 Jan 2024 21:48:24 -0500 Subject: [PATCH 11/12] Added cryp perimap. --- stm32-data-gen/src/chips.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 1b6f541..4d75133 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -533,6 +533,9 @@ impl PeriMatcher { (".*:HASH:hash1_v2_0", ("hash", "v2", "HASH")), (".*:HASH:hash1_v2_2", ("hash", "v2", "HASH")), (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")), + (".*:CRYP:cryp1_v1_0", ("cryp", "v1", "CRYP")), + (".*:CRYP:cryp1_v2_0", ("cryp", "v2", "CRYP")), + (".*:CRYP:cryp1_v2_2", ("cryp", "v2", "CRYP")), ]; Self { From 0ec4390269902121fa23a315c3db4748e46085ef Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Tue, 30 Jan 2024 09:46:13 -0500 Subject: [PATCH 12/12] Corrected cryp perimap. --- stm32-data-gen/src/chips.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 4d75133..2826d77 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -533,9 +533,9 @@ impl PeriMatcher { (".*:HASH:hash1_v2_0", ("hash", "v2", "HASH")), (".*:HASH:hash1_v2_2", ("hash", "v2", "HASH")), (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")), - (".*:CRYP:cryp1_v1_0", ("cryp", "v1", "CRYP")), - (".*:CRYP:cryp1_v2_0", ("cryp", "v2", "CRYP")), - (".*:CRYP:cryp1_v2_2", ("cryp", "v2", "CRYP")), + (".*:CRYP:cryp1_v1_0.*", ("cryp", "v1", "CRYP")), + (".*:CRYP:cryp1_v2_0.*", ("cryp", "v2", "CRYP")), + (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")), ]; Self {