diff --git a/data/registers/cryp_v1.yaml b/data/registers/cryp_v1.yaml
new file mode 100644
index 0000000..2832b52
--- /dev/null
+++ b/data/registers/cryp_v1.yaml
@@ -0,0 +1,165 @@
+block/CRYP:
+  description: Cryptographic processor.
+  items:
+    - name: CR
+      description: control register.
+      byte_offset: 0
+      fieldset: CR
+    - name: SR
+      description: status register.
+      byte_offset: 4
+      access: Read
+      fieldset: SR
+    - name: DIN
+      description: data input register.
+      byte_offset: 8
+    - name: DOUT
+      description: data output register.
+      byte_offset: 12
+      access: Read
+    - name: DMACR
+      description: DMA control register.
+      byte_offset: 16
+      fieldset: DMACR
+    - name: IMSCR
+      description: interrupt mask set/clear register.
+      byte_offset: 20
+      fieldset: IMSCR
+    - name: RISR
+      description: raw interrupt status register.
+      byte_offset: 24
+      access: Read
+      fieldset: RISR
+    - name: MISR
+      description: masked interrupt status register.
+      byte_offset: 28
+      access: Read
+      fieldset: MISR
+    - name: KEY
+      description: Cluster KEY%s, containing K?LR, K?RR.
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 32
+      block: KEY
+    - name: INIT
+      description: Cluster INIT%s, containing IV?LR, IV?RR.
+      array:
+        len: 2
+        stride: 8
+      byte_offset: 64
+      block: INIT
+block/INIT:
+  description: Cluster INIT%s, containing IV?LR, IV?RR.
+  items:
+    - name: IVLR
+      description: initialization vector registers.
+      byte_offset: 0
+    - name: IVRR
+      description: initialization vector registers.
+      byte_offset: 4
+block/KEY:
+  description: Cluster KEY%s, containing K?LR, K?RR.
+  items:
+    - name: KLR
+      description: key registers.
+      byte_offset: 0
+      access: Write
+    - name: KRR
+      description: key registers.
+      byte_offset: 4
+      access: Write
+fieldset/CR:
+  description: control register.
+  fields:
+    - name: ALGODIR
+      description: Algorithm direction.
+      bit_offset: 2
+      bit_size: 1
+    - name: ALGOMODE
+      description: Algorithm mode.
+      bit_offset: 3
+      bit_size: 3
+    - name: DATATYPE
+      description: Data type selection.
+      bit_offset: 6
+      bit_size: 2
+    - name: KEYSIZE
+      description: Key size selection (AES mode only).
+      bit_offset: 8
+      bit_size: 2
+    - name: FFLUSH
+      description: FIFO flush.
+      bit_offset: 14
+      bit_size: 1
+    - name: CRYPEN
+      description: Cryptographic processor enable.
+      bit_offset: 15
+      bit_size: 1
+fieldset/DMACR:
+  description: DMA control register.
+  fields:
+    - name: DIEN
+      description: DMA input enable.
+      bit_offset: 0
+      bit_size: 1
+    - name: DOEN
+      description: DMA output enable.
+      bit_offset: 1
+      bit_size: 1
+fieldset/IMSCR:
+  description: interrupt mask set/clear register.
+  fields:
+    - name: INIM
+      description: Input FIFO service interrupt mask.
+      bit_offset: 0
+      bit_size: 1
+    - name: OUTIM
+      description: Output FIFO service interrupt mask.
+      bit_offset: 1
+      bit_size: 1
+fieldset/MISR:
+  description: masked interrupt status register.
+  fields:
+    - name: INMIS
+      description: Input FIFO service masked interrupt status.
+      bit_offset: 0
+      bit_size: 1
+    - name: OUTMIS
+      description: Output FIFO service masked interrupt status.
+      bit_offset: 1
+      bit_size: 1
+fieldset/RISR:
+  description: raw interrupt status register.
+  fields:
+    - name: INRIS
+      description: Input FIFO service raw interrupt status.
+      bit_offset: 0
+      bit_size: 1
+    - name: OUTRIS
+      description: Output FIFO service raw interrupt status.
+      bit_offset: 1
+      bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+    - name: IFEM
+      description: Input FIFO empty.
+      bit_offset: 0
+      bit_size: 1
+    - name: IFNF
+      description: Input FIFO not full.
+      bit_offset: 1
+      bit_size: 1
+    - name: OFNE
+      description: Output FIFO not empty.
+      bit_offset: 2
+      bit_size: 1
+    - name: OFFU
+      description: Output FIFO full.
+      bit_offset: 3
+      bit_size: 1
+    - name: BUSY
+      description: Busy bit.
+      bit_offset: 4
+      bit_size: 1
diff --git a/data/registers/cryp_v2.yaml b/data/registers/cryp_v2.yaml
new file mode 100644
index 0000000..04df876
--- /dev/null
+++ b/data/registers/cryp_v2.yaml
@@ -0,0 +1,185 @@
+block/CRYP:
+  description: Cryptographic processor.
+  items:
+    - name: CR
+      description: control register.
+      byte_offset: 0
+      fieldset: CR
+    - name: SR
+      description: status register.
+      byte_offset: 4
+      access: Read
+      fieldset: SR
+    - name: DIN
+      description: data input register.
+      byte_offset: 8
+    - name: DOUT
+      description: data output register.
+      byte_offset: 12
+      access: Read
+    - name: DMACR
+      description: DMA control register.
+      byte_offset: 16
+      fieldset: DMACR
+    - name: IMSCR
+      description: interrupt mask set/clear register.
+      byte_offset: 20
+      fieldset: IMSCR
+    - name: RISR
+      description: raw interrupt status register.
+      byte_offset: 24
+      access: Read
+      fieldset: RISR
+    - name: MISR
+      description: masked interrupt status register.
+      byte_offset: 28
+      access: Read
+      fieldset: MISR
+    - name: KEY
+      description: Cluster KEY%s, containing K?LR, K?RR.
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 32
+      block: KEY
+    - name: INIT
+      description: Cluster INIT%s, containing IV?LR, IV?RR.
+      array:
+        len: 2
+        stride: 8
+      byte_offset: 64
+      block: INIT
+    - name: CSGCMCCMR
+      description: context swap register.
+      array:
+        len: 8
+        stride: 4
+      byte_offset: 80
+    - name: CSGCMR
+      description: context swap register.
+      array:
+        len: 8
+        stride: 4
+      byte_offset: 112
+block/INIT:
+  description: Cluster INIT%s, containing IV?LR, IV?RR.
+  items:
+    - name: IVLR
+      description: initialization vector registers.
+      byte_offset: 0
+    - name: IVRR
+      description: initialization vector registers.
+      byte_offset: 4
+block/KEY:
+  description: Cluster KEY%s, containing K?LR, K?RR.
+  items:
+    - name: KLR
+      description: key registers.
+      byte_offset: 0
+      access: Write
+    - name: KRR
+      description: key registers.
+      byte_offset: 4
+      access: Write
+fieldset/CR:
+  description: control register.
+  fields:
+    - name: ALGODIR
+      description: Algorithm direction.
+      bit_offset: 2
+      bit_size: 1
+    - name: ALGOMODE0
+      description: Algorithm mode.
+      bit_offset: 3
+      bit_size: 3
+    - name: DATATYPE
+      description: Data type selection.
+      bit_offset: 6
+      bit_size: 2
+    - name: KEYSIZE
+      description: Key size selection (AES mode only).
+      bit_offset: 8
+      bit_size: 2
+    - name: FFLUSH
+      description: FIFO flush.
+      bit_offset: 14
+      bit_size: 1
+    - name: CRYPEN
+      description: Cryptographic processor enable.
+      bit_offset: 15
+      bit_size: 1
+    - name: GCM_CCMPH
+      description: GCM_CCMPH.
+      bit_offset: 16
+      bit_size: 2
+    - name: ALGOMODE3
+      description: ALGOMODE.
+      bit_offset: 19
+      bit_size: 1
+fieldset/DMACR:
+  description: DMA control register.
+  fields:
+    - name: DIEN
+      description: DMA input enable.
+      bit_offset: 0
+      bit_size: 1
+    - name: DOEN
+      description: DMA output enable.
+      bit_offset: 1
+      bit_size: 1
+fieldset/IMSCR:
+  description: interrupt mask set/clear register.
+  fields:
+    - name: INIM
+      description: Input FIFO service interrupt mask.
+      bit_offset: 0
+      bit_size: 1
+    - name: OUTIM
+      description: Output FIFO service interrupt mask.
+      bit_offset: 1
+      bit_size: 1
+fieldset/MISR:
+  description: masked interrupt status register.
+  fields:
+    - name: INMIS
+      description: Input FIFO service masked interrupt status.
+      bit_offset: 0
+      bit_size: 1
+    - name: OUTMIS
+      description: Output FIFO service masked interrupt status.
+      bit_offset: 1
+      bit_size: 1
+fieldset/RISR:
+  description: raw interrupt status register.
+  fields:
+    - name: INRIS
+      description: Input FIFO service raw interrupt status.
+      bit_offset: 0
+      bit_size: 1
+    - name: OUTRIS
+      description: Output FIFO service raw interrupt status.
+      bit_offset: 1
+      bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+    - name: IFEM
+      description: Input FIFO empty.
+      bit_offset: 0
+      bit_size: 1
+    - name: IFNF
+      description: Input FIFO not full.
+      bit_offset: 1
+      bit_size: 1
+    - name: OFNE
+      description: Output FIFO not empty.
+      bit_offset: 2
+      bit_size: 1
+    - name: OFFU
+      description: Output FIFO full.
+      bit_offset: 3
+      bit_size: 1
+    - name: BUSY
+      description: Busy bit.
+      bit_offset: 4
+      bit_size: 1
diff --git a/data/registers/hash_v1.yaml b/data/registers/hash_v1.yaml
new file mode 100644
index 0000000..ef179b1
--- /dev/null
+++ b/data/registers/hash_v1.yaml
@@ -0,0 +1,113 @@
+block/HASH:
+  description: Hash processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DIN
+    description: data input register.
+    byte_offset: 4
+    access: Write
+  - name: STR
+    description: start register.
+    byte_offset: 8
+    access: Write
+    fieldset: STR
+  - name: HR
+    description: digest registers.
+    array:
+      len: 5
+      stride: 4
+    byte_offset: 12
+    access: Read
+  - name: IMR
+    description: interrupt enable register.
+    byte_offset: 32
+    fieldset: IMR
+  - name: SR
+    description: status register.
+    byte_offset: 36
+    fieldset: SR
+  - name: CSR
+    description: context swap registers.
+    array:
+      len: 51
+      stride: 4
+    byte_offset: 248
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: INIT
+    description: Initialize message digest calculation.
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAE
+    description: DMA enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 4
+    bit_size: 2
+  - name: MODE
+    description: Mode selection.
+    bit_offset: 6
+    bit_size: 1
+  - name: ALGO
+    description: Algorithm selection.
+    bit_offset: 7
+    bit_size: 1
+  - name: NBW
+    description: Number of words already pushed.
+    bit_offset: 8
+    bit_size: 4
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 12
+    bit_size: 1
+  - name: LKEY
+    description: Long key selection.
+    bit_offset: 16
+    bit_size: 1
+fieldset/IMR:
+  description: interrupt enable register.
+  fields:
+  - name: DINIE
+    description: Data input interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIE
+    description: Digest calculation completion interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: DINIS
+    description: Data input interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIS
+    description: Digest calculation completion interrupt status.
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAS
+    description: DMA Status.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 3
+    bit_size: 1
+fieldset/STR:
+  description: start register.
+  fields:
+  - name: NBLW
+    description: Number of valid bits in the last word of the message.
+    bit_offset: 0
+    bit_size: 5
+  - name: DCAL
+    description: Digest calculation.
+    bit_offset: 8
+    bit_size: 1
diff --git a/data/registers/hash_v2.yaml b/data/registers/hash_v2.yaml
new file mode 100644
index 0000000..b80ef98
--- /dev/null
+++ b/data/registers/hash_v2.yaml
@@ -0,0 +1,127 @@
+block/HASH:
+  description: Hash processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DIN
+    description: data input register.
+    byte_offset: 4
+    access: Write
+  - name: STR
+    description: start register.
+    byte_offset: 8
+    fieldset: STR
+  - name: HRA
+    description: digest registers.
+    array:
+      len: 5
+      stride: 4
+    byte_offset: 12
+    access: Read
+  - name: IMR
+    description: interrupt enable register.
+    byte_offset: 32
+    fieldset: IMR
+  - name: SR
+    description: status register.
+    byte_offset: 36
+    fieldset: SR
+  - name: CSR
+    description: context swap registers.
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 248
+  - name: HR
+    description: HASH digest register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 784
+    access: Read
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: INIT
+    description: Initialize message digest calculation.
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAE
+    description: DMA enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 4
+    bit_size: 2
+  - name: MODE
+    description: Mode selection.
+    bit_offset: 6
+    bit_size: 1
+  - name: ALGO0
+    description: Algorithm selection.
+    bit_offset: 7
+    bit_size: 1
+  - name: NBW
+    description: Number of words already pushed.
+    bit_offset: 8
+    bit_size: 4
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 12
+    bit_size: 1
+  - name: MDMAT
+    description: Multiple DMA Transfers.
+    bit_offset: 13
+    bit_size: 1
+  - name: LKEY
+    description: Long key selection.
+    bit_offset: 16
+    bit_size: 1
+  - name: ALGO1
+    description: ALGO.
+    bit_offset: 18
+    bit_size: 1
+fieldset/IMR:
+  description: interrupt enable register.
+  fields:
+  - name: DINIE
+    description: Data input interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIE
+    description: Digest calculation completion interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: DINIS
+    description: Data input interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIS
+    description: Digest calculation completion interrupt status.
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAS
+    description: DMA Status.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 3
+    bit_size: 1
+fieldset/STR:
+  description: start register.
+  fields:
+  - name: NBLW
+    description: Number of valid bits in the last word of the message.
+    bit_offset: 0
+    bit_size: 5
+  - name: DCAL
+    description: Digest calculation.
+    bit_offset: 8
+    bit_size: 1
diff --git a/data/registers/hash_v3.yaml b/data/registers/hash_v3.yaml
new file mode 100644
index 0000000..9d310d7
--- /dev/null
+++ b/data/registers/hash_v3.yaml
@@ -0,0 +1,135 @@
+block/HASH:
+  description: Hash processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DIN
+    description: data input register.
+    byte_offset: 4
+    access: Write
+  - name: STR
+    description: start register.
+    byte_offset: 8
+    fieldset: STR
+  - name: HRA
+    description: digest registers.
+    array:
+      len: 5
+      stride: 4
+    byte_offset: 12
+    access: Read
+  - name: IMR
+    description: interrupt enable register.
+    byte_offset: 32
+    fieldset: IMR
+  - name: SR
+    description: status register.
+    byte_offset: 36
+    fieldset: SR
+  - name: CSR
+    description: context swap registers.
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 248
+  - name: HR
+    description: HASH digest register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 784
+    access: Read
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: INIT
+    description: Initialize message digest calculation.
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAE
+    description: DMA enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 4
+    bit_size: 2
+  - name: MODE
+    description: Mode selection.
+    bit_offset: 6
+    bit_size: 1
+  - name: NBW
+    description: Number of words already pushed.
+    bit_offset: 8
+    bit_size: 4
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 12
+    bit_size: 1
+  - name: MDMAT
+    description: Multiple DMA Transfers.
+    bit_offset: 13
+    bit_size: 1
+  - name: LKEY
+    description: Long key selection.
+    bit_offset: 16
+    bit_size: 1
+  - name: ALGO
+    description: Algorithm selection.
+    bit_offset: 17
+    bit_size: 2
+fieldset/IMR:
+  description: interrupt enable register.
+  fields:
+  - name: DINIE
+    description: Data input interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIE
+    description: Digest calculation completion interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: DINIS
+    description: Data input interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIS
+    description: Digest calculation completion interrupt status.
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAS
+    description: DMA Status.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 3
+    bit_size: 1
+  - name: NBWP
+    description: Number of words already pushed.
+    bit_offset: 9
+    bit_size: 5
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 15
+    bit_size: 1
+  - name: NBWE
+    description: Number of words expected.
+    bit_offset: 16
+    bit_size: 5
+fieldset/STR:
+  description: start register.
+  fields:
+  - name: NBLW
+    description: Number of valid bits in the last word of the message.
+    bit_offset: 0
+    bit_size: 5
+  - name: DCAL
+    description: Digest calculation.
+    bit_offset: 8
+    bit_size: 1
diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml
index ae5d726..38dfa38 100644
--- a/data/registers/rcc_h50.yaml
+++ b/data/registers/rcc_h50.yaml
@@ -379,7 +379,7 @@ fieldset/APB1HENR:
     description: "LPTIM2 clock enable\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1EN
+  - name: FDCAN12EN
     description: "FDCAN1 peripheral clock enable\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -394,7 +394,7 @@ fieldset/APB1HLPENR:
     description: "LPTIM2 clock enable during sleep mode\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1LPEN
+  - name: FDCAN12LPEN
     description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -409,7 +409,7 @@ fieldset/APB1HRSTR:
     description: "LPTIM2 block reset\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1RST
+  - name: FDCAN12RST
     description: "FDCAN1 block reset\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -905,7 +905,7 @@ fieldset/CCIPR5:
     bit_offset: 4
     bit_size: 2
     enum: RNGSEL
-  - name: FDCAN1SEL
+  - name: FDCAN12SEL
     description: FDCAN1 kernel clock source selection
     bit_offset: 8
     bit_size: 2
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index 920aaca..dfc89c8 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -122,6 +122,7 @@ impl PeriMatcher {
             (".*:USART:sci3_v1_2", ("usart", "v4", "USART")),
             (".*:USART:sci3_v2_0", ("usart", "v4", "USART")),
             (".*:USART:sci3_v2_1", ("usart", "v4", "USART")),
+            (".*:UART:sci2_v1_1", ("usart", "v1", "USART")),
             (".*:UART:sci2_v1_2_F4", ("usart", "v2", "USART")),
             (".*:UART:sci2_v2_1", ("usart", "v3", "USART")),
             (".*:UART:sci2_v3_0", ("usart", "v4", "USART")),
@@ -274,6 +275,7 @@ impl PeriMatcher {
             (".*:RTC:rtc3_v3_0", ("rtc", "v3", "RTC")),
             (".*:SAI:sai1_v1_0", ("sai", "v1", "SAI")),
             (".*:SAI:sai1_v1_1", ("sai", "v2", "SAI")),
+            (".*:SAI:sai1_v1_2", ("sai", "v2", "SAI")),
             (".*:SAI:sai1_v2_0", ("sai", "v1", "SAI")),
             (".*:SAI:sai1_H7", ("sai", "v3", "SAI")),
             (".*:SAI:sai1_v2_1", ("sai", "v4", "SAI")),
@@ -470,15 +472,16 @@ impl PeriMatcher {
             (".*:FDCAN:fdcan1_v1_[01].*", ("can", "fdcan_v1", "FDCAN")),
             ("STM32H7.*:FDCANRAM.*", ("fdcanram", "h7", "FDCANRAM")),
             (".*:FDCANRAM.*", ("fdcanram", "v1", "FDCANRAM")),
-            // # stm32F4 CRC peripheral
-            // # ("STM32F4*:CRC:CRC:crc_f4")
-            // # v1: F1, F2, F4, L1
-            // # v2, adds INIT reg: F0
-            // # v3, adds POL reg: F3, F7, G0, G4, H7, L0, L4, L5, WB, WL
-            (".*:CRC:integtest1_v1_0", ("crc", "v1", "CRC")),
-            ("STM32L[04].*:CRC:integtest1_v2_0", ("crc", "v3", "CRC")),
-            (".*:CRC:integtest1_v2_0", ("crc", "v2", "CRC")),
-            (".*:CRC:integtest1_v2_2", ("crc", "v3", "CRC")),
+            ("STM32F[124].*:CRC:.*", ("crc", "v1", "CRC")),
+            ("STM32L1.*:CRC:.*", ("crc", "v1", "CRC")),
+            ("STM32F0.*:CRC:.*", ("crc", "v2", "CRC")),
+            ("STM32F[37].*:CRC:.*", ("crc", "v3", "CRC")),
+            ("STM32G[04].*:CRC:.*", ("crc", "v3", "CRC")),
+            ("STM32H[57].*:CRC:.*", ("crc", "v3", "CRC")),
+            ("STM32L[045].*:CRC:.*", ("crc", "v3", "CRC")),
+            ("STM32W[BL].*:CRC:.*", ("crc", "v3", "CRC")),
+            ("STM32C[0].*:CRC:.*", ("crc", "v3", "CRC")),
+            ("STM32U[5].*:CRC:.*", ("crc", "v3", "CRC")),
             (".*:LCD:lcdc1_v1.0.*", ("lcd", "v1", "LCD")),
             (".*:LCD:lcdc1_v1.2.*", ("lcd", "v2", "LCD")),
             (".*:LCD:lcdc1_v1.3.*", ("lcd", "v2", "LCD")),
@@ -500,7 +503,11 @@ impl PeriMatcher {
                 ("octospi", "v1", "OCTOSPI"),
             ),
             (
-                "STM32U5.*:OCTOSPI[12]:OCTOSPI:octospi1_v3_0.*",
+                "STM32U5[34].*:OCTOSPI[12]:OCTOSPI:octospi_v1_0L5.*",
+                ("octospi", "v1", "OCTOSPI"),
+            ),
+            (
+                "STM32U5[AFG789].*:OCTOSPI[12]:OCTOSPI:octospi1_v3_0.*",
                 ("octospi", "v1", "OCTOSPI"),
             ),
             (
@@ -522,6 +529,13 @@ impl PeriMatcher {
             ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")),
             ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")),
             ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")),
+            (".*:HASH:hash1_v1_0", ("hash", "v1", "HASH")),
+            (".*:HASH:hash1_v2_0", ("hash", "v2", "HASH")),
+            (".*:HASH:hash1_v2_2", ("hash", "v2", "HASH")),
+            (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")),
+            (".*:CRYP:cryp1_v1_0.*", ("cryp", "v1", "CRYP")),
+            (".*:CRYP:cryp1_v2_0.*", ("cryp", "v2", "CRYP")),
+            (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")),
             ("STM32G0.*1.*:.*:COMP:.*", ("comp", "v1", "COMP")),
             ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")),
         ];
diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs
index 50e4702..d3927a5 100644
--- a/stm32-data-gen/src/header.rs
+++ b/stm32-data-gen/src/header.rs
@@ -162,6 +162,14 @@ impl Defines {
             ("DBGMCU", &["DBGMCU_BASE", "DBG_BASE"]),
             ("QUADSPI", &["QUADSPI_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]),
             ("QUADSPI1", &["QUADSPI1_BASE", "QSPI_R", "QSPI_R_BASE", "QSPI_REG_BASE"]),
+            (
+                "OCTOSPI",
+                &["OSPI_R", "OCTOSPI_R_BASE", "OCTOSPI_R_BASE_NS", "OCTOSPI_REG_BASE"],
+            ),
+            (
+                "OCTOSPI1",
+                &["OSPI_R", "OCTOSPI1_R_BASE", "OCTOSPI1_R_BASE_NS", "OCTOSPI1_REG_BASE"],
+            ),
             ("FLASH", &["FLASH_R_BASE", "FLASH_REG_BASE"]),
             (
                 "ADC_COMMON",
diff --git a/transforms/SAI.yaml b/transforms/SAI.yaml
index 2f49573..93c4d1c 100644
--- a/transforms/SAI.yaml
+++ b/transforms/SAI.yaml
@@ -1,3 +1,3 @@
 transforms:
   - !DeleteEnums
-    from: ^(AFSDET|AFSDET|FREQ|LFSDET|MUTEDET|OVRUDR|FFLUSH)$
+    from: ^(C?AFSDET(IE)?|CCNRDY|CNRDYIE|COVRUDR|CWCKCFG|DMAEN|FFLUSH|FREQ(IE)?|C?LFSDET(IE)?|MUTE|C?MUTEDET(IE)?|OVRUDR(IE)?|SAIEN|WCKCFGIE)$
\ No newline at end of file