diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml
index b25f9ef..6996619 100644
--- a/data/registers/rcc_u5.yaml
+++ b/data/registers/rcc_u5.yaml
@@ -1293,12 +1293,10 @@ fieldset/BDCR:
       description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."
       bit_offset: 1
       bit_size: 1
-      enum: LSERDY
     - name: LSEBYP
       description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)."
       bit_offset: 2
       bit_size: 1
-      enum: LSEBYP
     - name: LSEDRV
       description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode."
       bit_offset: 3
@@ -1312,7 +1310,6 @@ fieldset/BDCR:
       description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)."
       bit_offset: 6
       bit_size: 1
-      enum: LSECSSD
     - name: LSESYSEN
       description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE."
       bit_offset: 7
@@ -1326,7 +1323,6 @@ fieldset/BDCR:
       description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."
       bit_offset: 11
       bit_size: 1
-      enum: LSESYSRDY
     - name: LSEGFON
       description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)"
       bit_offset: 12
@@ -1356,7 +1352,6 @@ fieldset/BDCR:
       description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."
       bit_offset: 27
       bit_size: 1
-      enum: LSIRDY
     - name: LSIPREDIV
       description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC."
       bit_offset: 28
@@ -1661,32 +1656,26 @@ fieldset/CIER:
       description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization."
       bit_offset: 0
       bit_size: 1
-      enum: LSIRDYIE
     - name: LSERDYIE
       description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization."
       bit_offset: 1
       bit_size: 1
-      enum: LSERDYIE
     - name: MSISRDYIE
       description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization."
       bit_offset: 2
       bit_size: 1
-      enum: MSISRDYIE
     - name: HSIRDYIE
       description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization."
       bit_offset: 3
       bit_size: 1
-      enum: HSIRDYIE
     - name: HSERDYIE
       description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization."
       bit_offset: 4
       bit_size: 1
-      enum: HSERDYIE
     - name: HSI48RDYIE
       description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."
       bit_offset: 5
       bit_size: 1
-      enum: HSIRDYIE
     - name: PLLRDYIE
       description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock."
       bit_offset: 6
@@ -1694,17 +1683,14 @@ fieldset/CIER:
       array:
         len: 3
         stride: 1
-      enum: PLLRDYIE
     - name: MSIKRDYIE
       description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization."
       bit_offset: 11
       bit_size: 1
-      enum: MSIKRDYIE
     - name: SHSIRDYIE
       description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization."
       bit_offset: 12
       bit_size: 1
-      enum: SHSIRDYIE
 fieldset/CIFR:
   description: "RCC clock interrupt flag register "
   fields:
@@ -1712,32 +1698,26 @@ fieldset/CIFR:
       description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit."
       bit_offset: 0
       bit_size: 1
-      enum: LSIRDYF
     - name: LSERDYF
       description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit."
       bit_offset: 1
       bit_size: 1
-      enum: LSERDYF
     - name: MSISRDYF
       description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit."
       bit_offset: 2
       bit_size: 1
-      enum: MSISRDYF
     - name: HSIRDYF
       description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit."
       bit_offset: 3
       bit_size: 1
-      enum: HSIRDYF
     - name: HSERDYF
       description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit."
       bit_offset: 4
       bit_size: 1
-      enum: HSERDYF
     - name: HSI48RDYF
       description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit."
       bit_offset: 5
       bit_size: 1
-      enum: HSIRDYF
     - name: PLLRDYF
       description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit."
       bit_offset: 6
@@ -1745,22 +1725,18 @@ fieldset/CIFR:
       array:
         len: 3
         stride: 1
-      enum: PLLRDYF
     - name: CSSF
       description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit."
       bit_offset: 10
       bit_size: 1
-      enum: CSSF
     - name: MSIKRDYF
       description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit."
       bit_offset: 11
       bit_size: 1
-      enum: MSIKRDYF
     - name: SHSIRDYF
       description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit."
       bit_offset: 12
       bit_size: 1
-      enum: SHSIRDYF
 fieldset/CR:
   description: "RCC clock control register "
   fields:
@@ -1788,7 +1764,6 @@ fieldset/CR:
       description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles."
       bit_offset: 5
       bit_size: 1
-      enum: MSIKRDY
     - name: MSIPLLSEL
       description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs."
       bit_offset: 6
@@ -1827,7 +1802,6 @@ fieldset/CR:
       description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles."
       bit_offset: 15
       bit_size: 1
-      enum: SHSIRDY
     - name: HSEON
       description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock."
       bit_offset: 16
@@ -1840,7 +1814,6 @@ fieldset/CR:
       description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled."
       bit_offset: 18
       bit_size: 1
-      enum: HSEBYP
     - name: CSSON
       description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset."
       bit_offset: 19
@@ -1878,17 +1851,16 @@ fieldset/CSR:
       description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency."
       bit_offset: 8
       bit_size: 4
-      enum: MSIKSRANGE
+      enum: MSIXSRANGE
     - name: MSISSRANGE
       description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency."
       bit_offset: 12
       bit_size: 4
-      enum: MSISSRANGE
+      enum: MSIXSRANGE
     - name: RMVF
       description: "Remove reset flag\r Set by software to clear the reset flags."
       bit_offset: 23
       bit_size: 1
-      enum: RMVF
     - name: OBLRSTF
       description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit."
       bit_offset: 25
@@ -2036,12 +2008,10 @@ fieldset/PLL1DIVR:
       description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..."
       bit_offset: 9
       bit_size: 7
-      enum: PLLP
     - name: PLLQ
       description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
       bit_offset: 16
       bit_size: 7
-      enum: PLLQ
     - name: PLLR
       description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
       bit_offset: 24
@@ -2098,12 +2068,10 @@ fieldset/PLL2DIVR:
       description: "PLL2 DIVP division factor\r Set and reset by software to control the frequency of the pll2_p_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..."
       bit_offset: 9
       bit_size: 7
-      enum: PLLP
     - name: PLLQ
       description: "PLL2 DIVQ division factor\r Set and reset by software to control the frequency of the pll2_q_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..."
       bit_offset: 16
       bit_size: 7
-      enum: PLLQ
     - name: PLLR
       description: "PLL2 DIVR division factor\r Set and reset by software to control the frequency of the pll2_r_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..."
       bit_offset: 24
@@ -2163,12 +2131,10 @@ fieldset/PLL3DIVR:
       description: "PLL3 DIVP division factor\r Set and reset by software to control the frequency of the pll3_p_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..."
       bit_offset: 9
       bit_size: 7
-      enum: PLLP
     - name: PLLQ
       description: "PLL3 DIVQ division factor\r Set and reset by software to control the frequency of the pll3_q_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..."
       bit_offset: 16
       bit_size: 7
-      enum: PLLQ
     - name: PLLR
       description: "PLL3 DIVR division factor\r Set and reset by software to control the frequency of the pll3_r_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..."
       bit_offset: 24
@@ -2187,12 +2153,12 @@ fieldset/PRIVCFGR:
       description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access."
       bit_offset: 0
       bit_size: 1
-      enum: SPRIV
+      enum: PRIV
     - name: NSPRIV
       description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure."
       bit_offset: 1
       bit_size: 1
-      enum: NSPRIV
+      enum: PRIV
 fieldset/SECCFGR:
   description: "RCC secure configuration register "
   fields:
@@ -2360,34 +2326,25 @@ enum/ADFSEL:
     - name: MSIK
       description: MSIK clock selected
       value: 4
-enum/CSSF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock security interrupt caused by HSE clock failure
-      value: 0
-    - name: B_0x1
-      description: Clock security interrupt caused by HSE clock failure
-      value: 1
 enum/DACSEL:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: LSE
       description: LSE selected
       value: 0
-    - name: B_0x1
+    - name: LSI
       description: LSI selected
       value: 1
 enum/FDCANSEL:
   bit_size: 2
   variants:
-    - name: B_0x0
+    - name: HSE
       description: "HSE clock selected "
       value: 0
-    - name: B_0x1
+    - name: PLL1_Q
       description: PLL1 Q (pll1_q_ck) selected
       value: 1
-    - name: B_0x2
+    - name: PLL2_P
       description: PLL2 P (pll2_p_ck) selected
       value: 2
 enum/HPRE:
@@ -2420,103 +2377,58 @@ enum/HPRE:
     - name: DIV512
       description: SYSCLK divided by 512
       value: 15
-enum/HSEBYP:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: HSE crystal oscillator not bypassed
-      value: 0
-    - name: B_0x1
-      description: HSE crystal oscillator bypassed with external clock
-      value: 1
 enum/HSEEXT:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: ANALOG
       description: external HSE clock analog mode
       value: 0
-    - name: B_0x1
+    - name: DIGITAL
       description: external HSE clock digital mode (through I/O Schmitt trigger)
       value: 1
-enum/HSERDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the HSE oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the HSE oscillator
-      value: 1
-enum/HSERDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: HSE ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: HSE ready interrupt enabled
-      value: 1
-enum/HSIRDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the HSI16 oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the HSI16 oscillator
-      value: 1
-enum/HSIRDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: HSI16 ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: HSI16 ready interrupt enabled
-      value: 1
 enum/ICLKSEL:
   bit_size: 2
   variants:
-    - name: B_0x0
+    - name: HSI48
       description: HSI48 clock selected
       value: 0
-    - name: B_0x1
+    - name: PLL2_Q
       description: PLL2 Q (pll2_q_ck) selected
       value: 1
-    - name: B_0x2
+    - name: PLL1_Q
       description: PLL1 Q (pll1_q_ck) selected
       value: 2
-    - name: B_0x3
+    - name: MSIK
       description: MSIK clock selected
       value: 3
 enum/ICSEL:
   bit_size: 2
   variants:
-    - name: B_0x0
+    - name: PCLK1
       description: PCLK1 selected
       value: 0
-    - name: B_0x1
+    - name: SYSCLK
       description: SYSCLK selected
       value: 1
-    - name: B_0x2
+    - name: HSI16
       description: HSI16 selected
       value: 2
-    - name: B_0x3
+    - name: MSIK
       description: MSIK selected
       value: 3
 enum/LPTIMSEL:
   bit_size: 2
   variants:
-    - name: B_0x0
+    - name: PCLK1
       description: PCLK1 selected
       value: 0
-    - name: B_0x1
+    - name: LSI
       description: LSI selected
       value: 1
-    - name: B_0x2
+    - name: HSI16
       description: HSI16 selected
       value: 2
-    - name: B_0x3
+    - name: LSE
       description: LSE selected
       value: 3
 enum/LPUARTSEL:
@@ -2546,187 +2458,106 @@ enum/LSCOSEL:
     - name: LSE
       description: LSE clock selected
       value: 1
-enum/LSEBYP:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: LSE oscillator not bypassed
-      value: 0
-    - name: B_0x1
-      description: LSE oscillator bypassed
-      value: 1
-enum/LSECSSD:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No failure detected on LSE
-      value: 0
-    - name: B_0x1
-      description: Failure detected on LSE
-      value: 1
 enum/LSEDRV:
   bit_size: 2
   variants:
-    - name: B_0x0
+    - name: LOW
       description: "'Xtal mode lower driving capability"
       value: 0
-    - name: B_0x1
+    - name: MEDIUM_LOW
       description: "'Xtal mode medium-low driving capability"
       value: 1
-    - name: B_0x2
+    - name: MEDIUM_HIGH
       description: "'Xtal mode medium-high driving capability"
       value: 2
-    - name: B_0x3
+    - name: HIGH
       description: "'Xtal mode higher driving capability "
       value: 3
-enum/LSERDY:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: LSE oscillator not ready
-      value: 0
-    - name: B_0x1
-      description: LSE oscillator ready
-      value: 1
-enum/LSERDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the LSE oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the LSE oscillator
-      value: 1
-enum/LSERDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: LSE ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: LSE ready interrupt enabled
-      value: 1
-enum/LSESYSRDY:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: LSESYS clock not ready
-      value: 0
-    - name: B_0x1
-      description: LSESYS clock ready
-      value: 1
 enum/LSIPREDIV:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: NONE
       description: LSI not divided
       value: 0
-    - name: B_0x1
+    - name: DIV_128
       description: LSI divided by 128
       value: 1
-enum/LSIRDY:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: LSI oscillator not ready
-      value: 0
-    - name: B_0x1
-      description: LSI oscillator ready
-      value: 1
-enum/LSIRDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the LSI oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the LSI oscillator
-      value: 1
-enum/LSIRDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: LSI ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: LSI ready interrupt enabled
-      value: 1
 enum/MCOPRE:
   bit_size: 3
   variants:
-    - name: B_0x0
+    - name: NONE
       description: MCO divided by 1
       value: 0
-    - name: B_0x1
+    - name: DIV2
       description: MCO divided by 2
       value: 1
-    - name: B_0x2
+    - name: DIV4
       description: MCO divided by 4
       value: 2
-    - name: B_0x3
+    - name: DIV8
       description: MCO divided by 8
       value: 3
-    - name: B_0x4
+    - name: DIV16
       description: MCO divided by 16
       value: 4
 enum/MCOSEL:
   bit_size: 4
   variants:
-    - name: B_0x0
+    - name: DISABLE
       description: "MCO output disabled, no clock on MCO"
       value: 0
-    - name: B_0x1
+    - name: SYSCLK
       description: SYSCLK system clock selected
       value: 1
-    - name: B_0x2
+    - name: MSIS
       description: MSIS clock selected
       value: 2
-    - name: B_0x3
+    - name: HSI16
       description: HSI16 clock selected
       value: 3
-    - name: B_0x4
+    - name: HSE
       description: HSE clock selected
       value: 4
-    - name: B_0x5
+    - name: PLL1_R
       description: Main PLL clock pll1_r_ck selected
       value: 5
-    - name: B_0x6
+    - name: LSI
       description: LSI clock selected
       value: 6
-    - name: B_0x7
+    - name: LSE
       description: LSE clock selected
       value: 7
-    - name: B_0x8
+    - name: HSI48
       description: Internal HSI48 clock selected
       value: 8
-    - name: B_0x9
+    - name: MSIK
       description: MSIK clock selected
       value: 9
 enum/MDFSEL:
   bit_size: 3
   variants:
-    - name: B_0x0
+    - name: HCLK
       description: HCLK selected
       value: 0
-    - name: B_0x1
+    - name: PLL1_P
       description: PLL1 P (pll1_p_ck) selected
       value: 1
-    - name: B_0x2
+    - name: PLL3_Q
       description: PLL3 Q (pll3_q_ck) selected
       value: 2
-    - name: B_0x3
+    - name: AUDIOCLK
       description: input pin AUDIOCLK selected
       value: 3
-    - name: B_0x4
+    - name: MSIK
       description: MSIK clock selected
       value: 4
 enum/MSIBIAS:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: CONTINUOUS
       description: MSI bias continuous mode (clock accuracy fast settling time)
       value: 0
-    - name: B_0x1
+    - name: SAMPLING
       description: MSI bias sampling mode (ultra-low-power mode)
       value: 1
 enum/MSIRANGE:
@@ -2780,49 +2611,22 @@ enum/MSIRANGE:
     - name: RANGE_100KHZ
       description: "range 15 around 100 kHz "
       value: 15
-enum/MSIKRDY:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: MSIK (MSI kernel) oscillator not ready
-      value: 0
-    - name: B_0x1
-      description: MSIK (MSI kernel) oscillator ready
-      value: 1
-enum/MSIKRDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the MSIK oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the MSIK oscillator
-      value: 1
-enum/MSIKRDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: MSIK ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: MSIK ready interrupt enabled
-      value: 1
-enum/MSIKSRANGE:
+enum/MSIXSRANGE:
   bit_size: 4
   variants:
-    - name: B_0x4
+    - name: RANGE_4MHZ
       description: "range 4 around 4M Hz (reset value) "
       value: 4
-    - name: B_0x5
+    - name: RANGE_2MHZ
       description: "range 5 around 2 MHz "
       value: 5
-    - name: B_0x6
+    - name: RANGE_1_5MHZ
       description: "range 6 around 1.5 MHz "
       value: 6
-    - name: B_0x7
+    - name: RANGE_1MHZ
       description: "range 7 around 1 MHz "
       value: 7
-    - name: B_0x8
+    - name: RANGE_3_072MHZ
       description: "range 8 around 3.072 MHz "
       value: 8
 enum/MSIPLLFAST:
@@ -2852,51 +2656,6 @@ enum/MSIRGSEL:
     - name: RCC_ICSCR1
       description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1"
       value: 1
-enum/MSISRDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the MSIS oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the MSIS oscillator
-      value: 1
-enum/MSISRDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: MSIS ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: MSIS ready interrupt enabled
-      value: 1
-enum/MSISSRANGE:
-  bit_size: 4
-  variants:
-    - name: B_0x4
-      description: "range 4 around 4M Hz (reset value) "
-      value: 4
-    - name: B_0x5
-      description: "range 5 around 2 MHz "
-      value: 5
-    - name: B_0x6
-      description: "range 6 around 1.5 MHz "
-      value: 6
-    - name: B_0x7
-      description: "range 7 around 1 MHz "
-      value: 7
-    - name: B_0x8
-      description: "range 8 around 3.072 MHz "
-      value: 8
-enum/NSPRIV:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access.
-      value: 0
-    - name: B_0x1
-      description: Read and write to RCC non-secure functions can be done by privileged access only.
-      value: 1
 enum/OCTOSPISEL:
   bit_size: 2
   variants:
@@ -2957,64 +2716,13 @@ enum/PLLMBOOST:
     - name: DIV16
       description: division by 16
       value: 8
-enum/PLLP:
-  bit_size: 7
-  variants:
-    - name: B_0x0
-      description: pll3_p_ck = vco3_ck
-      value: 0
-    - name: B_0x1
-      description: pll3_p_ck = vco3_ck / 2 (default after reset)
-      value: 1
-    - name: B_0x2
-      description: pll3_p_ck = vco3_ck / 3
-      value: 2
-    - name: B_0x3
-      description: pll3_p_ck = vco3_ck / 4
-      value: 3
-    - name: B_0x7F
-      description: pll3_p_ck = vco3_ck / 128
-      value: 127
-enum/PLLQ:
-  bit_size: 7
-  variants:
-    - name: VCO_CK
-      description: "pll3_q_ck = vco3_ck "
-      value: 0
-    - name: VCO_CK_DIV2
-      description: pll3_q_ck = vco3_ck / 2 (default after reset)
-      value: 1
-    - name: VCO_CK_DIV3
-      description: pll3_q_ck = vco3_ck / 3
-      value: 2
-    - name: VCO_CK_DIV4
-      description: pll3_q_ck = vco3_ck / 4
-      value: 3
-    - name: VCO_CK_DIV128
-      description: pll3_q_ck = vco3_ck / 128
-      value: 127
-enum/PLLRDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by PLL1 lock
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by PLL1 lock
-      value: 1
-enum/PLLRDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: PLL1 lock interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: PLL1 lock interrupt enabled
-      value: 1
 enum/PLLRGE:
   bit_size: 2
   variants:
-    - name: B_0x3
+    - name: FREQ_4TO8MHZ
+      description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
+      value: 0
+    - name: FREQ_8TO16MHZ
       description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz
       value: 3
 enum/PLLSRC:
@@ -3050,15 +2758,6 @@ enum/PPRE:
     - name: DIV16
       description: HCLK divided by 16
       value: 7
-enum/RMVF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No effect
-      value: 0
-    - name: B_0x1
-      description: Clear the reset flags
-      value: 1
 enum/RNGSEL:
   bit_size: 2
   variants:
@@ -3098,13 +2797,13 @@ enum/SAESSEL:
 enum/SAISEL:
   bit_size: 3
   variants:
-    - name: PLL2
+    - name: PLL2_P
       description: PLL2 P (pll2_p_ck) selected
       value: 0
-    - name: PLL3
+    - name: PLL3_P
       description: PLL3 P (pll3_p_ck) selected
       value: 1
-    - name: PLL1
+    - name: PLL1_P
       description: PLL1 P (pll1_p_ck) selected
       value: 2
     - name: AUDIOCLK
@@ -3116,39 +2815,12 @@ enum/SAISEL:
 enum/SDMMCSEL:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: ICLK
       description: ICLK clock selected
       value: 0
-    - name: B_0x1
+    - name: PLL1_P
       description: "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) "
       value: 1
-enum/SHSIRDY:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: SHSI oscillator not ready
-      value: 0
-    - name: B_0x1
-      description: "SHSI oscillator ready "
-      value: 1
-enum/SHSIRDYF:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: No clock ready interrupt caused by the SHSI oscillator
-      value: 0
-    - name: B_0x1
-      description: Clock ready interrupt caused by the SHSI oscillator
-      value: 1
-enum/SHSIRDYIE:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: SHSI ready interrupt disabled
-      value: 0
-    - name: B_0x1
-      description: SHSI ready interrupt enabled
-      value: 1
 enum/SPISEL:
   bit_size: 2
   variants:
@@ -3164,31 +2836,22 @@ enum/SPISEL:
     - name: MSIK
       description: MSIK selected
       value: 3
-enum/SPRIV:
-  bit_size: 1
-  variants:
-    - name: B_0x0
-      description: Read and write to RCC secure functions can be done by privileged or unprivileged access.
-      value: 0
-    - name: B_0x1
-      description: Read and write to RCC secure functions can be done by privileged access only.
-      value: 1
 enum/STOPKERWUCK:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: MSIK
       description: MSIK oscillator automatically enabled when exiting Stop mode
       value: 0
-    - name: B_0x1
+    - name: HSI16
       description: HSI16 oscillator automatically enabled when exiting Stop mode
       value: 1
 enum/STOPWUCK:
   bit_size: 1
   variants:
-    - name: B_0x0
+    - name: MSIS
       description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock
       value: 0
-    - name: B_0x1
+    - name: HSI16
       description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock
       value: 1
 enum/SW:
@@ -3221,16 +2884,19 @@ enum/SYSTICKSEL:
 enum/TIMICSEL:
   bit_size: 3
   variants:
-    - name: B_0x4
+    - name: NONE
+      description: "No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"
+      value: 0
+    - name: HSI256_MSIS1024_MSIS4
       description: "HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"
       value: 4
-    - name: B_0x5
+    - name: HSI256_MSIS1024_MSIK4
       description: "HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"
       value: 5
-    - name: B_0x6
+    - name: HSI256_MSIK1024_MSIS4
       description: "HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"
       value: 6
-    - name: B_0x7
+    - name: HSI256_MSIK1024_MSIK4
       description: "HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"
       value: 7
 enum/UARTSEL:
@@ -3272,3 +2938,12 @@ enum/SECURITY:
     - name: SECURE
       description: secure
       value: 1
+enum/PRIV:
+  bit_size: 1
+  variants:
+    - name: UNPRIVILEGED
+      description: Read and write to secure functions can be done by privileged or unprivileged access.
+      value: 0
+    - name: PRIVILEGED
+      description: Read and write to secure functions can be done by privileged access only.
+      value: 1