diff --git a/data/registers/eth_v2.yaml b/data/registers/eth_v2.yaml new file mode 100644 index 0000000..89fb46a --- /dev/null +++ b/data/registers/eth_v2.yaml @@ -0,0 +1,2614 @@ +--- +block/ETH: + description: "Ethernet Peripheral" + items: + - name: ETHERNET_MAC + description: "Ethernet: media access control (MAC)" + byte_offset: 0 + block: ETHERNET_MAC + - name: ETHERNET_MTL + description: "Ethernet: MTL mode register (MTL)" + byte_offset: 3072 + block: ETHERNET_MTL + - name: ETHERNET_DMA + description: "Ethernet: DMA mode register (DMA)" + byte_offset: 4096 + block: ETHERNET_DMA +block/ETHERNET_MAC: + description: "Ethernet: media access control (MAC)" + items: + - name: MACCR + description: Operating mode configuration register + byte_offset: 0 + fieldset: MACCR + - name: MACECR + description: Extended operating mode configuration register + byte_offset: 4 + fieldset: MACECR + - name: MACPFR + description: Packet filtering control register + byte_offset: 8 + fieldset: MACPFR + - name: MACWTR + description: Watchdog timeout register + byte_offset: 12 + fieldset: MACWTR + - name: MACHT0R + description: Hash Table 0 register + byte_offset: 16 + fieldset: MACHT0R + - name: MACHT1R + description: Hash Table 1 register + byte_offset: 20 + fieldset: MACHT1R + - name: MACVTR + description: VLAN tag register + byte_offset: 80 + fieldset: MACVTR + - name: MACVHTR + description: VLAN Hash table register + byte_offset: 88 + fieldset: MACVHTR + - name: MACVIR + description: VLAN inclusion register + byte_offset: 96 + fieldset: MACVIR + - name: MACIVIR + description: Inner VLAN inclusion register + byte_offset: 100 + fieldset: MACIVIR + - name: MACQTxFCR + description: Tx Queue flow control register + byte_offset: 112 + fieldset: MACQTxFCR + - name: MACRxFCR + description: Rx flow control register + byte_offset: 144 + fieldset: MACRxFCR + - name: MACISR + description: Interrupt status register + byte_offset: 176 + access: Read + fieldset: MACISR + - name: MACIER + description: Interrupt enable register + byte_offset: 180 + fieldset: MACIER + - name: MACRxTxSR + description: Rx Tx status register + byte_offset: 184 + access: Read + fieldset: MACRxTxSR + - name: MACPCSR + description: PMT control status register + byte_offset: 192 + fieldset: MACPCSR + - name: MACRWKPFR + description: Remove wakeup packet filter register + byte_offset: 196 + fieldset: MACRWKPFR + - name: MACLCSR + description: LPI control status register + byte_offset: 208 + fieldset: MACLCSR + - name: MACLTCR + description: LPI timers control register + byte_offset: 212 + fieldset: MACLTCR + - name: MACLETR + description: LPI entry timer register + byte_offset: 216 + fieldset: MACLETR + - name: MAC1USTCR + description: 1-microsecond-tick counter register + byte_offset: 220 + fieldset: MAC1USTCR + - name: MACVR + description: Version register + byte_offset: 272 + access: Read + fieldset: MACVR + - name: MACDR + description: Debug register + byte_offset: 276 + access: Read + fieldset: MACDR + - name: MACHWF1R + description: HW feature 1 register + byte_offset: 288 + access: Read + fieldset: MACHWF1R + - name: MACHWF2R + description: HW feature 2 register + byte_offset: 292 + access: Read + fieldset: MACHWF2R + - name: MACMDIOAR + description: MDIO address register + byte_offset: 512 + fieldset: MACMDIOAR + - name: MACMDIODR + description: MDIO data register + byte_offset: 516 + fieldset: MACMDIODR + - name: MACA0HR + description: Address 0 high register + byte_offset: 768 + fieldset: MACA0HR + - name: MACA0LR + description: Address 0 low register + byte_offset: 772 + fieldset: MACA0LR + - name: MACA1HR + description: Address 1 high register + byte_offset: 776 + fieldset: MACA1HR + - name: MACA1LR + description: Address 1 low register + byte_offset: 780 + fieldset: MACA1LR + - name: MACA2HR + description: Address 2 high register + byte_offset: 784 + fieldset: MACA2HR + - name: MACA2LR + description: Address 2 low register + byte_offset: 788 + fieldset: MACA2LR + - name: MACA3HR + description: Address 3 high register + byte_offset: 792 + fieldset: MACA3HR + - name: MACA3LR + description: Address 3 low register + byte_offset: 796 + fieldset: MACA3LR + - name: MMC_CONTROL + description: MMC control register + byte_offset: 1792 + fieldset: MMC_CONTROL + - name: MMC_RX_INTERRUPT + description: MMC Rx interrupt register + byte_offset: 1796 + access: Read + fieldset: MMC_RX_INTERRUPT + - name: MMC_TX_INTERRUPT + description: MMC Tx interrupt register + byte_offset: 1800 + access: Read + fieldset: MMC_TX_INTERRUPT + - name: MMC_RX_INTERRUPT_MASK + description: MMC Rx interrupt mask register + byte_offset: 1804 + fieldset: MMC_RX_INTERRUPT_MASK + - name: MMC_TX_INTERRUPT_MASK + description: MMC Tx interrupt mask register + byte_offset: 1808 + fieldset: MMC_TX_INTERRUPT_MASK + - name: TX_SINGLE_COLLISION_GOOD_PACKETS + description: Tx single collision good packets register + byte_offset: 1868 + access: Read + fieldset: TX_SINGLE_COLLISION_GOOD_PACKETS + - name: TX_MULTIPLE_COLLISION_GOOD_PACKETS + description: Tx multiple collision good packets register + byte_offset: 1872 + access: Read + fieldset: TX_MULTIPLE_COLLISION_GOOD_PACKETS + - name: TX_PACKET_COUNT_GOOD + description: Tx packet count good register + byte_offset: 1896 + access: Read + fieldset: TX_PACKET_COUNT_GOOD + - name: RX_CRC_ERROR_PACKETS + description: Rx CRC error packets register + byte_offset: 1940 + access: Read + fieldset: RX_CRC_ERROR_PACKETS + - name: RX_ALIGNMENT_ERROR_PACKETS + description: Rx alignment error packets register + byte_offset: 1944 + access: Read + fieldset: RX_ALIGNMENT_ERROR_PACKETS + - name: RX_UNICAST_PACKETS_GOOD + description: Rx unicast packets good register + byte_offset: 1988 + access: Read + fieldset: RX_UNICAST_PACKETS_GOOD + - name: TX_LPI_USEC_CNTR + description: Tx LPI microsecond timer register + byte_offset: 2028 + access: Read + fieldset: TX_LPI_USEC_CNTR + - name: TX_LPI_TRAN_CNTR + description: Tx LPI transition counter register + byte_offset: 2032 + access: Read + fieldset: TX_LPI_TRAN_CNTR + - name: RX_LPI_USEC_CNTR + description: Rx LPI microsecond counter register + byte_offset: 2036 + access: Read + fieldset: RX_LPI_USEC_CNTR + - name: RX_LPI_TRAN_CNTR + description: Rx LPI transition counter register + byte_offset: 2040 + access: Read + fieldset: RX_LPI_TRAN_CNTR + - name: MACL3L4C0R + description: L3 and L4 control 0 register + byte_offset: 2304 + fieldset: MACL3L4C0R + - name: MACL4A0R + description: Layer4 address filter 0 register + byte_offset: 2308 + fieldset: MACL4A0R + - name: MACL3A00R + description: MACL3A00R + byte_offset: 2320 + fieldset: MACL3A00R + - name: MACL3A10R + description: Layer3 address 1 filter 0 register + byte_offset: 2324 + fieldset: MACL3A10R + - name: MACL3A20 + description: Layer3 Address 2 filter 0 register + byte_offset: 2328 + fieldset: MACL3A20 + - name: MACL3A30 + description: Layer3 Address 3 filter 0 register + byte_offset: 2332 + fieldset: MACL3A30 + - name: MACL3L4C1R + description: L3 and L4 control 1 register + byte_offset: 2352 + fieldset: MACL3L4C1R + - name: MACL4A1R + description: Layer 4 address filter 1 register + byte_offset: 2356 + fieldset: MACL4A1R + - name: MACL3A01R + description: Layer3 address 0 filter 1 Register + byte_offset: 2368 + fieldset: MACL3A01R + - name: MACL3A11R + description: Layer3 address 1 filter 1 register + byte_offset: 2372 + fieldset: MACL3A11R + - name: MACL3A21R + description: Layer3 address 2 filter 1 Register + byte_offset: 2376 + fieldset: MACL3A21R + - name: MACL3A31R + description: Layer3 address 3 filter 1 register + byte_offset: 2380 + fieldset: MACL3A31R + - name: MACARPAR + description: ARP address register + byte_offset: 2784 + fieldset: MACARPAR + - name: MACTSCR + description: Timestamp control Register + byte_offset: 2816 + fieldset: MACTSCR + - name: MACSSIR + description: Sub-second increment register + byte_offset: 2820 + fieldset: MACSSIR + - name: MACSTSR + description: System time seconds register + byte_offset: 2824 + access: Read + fieldset: MACSTSR + - name: MACSTNR + description: System time nanoseconds register + byte_offset: 2828 + access: Read + fieldset: MACSTNR + - name: MACSTSUR + description: System time seconds update register + byte_offset: 2832 + fieldset: MACSTSUR + - name: MACSTNUR + description: System time nanoseconds update register + byte_offset: 2836 + fieldset: MACSTNUR + - name: MACTSAR + description: Timestamp addend register + byte_offset: 2840 + fieldset: MACTSAR + - name: MACTSSR + description: Timestamp status register + byte_offset: 2848 + access: Read + fieldset: MACTSSR + - name: MACTxTSSNR + description: Tx timestamp status nanoseconds register + byte_offset: 2864 + access: Read + fieldset: MACTxTSSNR + - name: MACTxTSSSR + description: Tx timestamp status seconds register + byte_offset: 2868 + access: Read + fieldset: MACTxTSSSR + - name: MACACR + description: Auxiliary control register + byte_offset: 2880 + fieldset: MACACR + - name: MACATSNR + description: Auxiliary timestamp nanoseconds register + byte_offset: 2888 + access: Read + fieldset: MACATSNR + - name: MACATSSR + description: Auxiliary timestamp seconds register + byte_offset: 2892 + access: Read + fieldset: MACATSSR + - name: MACTSIACR + description: Timestamp Ingress asymmetric correction register + byte_offset: 2896 + fieldset: MACTSIACR + - name: MACTSEACR + description: Timestamp Egress asymmetric correction register + byte_offset: 2900 + fieldset: MACTSEACR + - name: MACTSICNR + description: Timestamp Ingress correction nanosecond register + byte_offset: 2904 + fieldset: MACTSICNR + - name: MACTSECNR + description: Timestamp Egress correction nanosecond register + byte_offset: 2908 + fieldset: MACTSECNR + - name: MACPPSCR + description: PPS control register + byte_offset: 2928 + fieldset: MACPPSCR + - name: MACPPSTTSR + description: PPS target time seconds register + byte_offset: 2944 + fieldset: MACPPSTTSR + - name: MACPPSTTNR + description: PPS target time nanoseconds register + byte_offset: 2948 + fieldset: MACPPSTTNR + - name: MACPPSIR + description: PPS interval register + byte_offset: 2952 + fieldset: MACPPSIR + - name: MACPPSWR + description: PPS width register + byte_offset: 2956 + fieldset: MACPPSWR + - name: MACPOCR + description: PTP Offload control register + byte_offset: 3008 + fieldset: MACPOCR + - name: MACSPI0R + description: PTP Source Port Identity 0 Register + byte_offset: 3012 + fieldset: MACSPI0R + - name: MACSPI1R + description: PTP Source port identity 1 register + byte_offset: 3016 + fieldset: MACSPI1R + - name: MACSPI2R + description: PTP Source port identity 2 register + byte_offset: 3020 + fieldset: MACSPI2R + - name: MACLMIR + description: Log message interval register + byte_offset: 3024 + fieldset: MACLMIR +fieldset/MAC1USTCR: + description: 1-microsecond-tick counter register + fields: + - name: TIC_1US_CNTR + description: 1 µs tick Counter + bit_offset: 0 + bit_size: 12 +fieldset/MACA0HR: + description: Address 0 high register + fields: + - name: ADDRHI + description: "MAC Address0[47:32]" + bit_offset: 0 + bit_size: 16 + - name: AE + description: Address Enable + bit_offset: 31 + bit_size: 1 +fieldset/MACA0LR: + description: Address 0 low register + fields: + - name: ADDRLO + description: "MAC Address 0 [31:0]" + bit_offset: 0 + bit_size: 32 +fieldset/MACA1HR: + description: Address 1 high register + fields: + - name: ADDRHI + description: "MAC Address1 [47:32]" + bit_offset: 0 + bit_size: 16 + - name: MBC + description: Mask Byte Control + bit_offset: 24 + bit_size: 6 + - name: SA + description: Source Address + bit_offset: 30 + bit_size: 1 + - name: AE + description: Address Enable + bit_offset: 31 + bit_size: 1 +fieldset/MACA1LR: + description: Address 1 low register + fields: + - name: ADDRLO + description: "MAC Address 1 [31:0]" + bit_offset: 0 + bit_size: 32 +fieldset/MACA2HR: + description: Address 2 high register + fields: + - name: ADDRHI + description: "MAC Address2 [47:32]" + bit_offset: 0 + bit_size: 16 + - name: MBC + description: Mask Byte Control + bit_offset: 24 + bit_size: 6 + - name: SA + description: Source Address + bit_offset: 30 + bit_size: 1 + - name: AE + description: Address Enable + bit_offset: 31 + bit_size: 1 +fieldset/MACA2LR: + description: Address 2 low register + fields: + - name: ADDRLO + description: "MAC Address 2 [31:0]" + bit_offset: 0 + bit_size: 32 +fieldset/MACA3HR: + description: Address 3 high register + fields: + - name: ADDRHI + description: "MAC Address3 [47:32]" + bit_offset: 0 + bit_size: 16 + - name: MBC + description: Mask Byte Control + bit_offset: 24 + bit_size: 6 + - name: SA + description: Source Address + bit_offset: 30 + bit_size: 1 + - name: AE + description: Address Enable + bit_offset: 31 + bit_size: 1 +fieldset/MACA3LR: + description: Address 3 low register + fields: + - name: ADDRLO + description: "MAC Address 3 [31:0]" + bit_offset: 0 + bit_size: 32 +fieldset/MACACR: + description: Auxiliary control register + fields: + - name: ATSFC + description: Auxiliary Snapshot FIFO Clear + bit_offset: 0 + bit_size: 1 + - name: ATSEN0 + description: Auxiliary Snapshot 0 Enable + bit_offset: 4 + bit_size: 1 + - name: ATSEN1 + description: Auxiliary Snapshot 1 Enable + bit_offset: 5 + bit_size: 1 + - name: ATSEN2 + description: Auxiliary Snapshot 2 Enable + bit_offset: 6 + bit_size: 1 + - name: ATSEN3 + description: Auxiliary Snapshot 3 Enable + bit_offset: 7 + bit_size: 1 +fieldset/MACARPAR: + description: ARP address register + fields: + - name: ARPPA + description: ARP Protocol Address + bit_offset: 0 + bit_size: 32 +fieldset/MACATSNR: + description: Auxiliary timestamp nanoseconds register + fields: + - name: AUXTSLO + description: Auxiliary Timestamp + bit_offset: 0 + bit_size: 31 +fieldset/MACATSSR: + description: Auxiliary timestamp seconds register + fields: + - name: AUXTSHI + description: Auxiliary Timestamp + bit_offset: 0 + bit_size: 32 +fieldset/MACCR: + description: Operating mode configuration register + fields: + - name: RE + description: Receiver Enable + bit_offset: 0 + bit_size: 1 + - name: TE + description: Transmitter Enable + bit_offset: 1 + bit_size: 1 + - name: PRELEN + description: Preamble Length for Transmit Packets + bit_offset: 2 + bit_size: 2 + - name: DC + description: Deferral Check + bit_offset: 4 + bit_size: 1 + - name: BL + description: Back-Off Limit + bit_offset: 5 + bit_size: 2 + - name: DR + description: Disable Retry + bit_offset: 8 + bit_size: 1 + - name: DCRS + description: Disable Carrier Sense During Transmission + bit_offset: 9 + bit_size: 1 + - name: DO + description: Disable Receive Own + bit_offset: 10 + bit_size: 1 + - name: ECRSFD + description: Enable Carrier Sense Before Transmission in Full-Duplex Mode + bit_offset: 11 + bit_size: 1 + - name: LM + description: Loopback Mode + bit_offset: 12 + bit_size: 1 + - name: DM + description: Duplex Mode + bit_offset: 13 + bit_size: 1 + - name: FES + description: MAC Speed + bit_offset: 14 + bit_size: 1 + - name: JE + description: Jumbo Packet Enable + bit_offset: 16 + bit_size: 1 + - name: JD + description: Jabber Disable + bit_offset: 17 + bit_size: 1 + - name: WD + description: Watchdog Disable + bit_offset: 19 + bit_size: 1 + - name: ACS + description: Automatic Pad or CRC Stripping + bit_offset: 20 + bit_size: 1 + - name: CST + description: CRC stripping for Type packets + bit_offset: 21 + bit_size: 1 + - name: S2KP + description: IEEE 802.3as Support for 2K Packets + bit_offset: 22 + bit_size: 1 + - name: GPSLCE + description: Giant Packet Size Limit Control Enable + bit_offset: 23 + bit_size: 1 + - name: IPG + description: Inter-Packet Gap + bit_offset: 24 + bit_size: 3 + - name: IPC + description: Checksum Offload + bit_offset: 27 + bit_size: 1 + - name: SARC + description: Source Address Insertion or Replacement Control + bit_offset: 28 + bit_size: 3 + - name: ARPEN + description: ARP Offload Enable + bit_offset: 31 + bit_size: 1 +fieldset/MACDR: + description: Debug register + fields: + - name: RPESTS + description: MAC MII Receive Protocol Engine Status + bit_offset: 0 + bit_size: 1 + - name: RFCFCSTS + description: MAC Receive Packet Controller FIFO Status + bit_offset: 1 + bit_size: 2 + - name: TPESTS + description: MAC MII Transmit Protocol Engine Status + bit_offset: 16 + bit_size: 1 + - name: TFCSTS + description: MAC Transmit Packet Controller Status + bit_offset: 17 + bit_size: 2 +fieldset/MACECR: + description: Extended operating mode configuration register + fields: + - name: GPSL + description: Giant Packet Size Limit + bit_offset: 0 + bit_size: 14 + - name: DCRCC + description: Disable CRC Checking for Received Packets + bit_offset: 16 + bit_size: 1 + - name: SPEN + description: Slow Protocol Detection Enable + bit_offset: 17 + bit_size: 1 + - name: USP + description: Unicast Slow Protocol Packet Detect + bit_offset: 18 + bit_size: 1 + - name: EIPGEN + description: Extended Inter-Packet Gap Enable + bit_offset: 24 + bit_size: 1 + - name: EIPG + description: Extended Inter-Packet Gap + bit_offset: 25 + bit_size: 5 +fieldset/MACHT0R: + description: Hash Table 0 register + fields: + - name: HT31T0 + description: MAC Hash Table First 32 Bits + bit_offset: 0 + bit_size: 32 +fieldset/MACHT1R: + description: Hash Table 1 register + fields: + - name: HT63T32 + description: MAC Hash Table Second 32 Bits + bit_offset: 0 + bit_size: 32 +fieldset/MACHWF1R: + description: HW feature 1 register + fields: + - name: RXFIFOSIZE + description: MTL Receive FIFO Size + bit_offset: 0 + bit_size: 5 + - name: TXFIFOSIZE + description: MTL Transmit FIFO Size + bit_offset: 6 + bit_size: 5 + - name: OSTEN + description: One-Step Timestamping Enable + bit_offset: 11 + bit_size: 1 + - name: PTOEN + description: PTP Offload Enable + bit_offset: 12 + bit_size: 1 + - name: ADVTHWORD + description: IEEE 1588 High Word Register Enable + bit_offset: 13 + bit_size: 1 + - name: ADDR64 + description: Address width + bit_offset: 14 + bit_size: 2 + - name: DCBEN + description: DCB Feature Enable + bit_offset: 16 + bit_size: 1 + - name: SPHEN + description: Split Header Feature Enable + bit_offset: 17 + bit_size: 1 + - name: TSOEN + description: TCP Segmentation Offload Enable + bit_offset: 18 + bit_size: 1 + - name: DBGMEMA + description: DMA Debug Registers Enable + bit_offset: 19 + bit_size: 1 + - name: AVSEL + description: AV Feature Enable + bit_offset: 20 + bit_size: 1 + - name: HASHTBLSZ + description: Hash Table Size + bit_offset: 24 + bit_size: 2 + - name: L3L4FNUM + description: Total number of L3 or L4 Filters + bit_offset: 27 + bit_size: 4 +fieldset/MACHWF2R: + description: HW feature 2 register + fields: + - name: RXQCNT + description: Number of MTL Receive Queues + bit_offset: 0 + bit_size: 4 + - name: TXQCNT + description: Number of MTL Transmit Queues + bit_offset: 6 + bit_size: 4 + - name: RXCHCNT + description: Number of DMA Receive Channels + bit_offset: 12 + bit_size: 4 + - name: TXCHCNT + description: Number of DMA Transmit Channels + bit_offset: 18 + bit_size: 4 + - name: PPSOUTNUM + description: Number of PPS Outputs + bit_offset: 24 + bit_size: 3 + - name: AUXSNAPNUM + description: Number of Auxiliary Snapshot Inputs + bit_offset: 28 + bit_size: 3 +fieldset/MACIER: + description: Interrupt enable register + fields: + - name: PHYIE + description: PHY Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: PMTIE + description: PMT Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: LPIIE + description: LPI Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: TSIE + description: Timestamp Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: TXSTSIE + description: Transmit Status Interrupt Enable + bit_offset: 13 + bit_size: 1 + - name: RXSTSIE + description: Receive Status Interrupt Enable + bit_offset: 14 + bit_size: 1 +fieldset/MACISR: + description: Interrupt status register + fields: + - name: PHYIS + description: PHY Interrupt + bit_offset: 3 + bit_size: 1 + - name: PMTIS + description: PMT Interrupt Status + bit_offset: 4 + bit_size: 1 + - name: LPIIS + description: LPI Interrupt Status + bit_offset: 5 + bit_size: 1 + - name: MMCIS + description: MMC Interrupt Status + bit_offset: 8 + bit_size: 1 + - name: MMCRXIS + description: MMC Receive Interrupt Status + bit_offset: 9 + bit_size: 1 + - name: MMCTXIS + description: MMC Transmit Interrupt Status + bit_offset: 10 + bit_size: 1 + - name: TSIS + description: Timestamp Interrupt Status + bit_offset: 12 + bit_size: 1 + - name: TXSTSIS + description: Transmit Status Interrupt + bit_offset: 13 + bit_size: 1 + - name: RXSTSIS + description: Receive Status Interrupt + bit_offset: 14 + bit_size: 1 +fieldset/MACIVIR: + description: Inner VLAN inclusion register + fields: + - name: VLT + description: VLAN Tag for Transmit Packets + bit_offset: 0 + bit_size: 16 + - name: VLC + description: VLAN Tag Control in Transmit Packets + bit_offset: 16 + bit_size: 2 + - name: VLP + description: VLAN Priority Control + bit_offset: 18 + bit_size: 1 + - name: CSVL + description: C-VLAN or S-VLAN + bit_offset: 19 + bit_size: 1 + - name: VLTI + description: VLAN Tag Input + bit_offset: 20 + bit_size: 1 +fieldset/MACL3A00R: + description: MACL3A00R + fields: + - name: L3A00 + description: Layer 3 Address 0 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A01R: + description: Layer3 address 0 filter 1 Register + fields: + - name: L3A01 + description: Layer 3 Address 0 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A10R: + description: Layer3 address 1 filter 0 register + fields: + - name: L3A10 + description: Layer 3 Address 1 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A11R: + description: Layer3 address 1 filter 1 register + fields: + - name: L3A11 + description: Layer 3 Address 1 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A20: + description: Layer3 Address 2 filter 0 register + fields: + - name: L3A20 + description: Layer 3 Address 2 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A21R: + description: Layer3 address 2 filter 1 Register + fields: + - name: L3A21 + description: Layer 3 Address 2 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A30: + description: Layer3 Address 3 filter 0 register + fields: + - name: L3A30 + description: Layer 3 Address 3 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3A31R: + description: Layer3 address 3 filter 1 register + fields: + - name: L3A31 + description: Layer 3 Address 3 Field + bit_offset: 0 + bit_size: 32 +fieldset/MACL3L4C0R: + description: L3 and L4 control 0 register + fields: + - name: L3PEN0 + description: Layer 3 Protocol Enable + bit_offset: 0 + bit_size: 1 + - name: L3SAM0 + description: Layer 3 IP SA Match Enable + bit_offset: 2 + bit_size: 1 + - name: L3SAIM0 + description: Layer 3 IP SA Inverse Match Enable + bit_offset: 3 + bit_size: 1 + - name: L3DAM0 + description: Layer 3 IP DA Match Enable + bit_offset: 4 + bit_size: 1 + - name: L3DAIM0 + description: Layer 3 IP DA Inverse Match Enable + bit_offset: 5 + bit_size: 1 + - name: L3HSBM0 + description: Layer 3 IP SA Higher Bits Match + bit_offset: 6 + bit_size: 5 + - name: L3HDBM0 + description: Layer 3 IP DA Higher Bits Match + bit_offset: 11 + bit_size: 5 + - name: L4PEN0 + description: Layer 4 Protocol Enable + bit_offset: 16 + bit_size: 1 + - name: L4SPM0 + description: Layer 4 Source Port Match Enable + bit_offset: 18 + bit_size: 1 + - name: L4SPIM0 + description: Layer 4 Source Port Inverse Match Enable + bit_offset: 19 + bit_size: 1 + - name: L4DPM0 + description: Layer 4 Destination Port Match Enable + bit_offset: 20 + bit_size: 1 + - name: L4DPIM0 + description: Layer 4 Destination Port Inverse Match Enable + bit_offset: 21 + bit_size: 1 +fieldset/MACL3L4C1R: + description: L3 and L4 control 1 register + fields: + - name: L3PEN1 + description: Layer 3 Protocol Enable + bit_offset: 0 + bit_size: 1 + - name: L3SAM1 + description: Layer 3 IP SA Match Enable + bit_offset: 2 + bit_size: 1 + - name: L3SAIM1 + description: Layer 3 IP SA Inverse Match Enable + bit_offset: 3 + bit_size: 1 + - name: L3DAM1 + description: Layer 3 IP DA Match Enable + bit_offset: 4 + bit_size: 1 + - name: L3DAIM1 + description: Layer 3 IP DA Inverse Match Enable + bit_offset: 5 + bit_size: 1 + - name: L3HSBM1 + description: Layer 3 IP SA Higher Bits Match + bit_offset: 6 + bit_size: 5 + - name: L3HDBM1 + description: Layer 3 IP DA Higher Bits Match + bit_offset: 11 + bit_size: 5 + - name: L4PEN1 + description: Layer 4 Protocol Enable + bit_offset: 16 + bit_size: 1 + - name: L4SPM1 + description: Layer 4 Source Port Match Enable + bit_offset: 18 + bit_size: 1 + - name: L4SPIM1 + description: Layer 4 Source Port Inverse Match Enable + bit_offset: 19 + bit_size: 1 + - name: L4DPM1 + description: Layer 4 Destination Port Match Enable + bit_offset: 20 + bit_size: 1 + - name: L4DPIM1 + description: Layer 4 Destination Port Inverse Match Enable + bit_offset: 21 + bit_size: 1 +fieldset/MACL4A0R: + description: Layer4 address filter 0 register + fields: + - name: L4SP0 + description: Layer 4 Source Port Number Field + bit_offset: 0 + bit_size: 16 + - name: L4DP0 + description: Layer 4 Destination Port Number Field + bit_offset: 16 + bit_size: 16 +fieldset/MACL4A1R: + description: Layer 4 address filter 1 register + fields: + - name: L4SP1 + description: Layer 4 Source Port Number Field + bit_offset: 0 + bit_size: 16 + - name: L4DP1 + description: Layer 4 Destination Port Number Field + bit_offset: 16 + bit_size: 16 +fieldset/MACLCSR: + description: LPI control status register + fields: + - name: TLPIEN + description: Transmit LPI Entry + bit_offset: 0 + bit_size: 1 + - name: TLPIEX + description: Transmit LPI Exit + bit_offset: 1 + bit_size: 1 + - name: RLPIEN + description: Receive LPI Entry + bit_offset: 2 + bit_size: 1 + - name: RLPIEX + description: Receive LPI Exit + bit_offset: 3 + bit_size: 1 + - name: TLPIST + description: Transmit LPI State + bit_offset: 8 + bit_size: 1 + - name: RLPIST + description: Receive LPI State + bit_offset: 9 + bit_size: 1 + - name: LPIEN + description: LPI Enable + bit_offset: 16 + bit_size: 1 + - name: PLS + description: PHY Link Status + bit_offset: 17 + bit_size: 1 + - name: PLSEN + description: PHY Link Status Enable + bit_offset: 18 + bit_size: 1 + - name: LPITXA + description: LPI Tx Automate + bit_offset: 19 + bit_size: 1 + - name: LPITE + description: LPI Timer Enable + bit_offset: 20 + bit_size: 1 +fieldset/MACLETR: + description: LPI entry timer register + fields: + - name: LPIET + description: LPI Entry Timer + bit_offset: 3 + bit_size: 17 +fieldset/MACLMIR: + description: Log message interval register + fields: + - name: LSI + description: Log Sync Interval + bit_offset: 0 + bit_size: 8 + - name: DRSYNCR + description: Delay_Req to SYNC Ratio + bit_offset: 8 + bit_size: 3 + - name: LMPDRI + description: Log Min Pdelay_Req Interval + bit_offset: 24 + bit_size: 8 +fieldset/MACLTCR: + description: LPI timers control register + fields: + - name: TWT + description: LPI TW Timer + bit_offset: 0 + bit_size: 16 + - name: LST + description: LPI LS Timer + bit_offset: 16 + bit_size: 10 +fieldset/MACMDIOAR: + description: MDIO address register + fields: + - name: MB + description: MII Busy + bit_offset: 0 + bit_size: 1 + - name: C45E + description: Clause 45 PHY Enable + bit_offset: 1 + bit_size: 1 + - name: GOC + description: MII Operation Command + bit_offset: 2 + bit_size: 2 + - name: SKAP + description: Skip Address Packet + bit_offset: 4 + bit_size: 1 + - name: CR + description: CSR Clock Range + bit_offset: 8 + bit_size: 4 + - name: NTC + description: Number of Training Clocks + bit_offset: 12 + bit_size: 3 + - name: RDA + description: Register/Device Address + bit_offset: 16 + bit_size: 5 + - name: PA + description: Physical Layer Address + bit_offset: 21 + bit_size: 5 + - name: BTB + description: Back to Back transactions + bit_offset: 26 + bit_size: 1 + - name: PSE + description: Preamble Suppression Enable + bit_offset: 27 + bit_size: 1 +fieldset/MACMDIODR: + description: MDIO data register + fields: + - name: MD + description: MII Data + bit_offset: 0 + bit_size: 16 + - name: RA + description: Register Address + bit_offset: 16 + bit_size: 16 +fieldset/MACPCSR: + description: PMT control status register + fields: + - name: PWRDWN + description: Power Down + bit_offset: 0 + bit_size: 1 + - name: MGKPKTEN + description: Magic Packet Enable + bit_offset: 1 + bit_size: 1 + - name: RWKPKTEN + description: Remote wakeup Packet Enable + bit_offset: 2 + bit_size: 1 + - name: MGKPRCVD + description: Magic Packet Received + bit_offset: 5 + bit_size: 1 + - name: RWKPRCVD + description: Remote wakeup Packet Received + bit_offset: 6 + bit_size: 1 + - name: GLBLUCAST + description: Global Unicast + bit_offset: 9 + bit_size: 1 + - name: RWKPFE + description: Remote wakeup Packet Forwarding Enable + bit_offset: 10 + bit_size: 1 + - name: RWKPTR + description: Remote wakeup FIFO Pointer + bit_offset: 24 + bit_size: 5 + - name: RWKFILTRST + description: Remote wakeup Packet Filter Register Pointer Reset + bit_offset: 31 + bit_size: 1 +fieldset/MACPFR: + description: Packet filtering control register + fields: + - name: PR + description: Promiscuous Mode + bit_offset: 0 + bit_size: 1 + - name: HUC + description: Hash Unicast + bit_offset: 1 + bit_size: 1 + - name: HMC + description: Hash Multicast + bit_offset: 2 + bit_size: 1 + - name: DAIF + description: DA Inverse Filtering + bit_offset: 3 + bit_size: 1 + - name: PM + description: Pass All Multicast + bit_offset: 4 + bit_size: 1 + - name: DBF + description: Disable Broadcast Packets + bit_offset: 5 + bit_size: 1 + - name: PCF + description: Pass Control Packets + bit_offset: 6 + bit_size: 2 + - name: SAIF + description: SA Inverse Filtering + bit_offset: 8 + bit_size: 1 + - name: SAF + description: Source Address Filter Enable + bit_offset: 9 + bit_size: 1 + - name: HPF + description: Hash or Perfect Filter + bit_offset: 10 + bit_size: 1 + - name: VTFE + description: VLAN Tag Filter Enable + bit_offset: 16 + bit_size: 1 + - name: IPFE + description: Layer 3 and Layer 4 Filter Enable + bit_offset: 20 + bit_size: 1 + - name: DNTU + description: Drop Non-TCP/UDP over IP Packets + bit_offset: 21 + bit_size: 1 + - name: RA + description: Receive All + bit_offset: 31 + bit_size: 1 +fieldset/MACPOCR: + description: PTP Offload control register + fields: + - name: PTOEN + description: PTP Offload Enable + bit_offset: 0 + bit_size: 1 + - name: ASYNCEN + description: Automatic PTP SYNC message Enable + bit_offset: 1 + bit_size: 1 + - name: APDREQEN + description: Automatic PTP Pdelay_Req message Enable + bit_offset: 2 + bit_size: 1 + - name: ASYNCTRIG + description: Automatic PTP SYNC message Trigger + bit_offset: 4 + bit_size: 1 + - name: APDREQTRIG + description: Automatic PTP Pdelay_Req message Trigger + bit_offset: 5 + bit_size: 1 + - name: DRRDIS + description: Disable PTO Delay Request/Response response generation + bit_offset: 6 + bit_size: 1 + - name: DN + description: Domain Number + bit_offset: 8 + bit_size: 8 +fieldset/MACPPSCR: + description: PPS control register + fields: + - name: PPSCTRL + description: "Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared" + bit_offset: 0 + bit_size: 4 + - name: PPSEN0 + description: Flexible PPS Output Mode Enable + bit_offset: 4 + bit_size: 1 + - name: TRGTMODSEL0 + description: Target Time Register Mode for PPS Output + bit_offset: 5 + bit_size: 2 +fieldset/MACPPSIR: + description: PPS interval register + fields: + - name: PPSINT0 + description: PPS Output Signal Interval + bit_offset: 0 + bit_size: 32 +fieldset/MACPPSTTNR: + description: PPS target time nanoseconds register + fields: + - name: TTSL0 + description: Target Time Low for PPS Register + bit_offset: 0 + bit_size: 31 + - name: TRGTBUSY0 + description: PPS Target Time Register Busy + bit_offset: 31 + bit_size: 1 +fieldset/MACPPSTTSR: + description: PPS target time seconds register + fields: + - name: TSTRH0 + description: PPS Target Time Seconds Register + bit_offset: 0 + bit_size: 31 +fieldset/MACPPSWR: + description: PPS width register + fields: + - name: PPSWIDTH0 + description: PPS Output Signal Width + bit_offset: 0 + bit_size: 32 +fieldset/MACQTxFCR: + description: Tx Queue flow control register + fields: + - name: FCB_BPA + description: Flow Control Busy or Backpressure Activate + bit_offset: 0 + bit_size: 1 + - name: TFE + description: Transmit Flow Control Enable + bit_offset: 1 + bit_size: 1 + - name: PLT + description: Pause Low Threshold + bit_offset: 4 + bit_size: 3 + - name: DZPQ + description: Disable Zero-Quanta Pause + bit_offset: 7 + bit_size: 1 + - name: PT + description: Pause Time + bit_offset: 16 + bit_size: 16 +fieldset/MACRWKPFR: + description: Remove wakeup packet filter register + fields: + - name: MACRWKPFR + description: Remote wakeup packet filter + bit_offset: 0 + bit_size: 32 +fieldset/MACRxFCR: + description: Rx flow control register + fields: + - name: RFE + description: Receive Flow Control Enable + bit_offset: 0 + bit_size: 1 + - name: UP + description: Unicast Pause Packet Detect + bit_offset: 1 + bit_size: 1 +fieldset/MACRxTxSR: + description: Rx Tx status register + fields: + - name: TJT + description: Transmit Jabber Timeout + bit_offset: 0 + bit_size: 1 + - name: NCARR + description: No Carrier + bit_offset: 1 + bit_size: 1 + - name: LCARR + description: Loss of Carrier + bit_offset: 2 + bit_size: 1 + - name: EXDEF + description: Excessive Deferral + bit_offset: 3 + bit_size: 1 + - name: LCOL + description: Late Collision + bit_offset: 4 + bit_size: 1 + - name: EXCOL + description: Excessive Collisions + bit_offset: 5 + bit_size: 1 + - name: RWT + description: Receive Watchdog Timeout + bit_offset: 8 + bit_size: 1 +fieldset/MACSPI0R: + description: PTP Source Port Identity 0 Register + fields: + - name: SPI0 + description: Source Port Identity 0 + bit_offset: 0 + bit_size: 32 +fieldset/MACSPI1R: + description: PTP Source port identity 1 register + fields: + - name: SPI1 + description: Source Port Identity 1 + bit_offset: 0 + bit_size: 32 +fieldset/MACSPI2R: + description: PTP Source port identity 2 register + fields: + - name: SPI2 + description: Source Port Identity 2 + bit_offset: 0 + bit_size: 16 +fieldset/MACSSIR: + description: Sub-second increment register + fields: + - name: SNSINC + description: Sub-nanosecond Increment Value + bit_offset: 8 + bit_size: 8 + - name: SSINC + description: Sub-second Increment Value + bit_offset: 16 + bit_size: 8 +fieldset/MACSTNR: + description: System time nanoseconds register + fields: + - name: TSSS + description: Timestamp Sub-seconds + bit_offset: 0 + bit_size: 31 +fieldset/MACSTNUR: + description: System time nanoseconds update register + fields: + - name: TSSS + description: Timestamp Sub-seconds + bit_offset: 0 + bit_size: 31 + - name: ADDSUB + description: Add or Subtract Time + bit_offset: 31 + bit_size: 1 +fieldset/MACSTSR: + description: System time seconds register + fields: + - name: TSS + description: Timestamp Second + bit_offset: 0 + bit_size: 32 +fieldset/MACSTSUR: + description: System time seconds update register + fields: + - name: TSS + description: Timestamp Seconds + bit_offset: 0 + bit_size: 32 +fieldset/MACTSAR: + description: Timestamp addend register + fields: + - name: TSAR + description: Timestamp Addend Register + bit_offset: 0 + bit_size: 32 +fieldset/MACTSCR: + description: Timestamp control Register + fields: + - name: TSENA + description: Enable Timestamp + bit_offset: 0 + bit_size: 1 + - name: TSCFUPDT + description: Fine or Coarse Timestamp Update + bit_offset: 1 + bit_size: 1 + - name: TSINIT + description: Initialize Timestamp + bit_offset: 2 + bit_size: 1 + - name: TSUPDT + description: Update Timestamp + bit_offset: 3 + bit_size: 1 + - name: TSADDREG + description: Update Addend Register + bit_offset: 5 + bit_size: 1 + - name: TSENALL + description: Enable Timestamp for All Packets + bit_offset: 8 + bit_size: 1 + - name: TSCTRLSSR + description: Timestamp Digital or Binary Rollover Control + bit_offset: 9 + bit_size: 1 + - name: TSVER2ENA + description: Enable PTP Packet Processing for Version 2 Format + bit_offset: 10 + bit_size: 1 + - name: TSIPENA + description: Enable Processing of PTP over Ethernet Packets + bit_offset: 11 + bit_size: 1 + - name: TSIPV6ENA + description: Enable Processing of PTP Packets Sent over IPv6-UDP + bit_offset: 12 + bit_size: 1 + - name: TSIPV4ENA + description: Enable Processing of PTP Packets Sent over IPv4-UDP + bit_offset: 13 + bit_size: 1 + - name: TSEVNTENA + description: Enable Timestamp Snapshot for Event Messages + bit_offset: 14 + bit_size: 1 + - name: TSMSTRENA + description: Enable Snapshot for Messages Relevant to Master + bit_offset: 15 + bit_size: 1 + - name: SNAPTYPSEL + description: Select PTP packets for Taking Snapshots + bit_offset: 16 + bit_size: 2 + - name: TSENMACADDR + description: Enable MAC Address for PTP Packet Filtering + bit_offset: 18 + bit_size: 1 + - name: CSC + description: Enable checksum correction during OST for PTP over UDP/IPv4 packets + bit_offset: 19 + bit_size: 1 + - name: TXTSSTSM + description: Transmit Timestamp Status Mode + bit_offset: 24 + bit_size: 1 +fieldset/MACTSEACR: + description: Timestamp Egress asymmetric correction register + fields: + - name: OSTEAC + description: One-Step Timestamp Egress Asymmetry Correction + bit_offset: 0 + bit_size: 32 +fieldset/MACTSECNR: + description: Timestamp Egress correction nanosecond register + fields: + - name: TSEC + description: Timestamp Egress Correction + bit_offset: 0 + bit_size: 32 +fieldset/MACTSIACR: + description: Timestamp Ingress asymmetric correction register + fields: + - name: OSTIAC + description: One-Step Timestamp Ingress Asymmetry Correction + bit_offset: 0 + bit_size: 32 +fieldset/MACTSICNR: + description: Timestamp Ingress correction nanosecond register + fields: + - name: TSIC + description: Timestamp Ingress Correction + bit_offset: 0 + bit_size: 32 +fieldset/MACTSSR: + description: Timestamp status register + fields: + - name: TSSOVF + description: Timestamp Seconds Overflow + bit_offset: 0 + bit_size: 1 + - name: TSTARGT0 + description: Timestamp Target Time Reached + bit_offset: 1 + bit_size: 1 + - name: AUXTSTRIG + description: Auxiliary Timestamp Trigger Snapshot + bit_offset: 2 + bit_size: 1 + - name: TSTRGTERR0 + description: Timestamp Target Time Error + bit_offset: 3 + bit_size: 1 + - name: TXTSSIS + description: Tx Timestamp Status Interrupt Status + bit_offset: 15 + bit_size: 1 + - name: ATSSTN + description: Auxiliary Timestamp Snapshot Trigger Identifier + bit_offset: 16 + bit_size: 4 + - name: ATSSTM + description: Auxiliary Timestamp Snapshot Trigger Missed + bit_offset: 24 + bit_size: 1 + - name: ATSNS + description: Number of Auxiliary Timestamp Snapshots + bit_offset: 25 + bit_size: 5 +fieldset/MACTxTSSNR: + description: Tx timestamp status nanoseconds register + fields: + - name: TXTSSLO + description: Transmit Timestamp Status Low + bit_offset: 0 + bit_size: 31 + - name: TXTSSMIS + description: Transmit Timestamp Status Missed + bit_offset: 31 + bit_size: 1 +fieldset/MACTxTSSSR: + description: Tx timestamp status seconds register + fields: + - name: TXTSSHI + description: Transmit Timestamp Status High + bit_offset: 0 + bit_size: 32 +fieldset/MACVHTR: + description: VLAN Hash table register + fields: + - name: VLHT + description: VLAN Hash Table + bit_offset: 0 + bit_size: 16 +fieldset/MACVIR: + description: VLAN inclusion register + fields: + - name: VLT + description: VLAN Tag for Transmit Packets + bit_offset: 0 + bit_size: 16 + - name: VLC + description: VLAN Tag Control in Transmit Packets + bit_offset: 16 + bit_size: 2 + - name: VLP + description: VLAN Priority Control + bit_offset: 18 + bit_size: 1 + - name: CSVL + description: C-VLAN or S-VLAN + bit_offset: 19 + bit_size: 1 + - name: VLTI + description: VLAN Tag Input + bit_offset: 20 + bit_size: 1 +fieldset/MACVR: + description: Version register + fields: + - name: SNPSVER + description: IP version + bit_offset: 0 + bit_size: 8 + - name: USERVER + description: ST-defined version + bit_offset: 8 + bit_size: 8 +fieldset/MACVTR: + description: VLAN tag register + fields: + - name: VL + description: VLAN Tag Identifier for Receive Packets + bit_offset: 0 + bit_size: 16 + - name: ETV + description: Enable 12-Bit VLAN Tag Comparison + bit_offset: 16 + bit_size: 1 + - name: VTIM + description: VLAN Tag Inverse Match Enable + bit_offset: 17 + bit_size: 1 + - name: ESVL + description: Enable S-VLAN + bit_offset: 18 + bit_size: 1 + - name: ERSVLM + description: Enable Receive S-VLAN Match + bit_offset: 19 + bit_size: 1 + - name: DOVLTC + description: Disable VLAN Type Check + bit_offset: 20 + bit_size: 1 + - name: EVLS + description: Enable VLAN Tag Stripping on Receive + bit_offset: 21 + bit_size: 2 + - name: EVLRXS + description: Enable VLAN Tag in Rx status + bit_offset: 24 + bit_size: 1 + - name: VTHM + description: VLAN Tag Hash Table Match Enable + bit_offset: 25 + bit_size: 1 + - name: EDVLP + description: Enable Double VLAN Processing + bit_offset: 26 + bit_size: 1 + - name: ERIVLT + description: Enable Inner VLAN Tag + bit_offset: 27 + bit_size: 1 + - name: EIVLS + description: Enable Inner VLAN Tag Stripping on Receive + bit_offset: 28 + bit_size: 2 + - name: EIVLRXS + description: Enable Inner VLAN Tag in Rx Status + bit_offset: 31 + bit_size: 1 +fieldset/MACWTR: + description: Watchdog timeout register + fields: + - name: WTO + description: Watchdog Timeout + bit_offset: 0 + bit_size: 4 + - name: PWE + description: Programmable Watchdog Enable + bit_offset: 8 + bit_size: 1 +fieldset/MMC_CONTROL: + description: MMC control register + fields: + - name: CNTRST + description: Counters Reset + bit_offset: 0 + bit_size: 1 + - name: CNTSTOPRO + description: Counter Stop Rollover + bit_offset: 1 + bit_size: 1 + - name: RSTONRD + description: Reset on Read + bit_offset: 2 + bit_size: 1 + - name: CNTFREEZ + description: MMC Counter Freeze + bit_offset: 3 + bit_size: 1 + - name: CNTPRST + description: Counters Preset + bit_offset: 4 + bit_size: 1 + - name: CNTPRSTLVL + description: Full-Half Preset + bit_offset: 5 + bit_size: 1 + - name: UCDBC + description: Update MMC Counters for Dropped Broadcast Packets + bit_offset: 8 + bit_size: 1 +fieldset/MMC_RX_INTERRUPT: + description: MMC Rx interrupt register + fields: + - name: RXCRCERPIS + description: MMC Receive CRC Error Packet Counter Interrupt Status + bit_offset: 5 + bit_size: 1 + - name: RXALGNERPIS + description: MMC Receive Alignment Error Packet Counter Interrupt Status + bit_offset: 6 + bit_size: 1 + - name: RXUCGPIS + description: MMC Receive Unicast Good Packet Counter Interrupt Status + bit_offset: 17 + bit_size: 1 + - name: RXLPIUSCIS + description: MMC Receive LPI microsecond counter interrupt status + bit_offset: 26 + bit_size: 1 + - name: RXLPITRCIS + description: MMC Receive LPI transition counter interrupt status + bit_offset: 27 + bit_size: 1 +fieldset/MMC_RX_INTERRUPT_MASK: + description: MMC Rx interrupt mask register + fields: + - name: RXCRCERPIM + description: MMC Receive CRC Error Packet Counter Interrupt Mask + bit_offset: 5 + bit_size: 1 + - name: RXALGNERPIM + description: MMC Receive Alignment Error Packet Counter Interrupt Mask + bit_offset: 6 + bit_size: 1 + - name: RXUCGPIM + description: MMC Receive Unicast Good Packet Counter Interrupt Mask + bit_offset: 17 + bit_size: 1 + - name: RXLPIUSCIM + description: MMC Receive LPI microsecond counter interrupt Mask + bit_offset: 26 + bit_size: 1 + - name: RXLPITRCIM + description: MMC Receive LPI transition counter interrupt Mask + bit_offset: 27 + bit_size: 1 +fieldset/MMC_TX_INTERRUPT: + description: MMC Tx interrupt register + fields: + - name: TXSCOLGPIS + description: MMC Transmit Single Collision Good Packet Counter Interrupt Status + bit_offset: 14 + bit_size: 1 + - name: TXMCOLGPIS + description: MMC Transmit Multiple Collision Good Packet Counter Interrupt Status + bit_offset: 15 + bit_size: 1 + - name: TXGPKTIS + description: MMC Transmit Good Packet Counter Interrupt Status + bit_offset: 21 + bit_size: 1 + - name: TXLPIUSCIS + description: MMC Transmit LPI microsecond counter interrupt status + bit_offset: 26 + bit_size: 1 + - name: TXLPITRCIS + description: MMC Transmit LPI transition counter interrupt status + bit_offset: 27 + bit_size: 1 +fieldset/MMC_TX_INTERRUPT_MASK: + description: MMC Tx interrupt mask register + fields: + - name: TXSCOLGPIM + description: MMC Transmit Single Collision Good Packet Counter Interrupt Mask + bit_offset: 14 + bit_size: 1 + - name: TXMCOLGPIM + description: MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask + bit_offset: 15 + bit_size: 1 + - name: TXGPKTIM + description: MMC Transmit Good Packet Counter Interrupt Mask + bit_offset: 21 + bit_size: 1 + - name: TXLPIUSCIM + description: MMC Transmit LPI microsecond counter interrupt Mask + bit_offset: 26 + bit_size: 1 + - name: TXLPITRCIM + description: MMC Transmit LPI transition counter interrupt Mask + bit_offset: 27 + bit_size: 1 +fieldset/RX_ALIGNMENT_ERROR_PACKETS: + description: Rx alignment error packets register + fields: + - name: RXALGNERR + description: Rx Alignment Error Packets + bit_offset: 0 + bit_size: 32 +fieldset/RX_CRC_ERROR_PACKETS: + description: Rx CRC error packets register + fields: + - name: RXCRCERR + description: Rx CRC Error Packets + bit_offset: 0 + bit_size: 32 +fieldset/RX_LPI_TRAN_CNTR: + description: Rx LPI transition counter register + fields: + - name: RXLPITRC + description: Rx LPI Transition counter + bit_offset: 0 + bit_size: 32 +fieldset/RX_LPI_USEC_CNTR: + description: Rx LPI microsecond counter register + fields: + - name: RXLPIUSC + description: Rx LPI Microseconds Counter + bit_offset: 0 + bit_size: 32 +fieldset/RX_UNICAST_PACKETS_GOOD: + description: Rx unicast packets good register + fields: + - name: RXUCASTG + description: Rx Unicast Packets Good + bit_offset: 0 + bit_size: 32 +fieldset/TX_LPI_TRAN_CNTR: + description: Tx LPI transition counter register + fields: + - name: TXLPITRC + description: Tx LPI Transition counter + bit_offset: 0 + bit_size: 32 +fieldset/TX_LPI_USEC_CNTR: + description: Tx LPI microsecond timer register + fields: + - name: TXLPIUSC + description: Tx LPI Microseconds Counter + bit_offset: 0 + bit_size: 32 +fieldset/TX_MULTIPLE_COLLISION_GOOD_PACKETS: + description: Tx multiple collision good packets register + fields: + - name: TXMULTCOLG + description: Tx Multiple Collision Good Packets + bit_offset: 0 + bit_size: 32 +fieldset/TX_PACKET_COUNT_GOOD: + description: Tx packet count good register + fields: + - name: TXPKTG + description: Tx Packet Count Good + bit_offset: 0 + bit_size: 32 +fieldset/TX_SINGLE_COLLISION_GOOD_PACKETS: + description: Tx single collision good packets register + fields: + - name: TXSNGLCOLG + description: Tx Single Collision Good Packets + bit_offset: 0 + bit_size: 32 +block/ETHERNET_MTL: + description: "Ethernet: MTL mode register (MTL)" + items: + - name: MTLOMR + description: Operating mode Register + byte_offset: 0 + fieldset: MTLOMR + - name: MTLISR + description: Interrupt status Register + byte_offset: 32 + access: Read + fieldset: MTLISR + - name: MTLTxQOMR + description: Tx queue operating mode Register + byte_offset: 256 + fieldset: MTLTxQOMR + - name: MTLTxQUR + description: Tx queue underflow register + byte_offset: 260 + access: Read + fieldset: MTLTxQUR + - name: MTLTxQDR + description: Tx queue debug Register + byte_offset: 264 + access: Read + fieldset: MTLTxQDR + - name: MTLQICSR + description: Queue interrupt control status Register + byte_offset: 300 + fieldset: MTLQICSR + - name: MTLRxQOMR + description: Rx queue operating mode register + byte_offset: 304 + fieldset: MTLRxQOMR + - name: MTLRxQMPOCR + description: Rx queue missed packet and overflow counter register + byte_offset: 308 + access: Read + fieldset: MTLRxQMPOCR + - name: MTLRxQDR + description: Rx queue debug register + byte_offset: 312 + access: Read + fieldset: MTLRxQDR +fieldset/MTLISR: + description: Interrupt status Register + fields: + - name: Q0IS + description: Queue interrupt status + bit_offset: 0 + bit_size: 1 +fieldset/MTLOMR: + description: Operating mode Register + fields: + - name: DTXSTS + description: Drop Transmit Status + bit_offset: 1 + bit_size: 1 + - name: CNTPRST + description: Counters Preset + bit_offset: 8 + bit_size: 1 + - name: CNTCLR + description: Counters Reset + bit_offset: 9 + bit_size: 1 +fieldset/MTLQICSR: + description: Queue interrupt control status Register + fields: + - name: TXUNFIS + description: Transmit Queue Underflow Interrupt Status + bit_offset: 0 + bit_size: 1 + - name: TXUIE + description: Transmit Queue Underflow Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: RXOVFIS + description: Receive Queue Overflow Interrupt Status + bit_offset: 16 + bit_size: 1 + - name: RXOIE + description: Receive Queue Overflow Interrupt Enable + bit_offset: 24 + bit_size: 1 +fieldset/MTLRxQDR: + description: Rx queue debug register + fields: + - name: RWCSTS + description: MTL Rx Queue Write Controller Active Status + bit_offset: 0 + bit_size: 1 + - name: RRCSTS + description: MTL Rx Queue Read Controller State + bit_offset: 1 + bit_size: 2 + - name: RXQSTS + description: MTL Rx Queue Fill-Level Status + bit_offset: 4 + bit_size: 2 + - name: PRXQ + description: Number of Packets in Receive Queue + bit_offset: 16 + bit_size: 14 +fieldset/MTLRxQMPOCR: + description: Rx queue missed packet and overflow counter register + fields: + - name: OVFPKTCNT + description: Overflow Packet Counter + bit_offset: 0 + bit_size: 11 + - name: OVFCNTOVF + description: Overflow Counter Overflow Bit + bit_offset: 11 + bit_size: 1 + - name: MISPKTCNT + description: Missed Packet Counter + bit_offset: 16 + bit_size: 11 + - name: MISCNTOVF + description: Missed Packet Counter Overflow Bit + bit_offset: 27 + bit_size: 1 +fieldset/MTLRxQOMR: + description: Rx queue operating mode register + fields: + - name: RTC + description: Receive Queue Threshold Control + bit_offset: 0 + bit_size: 2 + - name: FUP + description: Forward Undersized Good Packets + bit_offset: 3 + bit_size: 1 + - name: FEP + description: Forward Error Packets + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Receive Queue Store and Forward + bit_offset: 5 + bit_size: 1 + - name: DIS_TCP_EF + description: Disable Dropping of TCP/IP Checksum Error Packets + bit_offset: 6 + bit_size: 1 + - name: EHFC + description: Enable Hardware Flow Control + bit_offset: 7 + bit_size: 1 + - name: RFA + description: Threshold for Activating Flow Control (in half-duplex and full-duplex modes) + bit_offset: 8 + bit_size: 3 + - name: RFD + description: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) + bit_offset: 14 + bit_size: 3 + - name: RQS + description: Receive Queue Size + bit_offset: 20 + bit_size: 3 +fieldset/MTLTxQDR: + description: Tx queue debug Register + fields: + - name: TXQPAUSED + description: Transmit Queue in Pause + bit_offset: 0 + bit_size: 1 + - name: TRCSTS + description: MTL Tx Queue Read Controller Status + bit_offset: 1 + bit_size: 2 + - name: TWCSTS + description: MTL Tx Queue Write Controller Status + bit_offset: 3 + bit_size: 1 + - name: TXQSTS + description: MTL Tx Queue Not Empty Status + bit_offset: 4 + bit_size: 1 + - name: TXSTSFSTS + description: MTL Tx Status FIFO Full Status + bit_offset: 5 + bit_size: 1 + - name: PTXQ + description: Number of Packets in the Transmit Queue + bit_offset: 16 + bit_size: 3 + - name: STXSTSF + description: Number of Status Words in Tx Status FIFO of Queue + bit_offset: 20 + bit_size: 3 +fieldset/MTLTxQOMR: + description: Tx queue operating mode Register + fields: + - name: FTQ + description: Flush Transmit Queue + bit_offset: 0 + bit_size: 1 + - name: TSF + description: Transmit Store and Forward + bit_offset: 1 + bit_size: 1 + - name: TXQEN + description: Transmit Queue Enable + bit_offset: 2 + bit_size: 2 + - name: TTC + description: Transmit Threshold Control + bit_offset: 4 + bit_size: 3 + - name: TQS + description: Transmit Queue Size + bit_offset: 16 + bit_size: 3 +fieldset/MTLTxQUR: + description: Tx queue underflow register + fields: + - name: UFFRMCNT + description: Underflow Packet Counter + bit_offset: 0 + bit_size: 11 + - name: UFCNTOVF + description: Overflow Bit for Underflow Packet Counter + bit_offset: 11 + bit_size: 1 +block/ETHERNET_DMA: + description: "Ethernet: DMA mode register (DMA)" + items: + - name: DMAMR + description: DMA mode register + byte_offset: 0 + fieldset: DMAMR + - name: DMASBMR + description: System bus mode register + byte_offset: 4 + fieldset: DMASBMR + - name: DMAISR + description: Interrupt status register + byte_offset: 8 + access: Read + fieldset: DMAISR + - name: DMADSR + description: Debug status register + byte_offset: 12 + access: Read + fieldset: DMADSR + - name: DMACCR + description: Channel control register + byte_offset: 256 + fieldset: DMACCR + - name: DMACTxCR + description: Channel transmit control register + byte_offset: 260 + fieldset: DMACTxCR + - name: DMACRxCR + description: Channel receive control register + byte_offset: 264 + fieldset: DMACRxCR + - name: DMACTxDLAR + description: Channel Tx descriptor list address register + byte_offset: 276 + fieldset: DMACTxDLAR + - name: DMACRxDLAR + description: Channel Rx descriptor list address register + byte_offset: 284 + fieldset: DMACRxDLAR + - name: DMACTxDTPR + description: Channel Tx descriptor tail pointer register + byte_offset: 288 + fieldset: DMACTxDTPR + - name: DMACRxDTPR + description: Channel Rx descriptor tail pointer register + byte_offset: 296 + fieldset: DMACRxDTPR + - name: DMACTxRLR + description: Channel Tx descriptor ring length register + byte_offset: 300 + fieldset: DMACTxRLR + - name: DMACRxRLR + description: Channel Rx descriptor ring length register + byte_offset: 304 + fieldset: DMACRxRLR + - name: DMACIER + description: Channel interrupt enable register + byte_offset: 308 + fieldset: DMACIER + - name: DMACRxIWTR + description: Channel Rx interrupt watchdog timer register + byte_offset: 312 + fieldset: DMACRxIWTR + - name: DMACCATxDR + description: Channel current application transmit descriptor register + byte_offset: 324 + access: Read + fieldset: DMACCATxDR + - name: DMACCARxDR + description: Channel current application receive descriptor register + byte_offset: 332 + access: Read + fieldset: DMACCARxDR + - name: DMACCATxBR + description: Channel current application transmit buffer register + byte_offset: 340 + access: Read + fieldset: DMACCATxBR + - name: DMACCARxBR + description: Channel current application receive buffer register + byte_offset: 348 + access: Read + fieldset: DMACCARxBR + - name: DMACSR + description: Channel status register + byte_offset: 352 + fieldset: DMACSR + - name: DMACMFCR + description: Channel missed frame count register + byte_offset: 364 + access: Read + fieldset: DMACMFCR +fieldset/DMACCARxBR: + description: Channel current application receive buffer register + fields: + - name: CURRBUFAPTR + description: Application Receive Buffer Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCARxDR: + description: Channel current application receive descriptor register + fields: + - name: CURRDESAPTR + description: Application Receive Descriptor Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCATxBR: + description: Channel current application transmit buffer register + fields: + - name: CURTBUFAPTR + description: Application Transmit Buffer Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCATxDR: + description: Channel current application transmit descriptor register + fields: + - name: CURTDESAPTR + description: Application Transmit Descriptor Address Pointer + bit_offset: 0 + bit_size: 32 +fieldset/DMACCR: + description: Channel control register + fields: + - name: MSS + description: Maximum Segment Size + bit_offset: 0 + bit_size: 14 + - name: PBLX8 + description: 8xPBL mode + bit_offset: 16 + bit_size: 1 + - name: DSL + description: Descriptor Skip Length + bit_offset: 18 + bit_size: 3 +fieldset/DMACIER: + description: Channel interrupt enable register + fields: + - name: TIE + description: Transmit Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: TXSE + description: Transmit Stopped Enable + bit_offset: 1 + bit_size: 1 + - name: TBUE + description: Transmit Buffer Unavailable Enable + bit_offset: 2 + bit_size: 1 + - name: RIE + description: Receive Interrupt Enable + bit_offset: 6 + bit_size: 1 + - name: RBUE + description: Receive Buffer Unavailable Enable + bit_offset: 7 + bit_size: 1 + - name: RSE + description: Receive Stopped Enable + bit_offset: 8 + bit_size: 1 + - name: RWTE + description: Receive Watchdog Timeout Enable + bit_offset: 9 + bit_size: 1 + - name: ETIE + description: Early Transmit Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: ERIE + description: Early Receive Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: FBEE + description: Fatal Bus Error Enable + bit_offset: 12 + bit_size: 1 + - name: CDEE + description: Context Descriptor Error Enable + bit_offset: 13 + bit_size: 1 + - name: AIE + description: Abnormal Interrupt Summary Enable + bit_offset: 14 + bit_size: 1 + - name: NIE + description: Normal Interrupt Summary Enable + bit_offset: 15 + bit_size: 1 +fieldset/DMACMFCR: + description: Channel missed frame count register + fields: + - name: MFC + description: Dropped Packet Counters + bit_offset: 0 + bit_size: 11 + - name: MFCO + description: Overflow status of the MFC Counter + bit_offset: 15 + bit_size: 1 +fieldset/DMACRxCR: + description: Channel receive control register + fields: + - name: SR + description: Start or Stop Receive Command + bit_offset: 0 + bit_size: 1 + - name: RBSZ + description: Receive Buffer size + bit_offset: 1 + bit_size: 14 + - name: RXPBL + description: RXPBL + bit_offset: 16 + bit_size: 6 + - name: RPF + description: DMA Rx Channel Packet Flush + bit_offset: 31 + bit_size: 1 +fieldset/DMACRxDLAR: + description: Channel Rx descriptor list address register + fields: + - name: RDESLA + description: Start of Receive List + bit_offset: 2 + bit_size: 30 +fieldset/DMACRxDTPR: + description: Channel Rx descriptor tail pointer register + fields: + - name: RDT + description: Receive Descriptor Tail Pointer + bit_offset: 2 + bit_size: 30 +fieldset/DMACRxIWTR: + description: Channel Rx interrupt watchdog timer register + fields: + - name: RWT + description: Receive Interrupt Watchdog Timer Count + bit_offset: 0 + bit_size: 8 +fieldset/DMACRxRLR: + description: Channel Rx descriptor ring length register + fields: + - name: RDRL + description: Receive Descriptor Ring Length + bit_offset: 0 + bit_size: 10 +fieldset/DMACSR: + description: Channel status register + fields: + - name: TI + description: Transmit Interrupt + bit_offset: 0 + bit_size: 1 + - name: TPS + description: Transmit Process Stopped + bit_offset: 1 + bit_size: 1 + - name: TBU + description: Transmit Buffer Unavailable + bit_offset: 2 + bit_size: 1 + - name: RI + description: Receive Interrupt + bit_offset: 6 + bit_size: 1 + - name: RBU + description: Receive Buffer Unavailable + bit_offset: 7 + bit_size: 1 + - name: RPS + description: Receive Process Stopped + bit_offset: 8 + bit_size: 1 + - name: RWT + description: Receive Watchdog Timeout + bit_offset: 9 + bit_size: 1 + - name: ET + description: Early Transmit Interrupt + bit_offset: 10 + bit_size: 1 + - name: ER + description: Early Receive Interrupt + bit_offset: 11 + bit_size: 1 + - name: FBE + description: Fatal Bus Error + bit_offset: 12 + bit_size: 1 + - name: CDE + description: Context Descriptor Error + bit_offset: 13 + bit_size: 1 + - name: AIS + description: Abnormal Interrupt Summary + bit_offset: 14 + bit_size: 1 + - name: NIS + description: Normal Interrupt Summary + bit_offset: 15 + bit_size: 1 + - name: TEB + description: Tx DMA Error Bits + bit_offset: 16 + bit_size: 3 + - name: REB + description: Rx DMA Error Bits + bit_offset: 19 + bit_size: 3 +fieldset/DMACTxCR: + description: Channel transmit control register + fields: + - name: ST + description: Start or Stop Transmission Command + bit_offset: 0 + bit_size: 1 + - name: OSF + description: Operate on Second Packet + bit_offset: 4 + bit_size: 1 + - name: TSE + description: TCP Segmentation Enabled + bit_offset: 12 + bit_size: 1 + - name: TXPBL + description: Transmit Programmable Burst Length + bit_offset: 16 + bit_size: 6 +fieldset/DMACTxDLAR: + description: Channel Tx descriptor list address register + fields: + - name: TDESLA + description: Start of Transmit List + bit_offset: 2 + bit_size: 30 +fieldset/DMACTxDTPR: + description: Channel Tx descriptor tail pointer register + fields: + - name: TDT + description: Transmit Descriptor Tail Pointer + bit_offset: 2 + bit_size: 30 +fieldset/DMACTxRLR: + description: Channel Tx descriptor ring length register + fields: + - name: TDRL + description: Transmit Descriptor Ring Length + bit_offset: 0 + bit_size: 10 +fieldset/DMADSR: + description: Debug status register + fields: + - name: AXWHSTS + description: AHB Master Write Channel + bit_offset: 0 + bit_size: 1 + - name: RPS0 + description: DMA Channel Receive Process State + bit_offset: 8 + bit_size: 4 + - name: TPS0 + description: DMA Channel Transmit Process State + bit_offset: 12 + bit_size: 4 +fieldset/DMAISR: + description: Interrupt status register + fields: + - name: DC0IS + description: DMA Channel Interrupt Status + bit_offset: 0 + bit_size: 1 + - name: MTLIS + description: MTL Interrupt Status + bit_offset: 16 + bit_size: 1 + - name: MACIS + description: MAC Interrupt Status + bit_offset: 17 + bit_size: 1 +fieldset/DMAMR: + description: DMA mode register + fields: + - name: SWR + description: Software Reset + bit_offset: 0 + bit_size: 1 + - name: DA + description: DMA Tx or Rx Arbitration Scheme + bit_offset: 1 + bit_size: 1 + - name: TXPR + description: Transmit priority + bit_offset: 11 + bit_size: 1 + - name: PR + description: Priority ratio + bit_offset: 12 + bit_size: 3 + - name: INTM + description: Interrupt Mode + bit_offset: 16 + bit_size: 2 +fieldset/DMASBMR: + description: System bus mode register + fields: + - name: FB + description: Fixed Burst Length + bit_offset: 0 + bit_size: 1 + - name: AAL + description: Address-Aligned Beats + bit_offset: 12 + bit_size: 1 + - name: MB + description: Mixed Burst + bit_offset: 14 + bit_size: 1 + - name: RB + description: Rebuild INCRx Burst + bit_offset: 15 + bit_size: 1 diff --git a/parse.py b/parse.py index 9014f11..45a4a2f 100644 --- a/parse.py +++ b/parse.py @@ -254,6 +254,7 @@ perimap = [ ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), ('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'), ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), + ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'), ] rng_clock_map = [