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rcc: fix tons of wrong muxes.

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This commit is contained in:
Dario Nieuwenhuis 2024-02-16 00:11:14 +01:00
parent c8698f3cd8
commit e2c7a7eae0
17 changed files with 384 additions and 191 deletions
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11
data/registers/rcc_f37.yaml
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@ -638,7 +638,7 @@ fieldset/CFGR3:
description: Timer2 clock source selection
bit_offset: 24
bit_size: 1
enum: TIMSW
enum: TIM2SW
- name: TIM34SW
description: Timer34 clock source selection
bit_offset: 25
@ -1168,6 +1168,15 @@ enum/SW:
- name: PLL1_P
description: PLL used as system clock
value: 2
enum/TIM2SW:
bit_size: 1
variants:
- name: PCLK1_TIM
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL1_P
description: PLL vco output (running up to 144 MHz)
value: 1
enum/TIMSW:
bit_size: 1
variants:

11
data/registers/rcc_f3v1.yaml
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@ -661,7 +661,7 @@ fieldset/CFGR3:
description: Timer2 clock source selection
bit_offset: 24
bit_size: 1
enum: TIMSW
enum: TIM2SW
- name: TIM34SW
description: Timer34 clock source selection
bit_offset: 25
@ -1140,6 +1140,15 @@ enum/SW:
- name: PLL1_P
description: PLL used as system clock
value: 2
enum/TIM2SW:
bit_size: 1
variants:
- name: PCLK1_TIM
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL1_P
description: PLL vco output (running up to 144 MHz)
value: 1
enum/TIMSW:
bit_size: 1
variants:

11
data/registers/rcc_f3v2.yaml
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@ -667,7 +667,7 @@ fieldset/CFGR3:
description: Timer2 clock source selection
bit_offset: 24
bit_size: 1
enum: TIMSW
enum: TIM2SW
- name: TIM34SW
description: Timer34 clock source selection
bit_offset: 25
@ -1182,6 +1182,15 @@ enum/SW:
- name: PLL1_P
description: PLL used as system clock
value: 2
enum/TIM2SW:
bit_size: 1
variants:
- name: PCLK1_TIM
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL1_P
description: PLL vco output (running up to 144 MHz)
value: 1
enum/TIMSW:
bit_size: 1
variants:

11
data/registers/rcc_f3v3.yaml
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@ -667,7 +667,7 @@ fieldset/CFGR3:
description: Timer2 clock source selection
bit_offset: 24
bit_size: 1
enum: TIMSW
enum: TIM2SW
- name: TIM34SW
description: Timer34 clock source selection
bit_offset: 25
@ -1185,6 +1185,15 @@ enum/SW:
- name: PLL1_P
description: PLL used as system clock
value: 2
enum/TIM2SW:
bit_size: 1
variants:
- name: PCLK1_TIM
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL1_P
description: PLL vco output (running up to 144 MHz)
value: 1
enum/TIMSW:
bit_size: 1
variants:

67
data/registers/rcc_h5.yaml
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@ -1403,7 +1403,7 @@ fieldset/CCIPR1:
description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
bit_offset: 0
bit_size: 3
enum: USARTSEL
enum: USART1SEL
- name: USART2SEL
description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
bit_offset: 3
@ -1418,12 +1418,12 @@ fieldset/CCIPR1:
description: "UART4 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 9
bit_size: 3
enum: UARTSEL
enum: USARTSEL
- name: UART5SEL
description: "UART5 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 12
bit_size: 3
enum: UARTSEL
enum: USARTSEL
- name: USART6SEL
description: "USART6 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 15
@ -1433,17 +1433,17 @@ fieldset/CCIPR1:
description: "UART7 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 18
bit_size: 3
enum: UARTSEL
enum: USARTSEL
- name: UART8SEL
description: "UART8 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 21
bit_size: 3
enum: UARTSEL
enum: USARTSEL
- name: UART9SEL
description: "UART9 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 24
bit_size: 3
enum: UARTSEL
enum: USARTSEL
- name: USART10SEL
description: "USART10 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 27
@ -1476,7 +1476,7 @@ fieldset/CCIPR2:
description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 12
bit_size: 3
enum: LPTIMSEL
enum: LPTIM2SEL
- name: LPTIM3SEL
description: "LPTIM3 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 16
@ -1534,7 +1534,7 @@ fieldset/CCIPR3:
description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 24
bit_size: 3
enum: LPUARTSEL
enum: LPUSARTSEL
fieldset/CCIPR4:
description: RCC kernel clock configuration register
fields:
@ -1577,12 +1577,12 @@ fieldset/CCIPR4:
description: I2C3 kernel clock source selection
bit_offset: 20
bit_size: 2
enum: I2CSEL
enum: I2C34SEL
- name: I2C4SEL
description: I2C4 kernel clock source selection
bit_offset: 22
bit_size: 2
enum: I2CSEL
enum: I2C34SEL
- name: I3C1SEL
description: I3C1 kernel clock source selection
bit_offset: 24
@ -2231,6 +2231,21 @@ enum/HSIDIV:
- name: Div8
description: Division by 8
value: 3
enum/I2C34SEL:
bit_size: 2
variants:
- name: PCLK3
description: rcc_pclk3 selected as peripheral clock
value: 0
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 1
- name: HSI
description: hsi_ker selected as peripheral clock
value: 2
- name: CSI
description: csi_ker selected as peripheral clock
value: 3
enum/I2CSEL:
bit_size: 2
variants:
@ -2246,6 +2261,24 @@ enum/I2CSEL:
- name: CSI
description: csi_ker selected as peripheral clock
value: 3
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 1
- name: LSE
description: LSE selected as peripheral clock
value: 3
- name: LSI
description: LSI selected as peripheral clock
value: 4
- name: PER
description: PER selected as peripheral clock
value: 5
enum/LPTIMSEL:
bit_size: 3
variants:
@ -2267,7 +2300,7 @@ enum/LPTIMSEL:
- name: PER
description: PER selected as peripheral clock
value: 5
enum/LPUARTSEL:
enum/LPUSARTSEL:
bit_size: 3
variants:
- name: PCLK3
@ -2420,7 +2453,7 @@ enum/NSPRIV:
enum/OCTOSPISEL:
bit_size: 2
variants:
- name: HCLK1
- name: HCLK4
description: rcc_hclk selected as kernel clock (default after reset)
value: 0
- name: PLL1_Q
@ -4139,11 +4172,11 @@ enum/TIMPRE:
- name: DefaultX4
description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
value: 1
enum/UARTSEL:
enum/USART1SEL:
bit_size: 3
variants:
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
@ -4163,8 +4196,8 @@ enum/UARTSEL:
enum/USARTSEL:
bit_size: 3
variants:
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock

63
data/registers/rcc_h50.yaml
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@ -802,7 +802,7 @@ fieldset/CCIPR1:
description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
bit_offset: 0
bit_size: 3
enum: USARTSEL
enum: USART1SEL
- name: USART2SEL
description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
bit_offset: 3
@ -825,12 +825,12 @@ fieldset/CCIPR2:
description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 8
bit_size: 3
enum: LPTIMSEL
enum: LPTIM1SEL
- name: LPTIM2SEL
description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled"
bit_offset: 12
bit_size: 3
enum: LPTIMSEL
enum: LPTIM2SEL
fieldset/CCIPR3:
description: RCC kernel clock configuration register
fields:
@ -886,7 +886,7 @@ fieldset/CCIPR4:
description: I3C2 kernel clock source selection
bit_offset: 26
bit_size: 2
enum: I2CSEL
enum: I3C2SEL
fieldset/CCIPR5:
description: RCC kernel clock configuration register
fields:
@ -1455,7 +1455,22 @@ enum/I2CSEL:
- name: CSI
description: csi_ker selected as peripheral clock
value: 3
enum/LPTIMSEL:
enum/I3C2SEL:
bit_size: 2
variants:
- name: PCLK3
description: rcc_pclk3 selected as peripheral clock
value: 0
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 1
- name: HSI
description: hsi_ker selected as peripheral clock
value: 2
- name: CSI
description: csi_ker selected as peripheral clock
value: 3
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: PCLK3
@ -1473,6 +1488,24 @@ enum/LPTIMSEL:
- name: PER
description: PER selected as peripheral clock
value: 5
enum/LPTIM2SEL:
bit_size: 3
variants:
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 1
- name: LSE
description: LSE selected as peripheral clock
value: 3
- name: LSI
description: LSI selected as peripheral clock
value: 4
- name: PER
description: PER selected as peripheral clock
value: 5
enum/LPUARTSEL:
bit_size: 3
variants:
@ -3180,7 +3213,7 @@ enum/TIMPRE:
- name: DefaultX4
description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
value: 1
enum/USARTSEL:
enum/USART1SEL:
bit_size: 3
variants:
- name: PCLK2
@ -3198,6 +3231,24 @@ enum/USARTSEL:
- name: LSE
description: LSE selected as peripheral clock
value: 5
enum/USARTSEL:
bit_size: 3
variants:
- name: PCLK1
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
value: 1
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
- name: CSI
description: csi_ker selected as peripheral clock
value: 4
- name: LSE
description: LSE selected as peripheral clock
value: 5
enum/USBSEL:
bit_size: 2
variants:

4
data/registers/rcc_h7.yaml
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@ -3718,8 +3718,8 @@ enum/LPTIM2SEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: PCLK3
description: rcc_pclk_d3 selected as peripheral clock
- name: PCLK4
description: rcc_pclk_d4 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock

4
data/registers/rcc_h7ab.yaml
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@ -2632,8 +2632,8 @@ enum/LPTIM2SEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: PCLK3
description: rcc_pclk_d3 selected as peripheral clock
- name: PCLK4
description: rcc_pclk_d4 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock

4
data/registers/rcc_h7rm0433.yaml
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@ -3701,8 +3701,8 @@ enum/LPTIM2SEL:
enum/LPUARTSEL:
bit_size: 3
variants:
- name: PCLK3
description: rcc_pclk_d3 selected as peripheral clock
- name: PCLK4
description: rcc_pclk_d4 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock

17
data/registers/rcc_l0.yaml
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@ -498,7 +498,7 @@ fieldset/CCIPR:
description: USART1 clock source selection
bit_offset: 0
bit_size: 2
enum: UARTSEL
enum: USART1SEL
- name: USART2SEL
description: USART2 clock source selection
bit_offset: 2
@ -1216,3 +1216,18 @@ enum/UARTSEL:
- name: LSE
description: LSE clock selected as peripheral clock
value: 3
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK2
description: APB clock selected as peripheral clock
value: 0
- name: SYS
description: System clock selected as peripheral clock
value: 1
- name: HSI
description: HSI clock selected as peripheral clock
value: 2
- name: LSE
description: LSE clock selected as peripheral clock
value: 3

17
data/registers/rcc_l0_v2.yaml
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@ -502,7 +502,7 @@ fieldset/CCIPR:
description: USART1 clock source selection
bit_offset: 0
bit_size: 2
enum: UARTSEL
enum: USART1SEL
- name: USART2SEL
description: USART2 clock source selection
bit_offset: 2
@ -1265,3 +1265,18 @@ enum/UARTSEL:
- name: LSE
description: LSE clock selected as peripheral clock
value: 3
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK2
description: APB clock selected as peripheral clock
value: 0
- name: SYS
description: System clock selected as peripheral clock
value: 1
- name: HSI
description: HSI clock selected as peripheral clock
value: 2
- name: LSE
description: LSE clock selected as peripheral clock
value: 3

65
data/registers/rcc_l4.yaml
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@ -564,10 +564,6 @@ fieldset/APB1ENR2:
description: LPTIM2EN
bit_offset: 5
bit_size: 1
- name: DFSDMEN
description: DFSDMEN enable
bit_offset: 24
bit_size: 1
fieldset/APB1RSTR1:
description: APB1 peripheral reset register 1
fields:
@ -867,8 +863,8 @@ fieldset/APB2ENR:
description: SAI2 clock enable
bit_offset: 22
bit_size: 1
- name: DFSDM_TIMEN
description: DFSDM timer clock enable
- name: DFSDMEN
description: DFSDMEN enable
bit_offset: 24
bit_size: 1
fieldset/APB2RSTR:
@ -1035,22 +1031,22 @@ fieldset/CCIPR:
description: USART2 clock source selection
bit_offset: 2
bit_size: 2
enum: USART2SEL
enum: USARTSEL
- name: USART3SEL
description: USART3 clock source selection
bit_offset: 4
bit_size: 2
enum: USART3SEL
enum: USARTSEL
- name: UART4SEL
description: UART4 clock source selection
bit_offset: 6
bit_size: 2
enum: UART4SEL
enum: USARTSEL
- name: UART5SEL
description: UART5 clock source selection
bit_offset: 8
bit_size: 2
enum: UART5SEL
enum: USARTSEL
- name: LPUART1SEL
description: LPUART1 clock source selection
bit_offset: 10
@ -2277,40 +2273,10 @@ enum/SWPMI1SEL:
value: 0
- name: HSI
value: 1
enum/UART4SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK clock selected
value: 0
- name: SYS
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI clock selected
value: 2
- name: LSE
description: LSE clock selected
value: 3
enum/UART5SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK clock selected
value: 0
- name: SYS
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI clock selected
value: 2
- name: LSE
description: LSE clock selected
value: 3
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK1
- name: PCLK2
description: PCLK clock selected
value: 0
- name: SYS
@ -2322,22 +2288,7 @@ enum/USART1SEL:
- name: LSE
description: LSE clock selected
value: 3
enum/USART2SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK clock selected
value: 0
- name: SYS
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI clock selected
value: 2
- name: LSE
description: LSE clock selected
value: 3
enum/USART3SEL:
enum/USARTSEL:
bit_size: 2
variants:
- name: PCLK1

57
data/registers/rcc_l4plus.yaml
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@ -1099,22 +1099,22 @@ fieldset/CCIPR:
description: USART2 clock source selection
bit_offset: 2
bit_size: 2
enum: USART2SEL
enum: USARTSEL
- name: USART3SEL
description: USART3 clock source selection
bit_offset: 4
bit_size: 2
enum: USART3SEL
enum: USARTSEL
- name: UART4SEL
description: UART4 clock source selection
bit_offset: 6
bit_size: 2
enum: UART4SEL
enum: USARTSEL
- name: UART5SEL
description: UART5 clock source selection
bit_offset: 8
bit_size: 2
enum: UART5SEL
enum: USARTSEL
- name: LPUART1SEL
description: LPUART1 clock source selection
bit_offset: 10
@ -2461,40 +2461,10 @@ enum/SW:
- name: PLL1_R
description: PLL selected as system clock
value: 3
enum/UART4SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK clock selected
value: 0
- name: SYS
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI clock selected
value: 2
- name: LSE
description: LSE clock selected
value: 3
enum/UART5SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK clock selected
value: 0
- name: SYS
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI clock selected
value: 2
- name: LSE
description: LSE clock selected
value: 3
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK1
- name: PCLK2
description: PCLK clock selected
value: 0
- name: SYS
@ -2506,22 +2476,7 @@ enum/USART1SEL:
- name: LSE
description: LSE clock selected
value: 3
enum/USART2SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK clock selected
value: 0
- name: SYS
description: SYSCLK clock selected
value: 1
- name: HSI
description: HSI clock selected
value: 2
- name: LSE
description: LSE clock selected
value: 3
enum/USART3SEL:
enum/USARTSEL:
bit_size: 2
variants:
- name: PCLK1

118
data/registers/rcc_u5.yaml
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@ -1551,7 +1551,7 @@ fieldset/CCIPR1:
description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 0
bit_size: 2
enum: USARTSEL
enum: USART1SEL
- name: USART2SEL
description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 2
@ -1566,12 +1566,12 @@ fieldset/CCIPR1:
description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 6
bit_size: 2
enum: UARTSEL
enum: USARTSEL
- name: UART5SEL
description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 8
bit_size: 2
enum: UARTSEL
enum: USARTSEL
- name: I2C1SEL
description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 10
@ -1591,17 +1591,17 @@ fieldset/CCIPR1:
description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 16
bit_size: 2
enum: SPISEL
enum: SPI2SEL
- name: LPTIM2SEL
description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1."
bit_offset: 18
bit_size: 2
enum: LPTIMSEL
enum: LPTIM2SEL
- name: SPI1SEL
description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 20
bit_size: 2
enum: SPISEL
enum: SPI1SEL
- name: SYSTICKSEL
description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry."
bit_offset: 22
@ -1702,17 +1702,17 @@ fieldset/CCIPR3:
description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK."
bit_offset: 0
bit_size: 3
enum: LPUARTSEL
enum: LPUSARTSEL
- name: SPI3SEL
description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."
bit_offset: 3
bit_size: 2
enum: SPISEL
enum: SPI3SEL
- name: I2C3SEL
description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."
bit_offset: 6
bit_size: 2
enum: I2CSEL
enum: I2C3SEL
- name: LPTIM34SEL
description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."
bit_offset: 8
@ -2451,7 +2451,7 @@ enum/ADCDACSEL:
enum/ADFSEL:
bit_size: 3
variants:
- name: HCLK1
- name: HCLK3
description: HCLK selected
value: 0
- name: PLL1_P
@ -2568,6 +2568,21 @@ enum/HSPISEL:
- name: PLL3_R
description: PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz
value: 3
enum/I2C3SEL:
bit_size: 2
variants:
- name: PCLK3
description: PCLK3 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: MSIK
description: MSIK selected
value: 3
enum/I2CSEL:
bit_size: 2
variants:
@ -2598,7 +2613,7 @@ enum/ICLKSEL:
- name: MSIK
description: MSIK clock selected
value: 3
enum/LPTIMSEL:
enum/LPTIM2SEL:
bit_size: 2
variants:
- name: PCLK1
@ -2613,7 +2628,22 @@ enum/LPTIMSEL:
- name: LSE
description: LSE selected
value: 3
enum/LPUARTSEL:
enum/LPTIMSEL:
bit_size: 2
variants:
- name: PCLK3
description: PCLK3 selected
value: 0
- name: LSI
description: LSI selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
enum/LPUSARTSEL:
bit_size: 3
variants:
- name: PCLK3
@ -4336,7 +4366,7 @@ enum/SECURITY:
- name: SECURE
description: secure
value: 1
enum/SPISEL:
enum/SPI1SEL:
bit_size: 2
variants:
- name: PCLK2
@ -4351,6 +4381,36 @@ enum/SPISEL:
- name: MSIK
description: MSIK selected
value: 3
enum/SPI2SEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK2 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: MSIK
description: MSIK selected
value: 3
enum/SPI3SEL:
bit_size: 2
variants:
- name: PCLK3
description: PCLK2 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: MSIK
description: MSIK selected
value: 3
enum/STOPKERWUCK:
bit_size: 1
variants:
@ -4414,22 +4474,7 @@ enum/TIMICSEL:
- name: HSI256_MSIK1024_MSIK4
description: HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 7
enum/UARTSEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK1 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
enum/USARTSEL:
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK2
@ -4444,3 +4489,18 @@ enum/USARTSEL:
- name: LSE
description: LSE selected
value: 3
enum/USARTSEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK1 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3

2
data/registers/rcc_wb.yaml
View File

@ -2368,7 +2368,7 @@ enum/SW:
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK1
- name: PCLK2
description: PCLK clock selected
value: 0
- name: SYS

78
data/registers/rcc_wba.yaml
View File

@ -765,7 +765,7 @@ fieldset/CCIPR1:
description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 0
bit_size: 2
enum: USARTSEL
enum: USART1SEL
- name: USART2SEL
description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 2
@ -775,17 +775,17 @@ fieldset/CCIPR1:
description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI."
bit_offset: 10
bit_size: 2
enum: I2CSEL
enum: I2C1SEL
- name: LPTIM2SEL
description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1."
bit_offset: 18
bit_size: 2
enum: LPTIMSEL
enum: LPTIM2SEL
- name: SPI1SEL
description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI."
bit_offset: 20
bit_size: 2
enum: SPISEL
enum: SPI1SEL
- name: SYSTICKSEL
description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry."
bit_offset: 22
@ -816,17 +816,17 @@ fieldset/CCIPR3:
description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI."
bit_offset: 3
bit_size: 2
enum: SPISEL
enum: SPI3SEL
- name: I2C3SEL
description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI"
bit_offset: 6
bit_size: 2
enum: I2CSEL
enum: I2C3SEL
- name: LPTIM1SEL
description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1."
bit_offset: 10
bit_size: 2
enum: LPTIMSEL
enum: LPTIM1SEL
- name: ADCSEL
description: "ADC4 kernel clock source selection\r These bits are used to select the ADC4 kernel clock source.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r others: reserved\r Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI."
bit_offset: 12
@ -1201,8 +1201,8 @@ fieldset/SECCFGR:
enum/ADCSEL:
bit_size: 3
variants:
- name: HCLK1
description: hclk1 clock selected
- name: HCLK4
description: hclk4 clock selected
value: 0
- name: SYS
description: SYSCLK selected
@ -1270,7 +1270,7 @@ enum/HSEPRE:
- name: Div2
description: HSE divided, SYSCLK = HSE/2
value: 1
enum/I2CSEL:
enum/I2C1SEL:
bit_size: 2
variants:
- name: PCLK1
@ -1282,10 +1282,37 @@ enum/I2CSEL:
- name: HSI
description: HSI selected
value: 2
enum/LPTIMSEL:
enum/I2C3SEL:
bit_size: 2
variants:
- name: PCLK7
description: pclk7 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
enum/LPTIM1SEL:
bit_size: 2
variants:
- name: PCLK7
description: pclk7 selected.
value: 0
- name: LSI
description: LSI selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
enum/LPTIM2SEL:
bit_size: 2
variants:
- name: PCLK1
description: pclk7 selected.
value: 0
- name: LSI
@ -1510,7 +1537,7 @@ enum/RTCSEL:
- name: HSE
description: HSE oscillator clock divided by 32 selected, and enabled
value: 3
enum/SPISEL:
enum/SPI1SEL:
bit_size: 2
variants:
- name: PCLK2
@ -1522,6 +1549,18 @@ enum/SPISEL:
- name: HSI
description: HSI selected
value: 2
enum/SPI3SEL:
bit_size: 2
variants:
- name: PCLK7
description: pclk2 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
enum/SW:
bit_size: 2
variants:
@ -1555,6 +1594,21 @@ enum/TIMICSEL:
- name: HSI_DIV_256
description: HSI/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 1
enum/USART1SEL:
bit_size: 2
variants:
- name: PCLK2
description: pclk2 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
enum/USARTSEL:
bit_size: 2
variants:

35
stm32-data-gen/src/rcc.rs
View File

@ -19,7 +19,13 @@ struct ParsedRcc {
/// name -> en/rst bit info
en_rst: HashMap<String, EnRst>,
/// name -> mux info
mux: HashMap<String, Mux>,
mux: HashMap<String, MuxInfo>,
}
#[derive(Debug)]
struct MuxInfo {
mux: Mux,
variants: Vec<String>,
}
#[derive(Debug)]
@ -166,9 +172,12 @@ impl ParsedRccs {
}
}
let val = Mux {
register: reg.to_ascii_lowercase(),
field: field.name.to_ascii_lowercase(),
let val = MuxInfo {
mux: Mux {
register: reg.to_ascii_lowercase(),
field: field.name.to_ascii_lowercase(),
},
variants: enumm.variants.iter().map(|v| v.name.to_ascii_lowercase()).collect(),
};
if mux.insert(peri.to_string(), val).is_some() {
@ -212,7 +221,7 @@ impl ParsedRccs {
};
// Timers are a bit special, they may have a x2 freq
let peri_clock = if regex!(r"^TIM\d+$").is_match(peri) {
let peri_clock = if regex!(r"^(HR)?TIM\d+$").is_match(peri) {
format!("{clock}_TIM")
} else {
clock.to_string()
@ -292,13 +301,27 @@ impl ParsedRccs {
let en_rst = get_with_fallback(peri_name, &rcc.en_rst, FALLBACKS)?;
let mux = get_with_fallback(peri_name, &rcc.mux, FALLBACKS);
let phclk = regex!("^[ph]clk");
if let Some(mux) = mux {
if phclk.is_match(&en_rst.clock) {
for v in &mux.variants {
if phclk.is_match(v) && v != &en_rst.clock {
panic!(
"rcc_{}: peripheral {} is on bus {} but mux {}.{} refers to {}",
rcc_version, peri_name, en_rst.clock, mux.mux.register, mux.mux.field, v
)
}
}
}
}
Some(peripheral::Rcc {
clock: en_rst.clock.clone(),
enable: en_rst.enable.clone(),
reset: en_rst.reset.clone(),
stop_mode: en_rst.stop_mode.clone(),
mux: mux.cloned(),
mux: mux.map(|m| m.mux.clone()),
})
}
}