guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Arrayify and cleanup DAC registers

Browse Source
This commit is contained in:
chemicstry 2022-08-04 02:34:19 +03:00
parent 40e1ece0d1
commit e1f8e76781
2 changed files with 204 additions and 371 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

236
data/registers/dac_v1.yaml
View File

@ -11,30 +11,27 @@ block/DAC:
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: SWTRIGR fieldset: SWTRIGR
- name: DHR12R1 - name: DHR12R
description: channel1 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
byte_offset: 8 byte_offset: 8
fieldset: DHR12R1 fieldset: DHR12R
- name: DHR12L1 array:
description: channel1 12-bit left aligned data holding register len: 2
stride: 12
- name: DHR12L
description: channel 12-bit left-aligned data holding register
byte_offset: 12 byte_offset: 12
fieldset: DHR12L1 fieldset: DHR12L
- name: DHR8R1 array:
description: channel1 8-bit right aligned data holding register len: 2
stride: 12
- name: DHR8R
description: channel 8-bit right-aligned data holding register
byte_offset: 16 byte_offset: 16
fieldset: DHR8R1 fieldset: DHR8R
- name: DHR12R2 array:
description: channel2 12-bit right aligned data holding register len: 2
byte_offset: 20 stride: 12
fieldset: DHR12R2
- name: DHR12L2
description: channel2 12-bit left aligned data holding register
byte_offset: 24
fieldset: DHR12L2
- name: DHR8R2
description: channel2 8-bit right-aligned data holding register
byte_offset: 28
fieldset: DHR8R2
- name: DHR12RD - name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
byte_offset: 32 byte_offset: 32
@ -47,16 +44,14 @@ block/DAC:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
byte_offset: 40 byte_offset: 40
fieldset: DHR8RD fieldset: DHR8RD
- name: DOR1 - name: DOR
description: channel1 data output register description: channel data output register
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: DOR1 fieldset: DOR
- name: DOR2 array:
description: channel2 data output register len: 2
byte_offset: 48 stride: 4
access: Read
fieldset: DOR2
- name: SR - name: SR
description: status register description: status register
byte_offset: 52 byte_offset: 52
@ -65,31 +60,28 @@ fieldset/CR:
description: control register description: control register
fields: fields:
- name: EN - name: EN
description: DAC channel1 enable description: DAC channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: EN
- name: BOFF - name: BOFF
description: DAC channel1 output buffer disable description: DAC channel output buffer disable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: BOFF
- name: TEN - name: TEN
description: DAC channel1 trigger enable description: DAC channel trigger enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: TEN
- name: TSEL - name: TSEL
description: DAC channel1 trigger selection description: DAC channel trigger selection
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
array: array:
@ -97,7 +89,7 @@ fieldset/CR:
stride: 16 stride: 16
enum: TSEL1 enum: TSEL1
- name: WAVE - name: WAVE
description: DAC channel1 noise/triangle wave generation enable description: DAC channel noise/triangle wave generation enable
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
array: array:
@ -105,202 +97,104 @@ fieldset/CR:
stride: 16 stride: 16
enum: WAVE enum: WAVE
- name: MAMP - name: MAMP
description: DAC channel1 mask/amplitude selector description: DAC channel mask/amplitude selector
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
array: array:
len: 2 len: 2
stride: 16 stride: 16
- name: DMAEN - name: DMAEN
description: DAC channel1 DMA enable description: DAC channel DMA enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: DMAEN
- name: DMAUDRIE - name: DMAUDRIE
description: DAC channel1 DMA Underrun Interrupt enable description: DAC channel DMA Underrun Interrupt enable
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: DMAUDRIE fieldset/DHR12L:
fieldset/DHR12L1: description: channel 12-bit left-aligned data holding register
description: channel1 12-bit left aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4
bit_size: 12
fieldset/DHR12L2:
description: channel2 12-bit left aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
fieldset/DHR12LD: fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
- name: DACC2DHR array:
description: DAC channel2 12-bit left-aligned data len: 2
bit_offset: 20 stride: 16
bit_size: 12 fieldset/DHR12R:
fieldset/DHR12R1: description: channel 12-bit right-aligned data holding register
description: channel1 12-bit right-aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0
bit_size: 12
fieldset/DHR12R2:
description: channel2 12-bit right aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/DHR12RD: fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: DACC2DHR array:
description: DAC channel2 12-bit right-aligned data len: 2
bit_offset: 16 stride: 16
bit_size: 12 fieldset/DHR8R:
fieldset/DHR8R1: description: channel 8-bit right-aligned data holding register
description: channel1 8-bit right aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0
bit_size: 8
fieldset/DHR8R2:
description: channel2 8-bit right-aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/DHR8RD: fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: DACC2DHR array:
description: DAC channel2 8-bit right-aligned data len: 2
bit_offset: 8 stride: 8
bit_size: 8 fieldset/DOR:
fieldset/DOR1: description: channel data output register
description: channel1 data output register
fields: fields:
- name: DACC1DOR - name: DOR
description: DAC channel1 data output description: DAC channel data output
bit_offset: 0
bit_size: 12
fieldset/DOR2:
description: channel2 data output register
fields:
- name: DACC2DOR
description: DAC channel2 data output
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: DMAUDR - name: DMAUDR
description: DAC channel1 DMA underrun flag description: DAC channel DMA underrun flag
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 16 stride: 16
enum: DMAUDR
fieldset/SWTRIGR: fieldset/SWTRIGR:
description: software trigger register description: software trigger register
fields: fields:
- name: SWTRIG - name: SWTRIG
description: DAC channel1 software trigger description: DAC channel software trigger
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum: SWTRIG
enum/BOFF:
bit_size: 1
variants:
- name: Enabled
description: DAC channel X output buffer enabled
value: 0
- name: Disabled
description: DAC channel X output buffer disabled
value: 1
enum/DMAEN:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X DMA mode disabled
value: 0
- name: Enabled
description: DAC channel X DMA mode enabled
value: 1
enum/DMAUDR:
bit_size: 1
variants:
- name: NoUnderrun
description: No DMA underrun error condition occurred for DAC channel X
value: 0
- name: Underrun
description: DMA underrun error condition occurred for DAC channel X
value: 1
enum/DMAUDRIE:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X DMA Underrun Interrupt disabled
value: 0
- name: Enabled
description: DAC channel X DMA Underrun Interrupt enabled
value: 1
enum/EN:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X disabled
value: 0
- name: Enabled
description: DAC channel X enabled
value: 1
enum/SWTRIG:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X software trigger disabled
value: 0
- name: Enabled
description: DAC channel X software trigger enabled
value: 1
enum/TEN:
bit_size: 1
variants:
- name: Disabled
description: DAC channel X trigger disabled
value: 0
- name: Enabled
description: DAC channel X trigger enabled
value: 1
enum/TSEL1: enum/TSEL1:
bit_size: 3 bit_size: 3
variants: variants:

339
data/registers/dac_v2.yaml
View File

@ -11,30 +11,27 @@ block/DAC:
byte_offset: 4 byte_offset: 4
access: Write access: Write
fieldset: SWTRIGR fieldset: SWTRIGR
- name: DHR12R1 - name: DHR12R
description: channel1 12-bit right-aligned data holding register description: channel 12-bit right-aligned data holding register
byte_offset: 8 byte_offset: 8
fieldset: DHR12R1 fieldset: DHR12R
- name: DHR12L1 array:
description: channel1 12-bit left-aligned data holding register len: 2
stride: 12
- name: DHR12L
description: channel 12-bit left-aligned data holding register
byte_offset: 12 byte_offset: 12
fieldset: DHR12L1 fieldset: DHR12L
- name: DHR8R1 array:
description: channel1 8-bit right-aligned data holding register len: 2
stride: 12
- name: DHR8R
description: channel 8-bit right-aligned data holding register
byte_offset: 16 byte_offset: 16
fieldset: DHR8R1 fieldset: DHR8R
- name: DHR12R2 array:
description: channel2 12-bit right aligned data holding register len: 2
byte_offset: 20 stride: 12
fieldset: DHR12R2
- name: DHR12L2
description: channel2 12-bit left aligned data holding register
byte_offset: 24
fieldset: DHR12L2
- name: DHR8R2
description: channel2 8-bit right-aligned data holding register
byte_offset: 28
fieldset: DHR8R2
- name: DHR12RD - name: DHR12RD
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
byte_offset: 32 byte_offset: 32
@ -47,16 +44,14 @@ block/DAC:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
byte_offset: 40 byte_offset: 40
fieldset: DHR8RD fieldset: DHR8RD
- name: DOR1 - name: DOR
description: channel1 data output register description: channel data output register
byte_offset: 44 byte_offset: 44
access: Read access: Read
fieldset: DOR1 fieldset: DOR
- name: DOR2 array:
description: channel2 data output register len: 2
byte_offset: 48 stride: 4
access: Read
fieldset: DOR2
- name: SR - name: SR
description: status register description: status register
byte_offset: 52 byte_offset: 52
@ -70,13 +65,12 @@ block/DAC:
byte_offset: 60 byte_offset: 60
fieldset: MCR fieldset: MCR
- name: SHSR1 - name: SHSR1
description: Sample and Hold sample time register 1 description: Sample and Hold sample time register
byte_offset: 64 byte_offset: 64
fieldset: SHSR1 fieldset: SHSR
- name: SHSR2 array:
description: Sample and Hold sample time register 2 len: 2
byte_offset: 68 stride: 4
fieldset: SHSR2
- name: SHHR - name: SHHR
description: Sample and Hold hold time register description: Sample and Hold hold time register
byte_offset: 72 byte_offset: 72
@ -99,248 +93,193 @@ fieldset/CCR:
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: EN1 - name: EN
description: DAC channel1 enable description: DAC channel enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: TEN1 array:
description: DAC channel1 trigger enable len: 2
stride: 16
- name: TEN
description: DAC channel trigger enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: TSEL1 array:
description: DAC channel1 trigger selection len: 2
stride: 16
- name: TSEL
description: DAC channel trigger selection
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
array:
len: 2
stride: 16
enum: TSEL1 enum: TSEL1
- name: WAVE1 - name: WAVE
description: DAC channel1 noise/triangle wave generation enable description: DAC channel noise/triangle wave generation enable
bit_offset: 6 bit_offset: 6
bit_size: 2 bit_size: 2
array:
len: 2
stride: 16
enum: WAVE enum: WAVE
- name: MAMP1 - name: MAMP
description: DAC channel1 mask/amplitude selector description: DAC channel mask/amplitude selector
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
- name: DMAEN1 array:
description: DAC channel1 DMA enable len: 2
stride: 16
- name: DMAEN
description: DAC channel DMA enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DMAUDRIE1 array:
description: DAC channel1 DMA Underrun Interrupt enable len: 2
stride: 16
- name: DMAUDRIE
description: DAC channel DMA Underrun Interrupt enable
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: CEN1 array:
description: DAC Channel 1 calibration enable len: 2
stride: 16
- name: CEN
description: DAC channel calibration enable
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: EN2 array:
description: DAC channel2 enable len: 2
bit_offset: 16 stride: 16
bit_size: 1 fieldset/DHR12L:
- name: TEN2 description: channel 12-bit left-aligned data holding register
description: DAC channel2 trigger enable
bit_offset: 18
bit_size: 1
- name: TSEL2
description: DAC channel2 trigger selection
bit_offset: 19
bit_size: 3
enum: TSEL2
- name: WAVE2
description: DAC channel2 noise/triangle wave generation enable
bit_offset: 22
bit_size: 2
enum: WAVE
- name: MAMP2
description: DAC channel2 mask/amplitude selector
bit_offset: 24
bit_size: 4
- name: DMAEN2
description: DAC channel2 DMA enable
bit_offset: 28
bit_size: 1
- name: DMAUDRIE2
description: DAC channel2 DMA underrun interrupt enable
bit_offset: 29
bit_size: 1
- name: CEN2
description: DAC Channel 2 calibration enable
bit_offset: 30
bit_size: 1
fieldset/DHR12L1:
description: channel1 12-bit left-aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4
bit_size: 12
fieldset/DHR12L2:
description: channel2 12-bit left aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
fieldset/DHR12LD: fieldset/DHR12LD:
description: DUAL DAC 12-bit left aligned data holding register description: DUAL DAC 12-bit left aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit left-aligned data description: DAC channel 12-bit left-aligned data
bit_offset: 4 bit_offset: 4
bit_size: 12 bit_size: 12
- name: DACC2DHR array:
description: DAC channel2 12-bit left-aligned data len: 2
bit_offset: 20 stride: 16
bit_size: 12 fieldset/DHR12R:
fieldset/DHR12R1: description: channel 12-bit right-aligned data holding register
description: channel1 12-bit right-aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0
bit_size: 12
fieldset/DHR12R2:
description: channel2 12-bit right aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/DHR12RD: fieldset/DHR12RD:
description: Dual DAC 12-bit right-aligned data holding register description: Dual DAC 12-bit right-aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 12-bit right-aligned data description: DAC channel 12-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
- name: DACC2DHR array:
description: DAC channel2 12-bit right-aligned data len: 2
bit_offset: 16 stride: 16
bit_size: 12 fieldset/DHR8R:
fieldset/DHR8R1: description: channel 8-bit right-aligned data holding register
description: channel1 8-bit right-aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0
bit_size: 8
fieldset/DHR8R2:
description: channel2 8-bit right-aligned data holding register
fields:
- name: DACC2DHR
description: DAC channel2 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
fieldset/DHR8RD: fieldset/DHR8RD:
description: DUAL DAC 8-bit right aligned data holding register description: DUAL DAC 8-bit right aligned data holding register
fields: fields:
- name: DACC1DHR - name: DHR
description: DAC channel1 8-bit right-aligned data description: DAC channel 8-bit right-aligned data
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: DACC2DHR array:
description: DAC channel2 8-bit right-aligned data len: 2
bit_offset: 8 stride: 8
bit_size: 8 fieldset/DOR:
fieldset/DOR1: description: channel data output register
description: channel1 data output register
fields: fields:
- name: DACC1DOR - name: DOR
description: DAC channel1 data output description: DAC channel data output
bit_offset: 0
bit_size: 12
fieldset/DOR2:
description: channel2 data output register
fields:
- name: DACC2DOR
description: DAC channel2 data output
bit_offset: 0 bit_offset: 0
bit_size: 12 bit_size: 12
fieldset/MCR: fieldset/MCR:
description: mode control register description: mode control register
fields: fields:
- name: MODE1 - name: MODE
description: DAC Channel 1 mode description: DAC channel mode
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
- name: MODE2 array:
description: DAC Channel 2 mode len: 2
bit_offset: 16 stride: 16
bit_size: 3
fieldset/SHHR: fieldset/SHHR:
description: Sample and Hold hold time register description: Sample and Hold hold time register
fields: fields:
- name: THOLD1 - name: THOLD
description: DAC Channel 1 hold Time description: DAC channel hold Time
bit_offset: 0 bit_offset: 0
bit_size: 10 bit_size: 10
- name: THOLD2 array:
description: DAC Channel 2 hold time len: 2
bit_offset: 16 stride: 16
bit_size: 10
fieldset/SHRR: fieldset/SHRR:
description: Sample and Hold refresh time register description: Sample and Hold refresh time register
fields: fields:
- name: TREFRESH1 - name: TREFRESH
description: DAC Channel 1 refresh Time description: DAC channel refresh Time
bit_offset: 0 bit_offset: 0
bit_size: 8 bit_size: 8
- name: TREFRESH2 array:
description: DAC Channel 2 refresh Time len: 2
bit_offset: 16 stride: 16
bit_size: 8 fieldset/SHSR:
fieldset/SHSR1: description: Sample and Hold sample time register
description: Sample and Hold sample time register 1
fields: fields:
- name: TSAMPLE1 - name: TSAMPLE
description: DAC Channel 1 sample Time description: DAC channel sample Time
bit_offset: 0
bit_size: 10
fieldset/SHSR2:
description: Sample and Hold sample time register 2
fields:
- name: TSAMPLE2
description: DAC Channel 2 sample Time
bit_offset: 0 bit_offset: 0
bit_size: 10 bit_size: 10
fieldset/SR: fieldset/SR:
description: status register description: status register
fields: fields:
- name: DMAUDR1 - name: DMAUDR
description: DAC channel1 DMA underrun flag description: DAC channel DMA underrun flag
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: CAL_FLAG1 array:
description: DAC Channel 1 calibration offset status len: 2
stride: 16
- name: CAL_FLAG
description: DAC channel calibration offset status
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
- name: BWST1 array:
description: DAC Channel 1 busy writing sample time flag len: 2
stride: 16
- name: BWST
description: DAC channel busy writing sample time flag
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
- name: DMAUDR2 array:
description: DAC channel2 DMA underrun flag len: 2
bit_offset: 29 stride: 16
bit_size: 1
- name: CAL_FLAG2
description: DAC Channel 2 calibration offset status
bit_offset: 30
bit_size: 1
- name: BWST2
description: DAC Channel 2 busy writing sample time flag
bit_offset: 31
bit_size: 1
fieldset/SWTRIGR: fieldset/SWTRIGR:
description: software trigger register description: software trigger register
fields: fields:
- name: SWTRIG1 - name: SWTRIG
description: DAC channel1 software trigger description: DAC channel software trigger
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: SWTRIG2 array:
description: DAC channel2 software trigger len: 2
bit_offset: 1 stride: 1
bit_size: 1
enum/TSEL1: enum/TSEL1:
bit_size: 3 bit_size: 3
variants: variants: