diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml
index bad21c3..27a3aa6 100644
--- a/data/registers/rcc_f4.yaml
+++ b/data/registers/rcc_f4.yaml
@@ -1793,10 +1793,10 @@ enum/CKDFSDMSEL:
 enum/CLK48SEL:
   bit_size: 1
   variants:
-  - name: PLL
+  - name: PLL1_Q
     description: 48MHz clock from PLL is selected
     value: 0
-  - name: PLLSAI
+  - name: PLLSAI1_Q
     description: 48MHz clock from PLLSAI is selected
     value: 1
 enum/DSISEL:
@@ -1805,13 +1805,13 @@ enum/DSISEL:
   - name: DSI_PHY
     description: DSI-PHY used as DSI byte lane clock source (usual case)
     value: 0
-  - name: PLLR
+  - name: PLL1_R
     description: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
     value: 1
 enum/FMPICSEL:
   bit_size: 2
   variants:
-  - name: APB
+  - name: PCLK1
     description: APB clock selected as I2C clock
     value: 0
   - name: SYS
@@ -3446,10 +3446,10 @@ enum/SDIOSEL:
 enum/SPDIFRXSEL:
   bit_size: 1
   variants:
-  - name: PLL
+  - name: PLL1_R
     description: SPDIF-Rx clock from PLL is selected
     value: 0
-  - name: PLLI2S
+  - name: PLLI2S1_P
     description: SPDIF-Rx clock from PLLI2S is selected
     value: 1
 enum/SPREADSEL:
diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml
index 544d5f1..b2e867d 100644
--- a/data/registers/rcc_f410.yaml
+++ b/data/registers/rcc_f410.yaml
@@ -795,7 +795,7 @@ fieldset/SSCGR:
 enum/FMPICSEL:
   bit_size: 2
   variants:
-  - name: APB
+  - name: PCLK1
     description: APB clock selected as I2C clock
     value: 0
   - name: SYS
diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml
index 7563d19..aeed9c3 100644
--- a/data/registers/rcc_f7.yaml
+++ b/data/registers/rcc_f7.yaml
@@ -1577,7 +1577,7 @@ fieldset/DCKCFGR2:
     description: 48MHz clock source selection
     bit_offset: 27
     bit_size: 1
-    enum: CKMSEL
+    enum: CLK48SEL
   - name: SDMMC1SEL
     description: SDMMC1 clock source selection
     bit_offset: 28
@@ -1710,13 +1710,13 @@ enum/CECSEL:
   - name: HSI_Div488
     description: HSI divided by 488 clock is selected as HDMI-CEC clock
     value: 1
-enum/CKMSEL:
+enum/CLK48SEL:
   bit_size: 1
   variants:
-  - name: PLL
+  - name: PLL1_Q
     description: 48MHz clock from PLL is selected
     value: 0
-  - name: PLLSAI
+  - name: PLLSAI1_P
     description: 48MHz clock from PLLSAI is selected
     value: 1
 enum/DFSDMSEL:
@@ -1734,7 +1734,7 @@ enum/DSISEL:
   - name: DSI_PHY
     description: DSI-PHY used as DSI byte lane clock source (usual case)
     value: 0
-  - name: PLLR
+  - name: PLL1_R
     description: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
     value: 1
 enum/HPRE:
@@ -1770,7 +1770,7 @@ enum/HPRE:
 enum/ICSEL:
   bit_size: 2
   variants:
-  - name: APB
+  - name: PCLK1
     description: APB clock selected as I2C clock
     value: 0
   - name: SYS
@@ -3081,10 +3081,10 @@ enum/RTCSEL:
 enum/SAISEL:
   bit_size: 2
   variants:
-  - name: PLLSAI
+  - name: PLLSAI1_Q
     description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
     value: 0
-  - name: PLLI2S
+  - name: PLLI2S1_Q
     description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
     value: 1
   - name: AFIF
diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 5f83f48..5fb0b77 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -92,6 +92,10 @@ impl PeripheralToClock {
             "PER",
             "CLK48",
             // TODO: variants to cleanup
+            "AFIF",
+            "HSI_HSE",
+            "DSI_PHY",
+            "HSI_Div488",
             "SAI1_EXTCLK",
             "SAI2_EXTCLK",
             "B_0x0",
@@ -104,6 +108,10 @@ impl PeripheralToClock {
             "DSIPHY",
             "ICLK",
             "DCLK",
+            "I2S1",
+            "I2S2",
+            "SAI1",
+            "SAI2",
             "HSI256_MSIS1024_MSIS4",
             "HSI256_MSIS1024_MSIK4",
             "HSI256_MSIK1024_MSIS4",
@@ -177,7 +185,7 @@ impl PeripheralToClock {
                 let mut family_muxes = HashMap::new();
                 for (reg, body) in &ir.fieldsets {
                     let key = format!("fieldset/{reg}");
-                    if regex!(r"^fieldset/CCIPR\d?$").captures(&key).is_some() {
+                    if regex!(r"^fieldset/(CCIPR|DCKCFGR)\d?$").captures(&key).is_some() {
                         for field in &body.fields {
                             if let Some(peri) = field.name.strip_suffix("SEL") {
                                 check_mux(reg, &field.name)?;
@@ -330,6 +338,7 @@ impl PeripheralToClock {
             ("DAC", &["DAC1"]),
             ("DAC1", &["DAC12", "DAC"]),
             ("DAC2", &["DAC12", "DAC"]),
+            ("ETH", &["ETHMAC", "ETH1MAC"]),
         ];
 
         let clocks = self.0.get(rcc_block)?;