diff --git a/data/registers/adccommon_h50.yaml b/data/registers/adccommon_h50.yaml
index 2d14a37..b30aabb 100644
--- a/data/registers/adccommon_h50.yaml
+++ b/data/registers/adccommon_h50.yaml
@@ -16,11 +16,9 @@ block/ADC_COMMON:
   - name: IPDR
     description: identification register
     byte_offset: 248
-    fieldset: IPDR
   - name: SIDR
     description: size identification register
     byte_offset: 252
-    fieldset: SIDR
 fieldset/CCR:
   description: common control register
   fields:
@@ -28,10 +26,12 @@ fieldset/CCR:
     description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
     bit_offset: 16
     bit_size: 2
+    enum: CKMODE
   - name: PRESC
     description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
     bit_offset: 18
     bit_size: 4
+    enum: PRESC
   - name: VREFEN
     description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
     bit_offset: 22
@@ -63,6 +63,7 @@ fieldset/HWCFGR0:
     description: Idle value for non-selected channels
     bit_offset: 12
     bit_size: 4
+    enum: IDLEVALUE
 fieldset/VERR:
   description: version register
   fields:
@@ -74,17 +75,66 @@ fieldset/VERR:
     description: Major revision These bits returns the ADC IP major revision
     bit_offset: 4
     bit_size: 4
-fieldset/IPDR:
-  description: identification register
-  fields:
-  - name: ID
-    description: 'Peripheral identifier These bits returns the ADC identifier. ID[31:0] = 0x0011 0006: c7amba_aditf5_90_v1.'
-    bit_offset: 0
-    bit_size: 32
-fieldset/SIDR:
-  description: size identification register
-  fields:
-  - name: SID
-    description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.'
-    bit_offset: 0
-    bit_size: 32
+enum/CKMODE:
+  bit_size: 2
+  variants:
+  - name: Asynchronous
+    description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
+    value: 0
+  - name: SyncDiv1
+    description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
+    value: 1
+  - name: SyncDiv2
+    description: Use AHB clock rcc_hclk3 divided by 2
+    value: 2
+  - name: SyncDiv4
+    description: Use AHB clock rcc_hclk3 divided by 4
+    value: 3
+enum/IDLEVALUE:
+  bit_size: 4
+  variants:
+  - name: H13
+    description: Dummy channel selection is 0x13
+    value: 0
+  - name: H1F
+    description: Dummy channel selection is 0x1F
+    value: 1
+enum/PRESC:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: adc_ker_ck_input not divided
+    value: 0
+  - name: Div2
+    description: adc_ker_ck_input divided by 2
+    value: 1
+  - name: Div4
+    description: adc_ker_ck_input divided by 4
+    value: 2
+  - name: Div6
+    description: adc_ker_ck_input divided by 6
+    value: 3
+  - name: Div8
+    description: adc_ker_ck_input divided by 8
+    value: 4
+  - name: Div10
+    description: adc_ker_ck_input divided by 10
+    value: 5
+  - name: Div12
+    description: adc_ker_ck_input divided by 12
+    value: 6
+  - name: Div16
+    description: adc_ker_ck_input divided by 16
+    value: 7
+  - name: Div32
+    description: adc_ker_ck_input divided by 32
+    value: 8
+  - name: Div64
+    description: adc_ker_ck_input divided by 64
+    value: 9
+  - name: Div128
+    description: adc_ker_ck_input divided by 128
+    value: 10
+  - name: Div256
+    description: adc_ker_ck_input divided by 256
+    value: 11