diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml
index 1bb0f7e..286ff85 100644
--- a/data/registers/rcc_f3.yaml
+++ b/data/registers/rcc_f3.yaml
@@ -61,6 +61,10 @@ fieldset/AHBENR:
       description: DMA1 clock enable
       bit_offset: 0
       bit_size: 1
+    - name: DMA2EN
+      description: DMA2 clock enable
+      bit_offset: 1
+      bit_size: 1
     - name: SRAMEN
       description: SRAM interface clock enable
       bit_offset: 2
@@ -69,10 +73,18 @@ fieldset/AHBENR:
       description: FLITF clock enable
       bit_offset: 4
       bit_size: 1
+    - name: FMCEN
+      description: FMC clock enable
+      bit_offset: 5
+      bit_size: 1
     - name: CRCEN
       description: CRC clock enable
       bit_offset: 6
       bit_size: 1
+    - name: GPIOHEN
+      description: IO port H clock enable
+      bit_offset: 16
+      bit_size: 1
     - name: GPIOAEN
       description: I/O port A clock enable
       bit_offset: 17
@@ -89,14 +101,26 @@ fieldset/AHBENR:
       description: I/O port D clock enable
       bit_offset: 20
       bit_size: 1
+    - name: GPIOEEN
+      description: I/O port E clock enable
+      bit_offset: 21
+      bit_size: 1
     - name: GPIOFEN
       description: I/O port F clock enable
       bit_offset: 22
       bit_size: 1
+    - name: GPIOGEN
+      description: IO port G clock enable
+      bit_offset: 23
+      bit_size: 1
     - name: TSCEN
       description: Touch sensing controller clock enable
       bit_offset: 24
       bit_size: 1
+    - name: ADC1EN
+      description: ADC 1
+      bit_offset: 28
+      bit_size: 1
     - name: ADC12EN
       description: ADC1 and ADC2 clock enable
       bit_offset: 28
@@ -108,6 +132,14 @@ fieldset/AHBENR:
 fieldset/AHBRSTR:
   description: AHB peripheral reset register
   fields:
+    - name: FMCRST
+      description: FMC reset
+      bit_offset: 5
+      bit_size: 1
+    - name: GPIOHRST
+      description: IO port H reset
+      bit_offset: 16
+      bit_size: 1
     - name: GPIOARST
       description: I/O port A reset
       bit_offset: 17
@@ -124,18 +156,34 @@ fieldset/AHBRSTR:
       description: I/O port D reset
       bit_offset: 20
       bit_size: 1
+    - name: GPIOERST
+      description: I/O port E reset
+      bit_offset: 21
+      bit_size: 1
     - name: GPIOFRST
       description: I/O port F reset
       bit_offset: 22
       bit_size: 1
+    - name: GPIOGRST
+      description: IO port G reset
+      bit_offset: 23
+      bit_size: 1
     - name: TSCRST
       description: Touch sensing controller reset
       bit_offset: 24
       bit_size: 1
+    - name: ADC1RST
+      description: ADC1 reset
+      bit_offset: 28
+      bit_size: 1
     - name: ADC12RST
       description: ADC1 and ADC2 reset
       bit_offset: 28
       bit_size: 1
+    - name: ADC34RST
+      description: ADC3 and ADC4 reset
+      bit_offset: 29
+      bit_size: 1
 fieldset/APB1ENR:
   description: APB1 peripheral clock enable register (RCC_APB1ENR)
   fields:
@@ -147,6 +195,14 @@ fieldset/APB1ENR:
       description: Timer 3 clock enable
       bit_offset: 1
       bit_size: 1
+    - name: TIM4EN
+      description: Timer 4 clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: TIM5EN
+      description: Timer 5 clock enable
+      bit_offset: 3
+      bit_size: 1
     - name: TIM6EN
       description: Timer 6 clock enable
       bit_offset: 4
@@ -155,22 +211,62 @@ fieldset/APB1ENR:
       description: Timer 7 clock enable
       bit_offset: 5
       bit_size: 1
+    - name: TIM12EN
+      description: Timer 12 clock enable
+      bit_offset: 6
+      bit_size: 1
+    - name: TIM13EN
+      description: Timer 13 clock enable
+      bit_offset: 7
+      bit_size: 1
+    - name: TIM14EN
+      description: Timer 14 clock enable
+      bit_offset: 8
+      bit_size: 1
+    - name: TIM18EN
+      description: Timer 18 clock enable
+      bit_offset: 9
+      bit_size: 1
     - name: WWDGEN
       description: Window watchdog clock enable
       bit_offset: 11
       bit_size: 1
+    - name: SPI2EN
+      description: SPI 2 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: SPI3EN
+      description: SPI 3 clock enable
+      bit_offset: 15
+      bit_size: 1
     - name: USART2EN
       description: USART 2 clock enable
       bit_offset: 17
       bit_size: 1
     - name: USART3EN
-      description: USART3 clock enable
+      description: USART 3 clock enable
       bit_offset: 18
       bit_size: 1
+    - name: UART4EN
+      description: UART4 clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: UART5EN
+      description: UART5 clock enable
+      bit_offset: 20
+      bit_size: 1
     - name: I2C1EN
       description: I2C 1 clock enable
       bit_offset: 21
       bit_size: 1
+    - name: I2C2EN
+      description: I2C 2 clock enable
+      bit_offset: 22
+      bit_size: 1
+    - name: USBEN
+      description: USB clock enable
+      bit_offset: 23
+      bit_size: 1
     - name: CANEN
       description: CAN clock enable
       bit_offset: 25
@@ -187,6 +283,14 @@ fieldset/APB1ENR:
       description: DAC interface clock enable
       bit_offset: 29
       bit_size: 1
+    - name: I2C3EN
+      description: I2C3 clock enable
+      bit_offset: 30
+      bit_size: 1
+    - name: CECEN
+      description: HDMI CEC interface clock enable
+      bit_offset: 30
+      bit_size: 1
 fieldset/APB1RSTR:
   description: APB1 peripheral reset register (RCC_APB1RSTR)
   fields:
@@ -198,6 +302,14 @@ fieldset/APB1RSTR:
       description: Timer 3 reset
       bit_offset: 1
       bit_size: 1
+    - name: TIM4RST
+      description: Timer 14 reset
+      bit_offset: 2
+      bit_size: 1
+    - name: TIM5RST
+      description: Timer 5 reset
+      bit_offset: 3
+      bit_size: 1
     - name: TIM6RST
       description: Timer 6 reset
       bit_offset: 4
@@ -206,10 +318,34 @@ fieldset/APB1RSTR:
       description: Timer 7 reset
       bit_offset: 5
       bit_size: 1
+    - name: TIM12RST
+      description: Timer 12 reset
+      bit_offset: 6
+      bit_size: 1
+    - name: TIM13RST
+      description: Timer 13 reset
+      bit_offset: 7
+      bit_size: 1
+    - name: TIM14RST
+      description: Timer 14 reset
+      bit_offset: 8
+      bit_size: 1
+    - name: TIM18RST
+      description: Timer 18 reset
+      bit_offset: 9
+      bit_size: 1
     - name: WWDGRST
       description: Window watchdog reset
       bit_offset: 11
       bit_size: 1
+    - name: SPI2RST
+      description: SPI2 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: SPI3RST
+      description: SPI3 reset
+      bit_offset: 15
+      bit_size: 1
     - name: USART2RST
       description: USART 2 reset
       bit_offset: 17
@@ -218,10 +354,26 @@ fieldset/APB1RSTR:
       description: USART3 reset
       bit_offset: 18
       bit_size: 1
+    - name: UART4RST
+      description: UART 4 reset
+      bit_offset: 19
+      bit_size: 1
+    - name: UART5RST
+      description: UART 5 reset
+      bit_offset: 20
+      bit_size: 1
     - name: I2C1RST
       description: I2C1 reset
       bit_offset: 21
       bit_size: 1
+    - name: I2C2RST
+      description: I2C2 reset
+      bit_offset: 22
+      bit_size: 1
+    - name: USBRST
+      description: USB reset
+      bit_offset: 23
+      bit_size: 1
     - name: CANRST
       description: CAN reset
       bit_offset: 25
@@ -238,6 +390,14 @@ fieldset/APB1RSTR:
       description: DAC interface reset
       bit_offset: 29
       bit_size: 1
+    - name: I2C3RST
+      description: I2C3 reset
+      bit_offset: 30
+      bit_size: 1
+    - name: CECRST
+      description: HDMI CEC reset
+      bit_offset: 30
+      bit_size: 1
 fieldset/APB2ENR:
   description: APB2 peripheral clock enable register (RCC_APB2ENR)
   fields:
@@ -245,6 +405,10 @@ fieldset/APB2ENR:
       description: SYSCFG clock enable
       bit_offset: 0
       bit_size: 1
+    - name: ADCEN
+      description: ADC 1 interface clock enable
+      bit_offset: 9
+      bit_size: 1
     - name: TIM1EN
       description: TIM1 Timer clock enable
       bit_offset: 11
@@ -253,10 +417,18 @@ fieldset/APB2ENR:
       description: SPI 1 clock enable
       bit_offset: 12
       bit_size: 1
+    - name: TIM8EN
+      description: TIM8 Timer clock enable
+      bit_offset: 13
+      bit_size: 1
     - name: USART1EN
       description: USART1 clock enable
       bit_offset: 14
       bit_size: 1
+    - name: SPI4EN
+      description: SPI4 clock enable
+      bit_offset: 15
+      bit_size: 1
     - name: TIM15EN
       description: TIM15 timer clock enable
       bit_offset: 16
@@ -269,6 +441,30 @@ fieldset/APB2ENR:
       description: TIM17 timer clock enable
       bit_offset: 18
       bit_size: 1
+    - name: TIM19EN
+      description: TIM19 timer clock enable
+      bit_offset: 19
+      bit_size: 1
+    - name: TIM20EN
+      description: TIM20 timer clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: DBGMCUEN
+      description: MCU debug module clock enable
+      bit_offset: 22
+      bit_size: 1
+    - name: SDADC1EN
+      description: SDADC1 (Sigma Delta ADC 1) clock enable
+      bit_offset: 24
+      bit_size: 1
+    - name: SDADC2EN
+      description: SDADC2 (Sigma Delta ADC 2) clock enable
+      bit_offset: 25
+      bit_size: 1
+    - name: SDADC3EN
+      description: SDADC3 (Sigma Delta ADC 3) clock enable
+      bit_offset: 26
+      bit_size: 1
     - name: HRTIM1EN
       description: High Resolution Timer 1 clock enable
       bit_offset: 29
@@ -280,6 +476,10 @@ fieldset/APB2RSTR:
       description: SYSCFG and COMP reset
       bit_offset: 0
       bit_size: 1
+    - name: ADCRST
+      description: ADC interface reset
+      bit_offset: 9
+      bit_size: 1
     - name: TIM1RST
       description: TIM1 timer reset
       bit_offset: 11
@@ -288,10 +488,18 @@ fieldset/APB2RSTR:
       description: SPI 1 reset
       bit_offset: 12
       bit_size: 1
+    - name: TIM8RST
+      description: TIM8 timer reset
+      bit_offset: 13
+      bit_size: 1
     - name: USART1RST
       description: USART1 reset
       bit_offset: 14
       bit_size: 1
+    - name: SPI4RST
+      description: SPI4 reset
+      bit_offset: 15
+      bit_size: 1
     - name: TIM15RST
       description: TIM15 timer reset
       bit_offset: 16
@@ -304,6 +512,26 @@ fieldset/APB2RSTR:
       description: TIM17 timer reset
       bit_offset: 18
       bit_size: 1
+    - name: TIM19RST
+      description: TIM19 timer reset
+      bit_offset: 19
+      bit_size: 1
+    - name: TIM20RST
+      description: TIM20 timer reset
+      bit_offset: 20
+      bit_size: 1
+    - name: SDADC1RST
+      description: SDADC1 (Sigma delta ADC 1) reset
+      bit_offset: 24
+      bit_size: 1
+    - name: SDADC2RST
+      description: SDADC2 (Sigma delta ADC 2) reset
+      bit_offset: 25
+      bit_size: 1
+    - name: SDADC3RST
+      description: SDADC3 (Sigma delta ADC 3) reset
+      bit_offset: 26
+      bit_size: 1
     - name: HRTIM1RST
       description: High Resolution Timer1 reset
       bit_offset: 29
@@ -371,6 +599,16 @@ fieldset/CFGR:
       bit_offset: 11
       bit_size: 3
       enum: PPRE
+    - name: ADCPRE
+      description: ADC prescaler
+      bit_offset: 14
+      bit_size: 2
+      enum: ADCPRE
+    - name: PLLSRC
+      description: PLL entry clock source
+      bit_offset: 15
+      bit_size: 2
+      enum: PLLSRC
     - name: PLLSRC
       description: PLL entry clock source
       bit_offset: 16
@@ -386,11 +624,26 @@ fieldset/CFGR:
       bit_offset: 18
       bit_size: 4
       enum: PLLMUL
+    - name: USBPRE
+      description: USB prescaler
+      bit_offset: 22
+      bit_size: 1
+      enum: USBPRE
+    - name: I2SSRC
+      description: I2S external clock source selection
+      bit_offset: 23
+      bit_size: 1
+      enum: ISSRC
     - name: MCO
       description: Microcontroller clock output
       bit_offset: 24
       bit_size: 3
       enum: MCO
+    - name: SDPRE
+      description: SDADC prescaler
+      bit_offset: 27
+      bit_size: 5
+      enum: SDPRE
     - name: MCOPRE
       description: Microcontroller Clock Output Prescaler
       bit_offset: 28
@@ -409,11 +662,21 @@ fieldset/CFGR2:
       bit_offset: 0
       bit_size: 4
       enum: PREDIV
+    - name: ADC1PRES
+      description: ADC1 prescaler
+      bit_offset: 4
+      bit_size: 5
+      enum: ADCPRES
     - name: ADC12PRES
       description: ADC1 and ADC2 prescaler
       bit_offset: 4
       bit_size: 5
       enum: ADCPRES
+    - name: ADC34PRES
+      description: ADC3 and ADC4 prescaler
+      bit_offset: 9
+      bit_size: 5
+      enum: ADCPRES
 fieldset/CFGR3:
   description: Clock configuration register 3
   fields:
@@ -427,11 +690,81 @@ fieldset/CFGR3:
       bit_offset: 4
       bit_size: 1
       enum: ICSW
+    - name: I2C2SW
+      description: I2C2 clock source selection
+      bit_offset: 5
+      bit_size: 1
+      enum: ICSW
+    - name: I2C3SW
+      description: I2C3 clock source selection
+      bit_offset: 6
+      bit_size: 1
+      enum: ICSW
+    - name: CECSW
+      description: HDMI CEC clock source selection
+      bit_offset: 6
+      bit_size: 1
+      enum: CECSW
     - name: TIM1SW
       description: Timer1 clock source selection
       bit_offset: 8
       bit_size: 1
       enum: TIMSW
+    - name: TIM8SW
+      description: Timer8 clock source selection
+      bit_offset: 9
+      bit_size: 1
+      enum: TIMSW
+    - name: TIM15SW
+      description: Timer15 clock source selection
+      bit_offset: 10
+      bit_size: 1
+      enum: TIMSW
+    - name: TIM16SW
+      description: Timer16 clock source selection
+      bit_offset: 11
+      bit_size: 1
+      enum: TIMSW
+    - name: TIM17SW
+      description: Timer17 clock source selection
+      bit_offset: 13
+      bit_size: 1
+      enum: TIMSW
+    - name: TIM20SW
+      description: Timer20 clock source selection
+      bit_offset: 15
+      bit_size: 1
+      enum: TIMSW
+    - name: USART2SW
+      description: USART2 clock source selection
+      bit_offset: 16
+      bit_size: 2
+      enum: USARTSW
+    - name: USART3SW
+      description: USART3 clock source selection
+      bit_offset: 18
+      bit_size: 2
+      enum: USARTSW
+    - name: UART4SW
+      description: UART4 clock source selection
+      bit_offset: 20
+      bit_size: 2
+      enum: USARTSW
+    - name: UART5SW
+      description: UART5 clock source selection
+      bit_offset: 22
+      bit_size: 2
+      enum: USARTSW
+    - name: TIM2SW
+      description: Timer2 clock source selection
+      bit_offset: 24
+      bit_size: 1
+      enum: TIMSW
+    - name: TIM34SW
+      description: Timer34 clock source selection
+      bit_offset: 25
+      bit_size: 1
+      enum: TIMSW
 fieldset/CIR:
   description: Clock interrupt register (RCC_CIR)
   fields:
@@ -583,7 +916,6 @@ fieldset/CSR:
       description: Reset flag of the 1.8 V domain
       bit_offset: 23
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: RMVF
       description: Remove reset flag
       bit_offset: 24
@@ -593,37 +925,45 @@ fieldset/CSR:
       description: Option byte loader reset flag
       bit_offset: 25
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: PINRSTF
       description: PIN reset flag
       bit_offset: 26
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: PORRSTF
       description: POR/PDR reset flag
       bit_offset: 27
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: SFTRSTF
       description: Software reset flag
       bit_offset: 28
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: IWDGRSTF
       description: Independent watchdog reset flag
       bit_offset: 29
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: WWDGRSTF
       description: Window watchdog reset flag
       bit_offset: 30
       bit_size: 1
-      enum_read: OBLRSTFR
     - name: LPWRRSTF
       description: Low-power reset flag
       bit_offset: 31
       bit_size: 1
-      enum_read: OBLRSTFR
+enum/ADCPRE:
+  bit_size: 2
+  variants:
+    - name: Div2
+      description: PCLK divided by 2
+      value: 0
+    - name: Div4
+      description: PCLK divided by 4
+      value: 1
+    - name: Div6
+      description: PCLK divided by 6
+      value: 2
+    - name: Div8
+      description: PCLK divided by 8
+      value: 3
 enum/ADCPRES:
   bit_size: 5
   variants:
@@ -666,6 +1006,15 @@ enum/ADCPRES:
     - name: Div256
       description: PLL clock divided by 256
       value: 27
+enum/CECSW:
+  bit_size: 1
+  variants:
+    - name: HSI_Div244
+      description: HSI clock divided by 244 selected as CEC clock source
+      value: 0
+    - name: LSE
+      description: LSE clock selected as CEC clock source
+      value: 1
 enum/CSSCW:
   bit_size: 1
   variants:
@@ -738,6 +1087,15 @@ enum/ICSW:
     - name: SYSCLK
       description: SYSCLK clock selected as I2C clock source
       value: 1
+enum/ISSRC:
+  bit_size: 1
+  variants:
+    - name: SYSCLK
+      description: System clock used as I2S clock source
+      value: 0
+    - name: CKIN
+      description: External clock mapped on the I2S_CKIN pin used as I2S clock source
+      value: 1
 enum/LSEBYP:
   bit_size: 1
   variants:
@@ -855,15 +1213,6 @@ enum/MCOPRE:
     - name: Div128
       description: MCO is divided by 128
       value: 7
-enum/OBLRSTFR:
-  bit_size: 1
-  variants:
-    - name: NoReset
-      description: No reset has occured
-      value: 0
-    - name: Reset
-      description: A reset has occured
-      value: 1
 enum/PLLMUL:
   bit_size: 4
   variants:
@@ -1032,6 +1381,57 @@ enum/RTCSEL:
     - name: HSE
       description: HSE oscillator clock divided by a prescaler used as RTC clock
       value: 3
+enum/SDPRE:
+  bit_size: 5
+  variants:
+    - name: Div2
+      description: SYSCLK divided by 2
+      value: 0
+    - name: Div4
+      description: SYSCLK divided by 4
+      value: 17
+    - name: Div6
+      description: SYSCLK divided by 6
+      value: 18
+    - name: Div8
+      description: SYSCLK divided by 8
+      value: 19
+    - name: Div10
+      description: SYSCLK divided by 10
+      value: 20
+    - name: Div12
+      description: SYSCLK divided by 12
+      value: 21
+    - name: Div14
+      description: SYSCLK divided by 14
+      value: 22
+    - name: Div16
+      description: SYSCLK divided by 16
+      value: 23
+    - name: Div20
+      description: SYSCLK divided by 20
+      value: 24
+    - name: Div24
+      description: SYSCLK divided by 24
+      value: 25
+    - name: Div28
+      description: SYSCLK divided by 28
+      value: 26
+    - name: Div32
+      description: SYSCLK divided by 32
+      value: 27
+    - name: Div36
+      description: SYSCLK divided by 36
+      value: 28
+    - name: Div40
+      description: SYSCLK divided by 40
+      value: 29
+    - name: Div44
+      description: SYSCLK divided by 44
+      value: 30
+    - name: Div48
+      description: SYSCLK divided by 48
+      value: 31
 enum/SW:
   bit_size: 2
   variants:
@@ -1080,3 +1480,12 @@ enum/USARTSW:
     - name: HSI
       description: HSI selected as USART clock source
       value: 3
+enum/USBPRE:
+  bit_size: 1
+  variants:
+    - name: DIV1_5
+      description: PLL clock is divided by 1.5
+      value: 0
+    - name: DIV1
+      description: PLL clock is not divided
+      value: 1