diff --git a/data/registers/pwr_h50.yaml b/data/registers/pwr_h50.yaml
index 1b8e961..932e941 100644
--- a/data/registers/pwr_h50.yaml
+++ b/data/registers/pwr_h50.yaml
@@ -408,16 +408,16 @@ enum/VBRS:
 enum/VOS:
   bit_size: 2
   variants:
-    - name: B_0x0
+    - name: Scale3
       description: scale 3 (default)
       value: 0
-    - name: B_0x1
+    - name: Scale2
       description: scale 2
       value: 1
-    - name: B_0x2
+    - name: Scale1
       description: scale 1
       value: 2
-    - name: B_0x3
+    - name: Scale0
       description: scale 0
       value: 3
 enum/WUPP:
diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml
index b4d23bd..8fac1eb 100644
--- a/data/registers/rcc_h5.yaml
+++ b/data/registers/rcc_h5.yaml
@@ -84,7 +84,7 @@ block/RCC:
       byte_offset: 124
       fieldset: APB2RSTR
     - name: APB3RSTR
-      description: RCC APB4 peripheral reset register
+      description: RCC APB3 peripheral reset register
       byte_offset: 128
       fieldset: APB3RSTR
     - name: AHB1ENR
@@ -112,7 +112,7 @@ block/RCC:
       byte_offset: 164
       fieldset: APB2ENR
     - name: APB3ENR
-      description: RCC APB4 peripheral clock register
+      description: RCC APB3 peripheral clock register
       byte_offset: 168
       fieldset: APB3ENR
     - name: AHB1LPENR
@@ -140,7 +140,7 @@ block/RCC:
       byte_offset: 204
       fieldset: APB2LPENR
     - name: APB3LPENR
-      description: RCC APB4 sleep clock register
+      description: RCC APB3 sleep clock register
       byte_offset: 208
       fieldset: APB3LPENR
     - name: CCIPR1
@@ -1186,7 +1186,7 @@ fieldset/APB2RSTR:
       bit_offset: 24
       bit_size: 1
 fieldset/APB3ENR:
-  description: RCC APB4 peripheral clock register
+  description: RCC APB3 peripheral clock register
   fields:
     - name: SBSEN
       description: "SBS clock enable\r Set and reset by software."
diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml
index c0bf504..9fb305f 100644
--- a/data/registers/rcc_h50.yaml
+++ b/data/registers/rcc_h50.yaml
@@ -614,8 +614,8 @@ fieldset/APB2ENR:
       description: "USART1 clock enable\r Set and reset by software."
       bit_offset: 14
       bit_size: 1
-    - name: USBFSEN
-      description: "USBFS clock enable\r Set and reset by software."
+    - name: USBEN
+      description: "USB clock enable\r Set and reset by software."
       bit_offset: 24
       bit_size: 1
 fieldset/APB2LPENR:
@@ -633,8 +633,8 @@ fieldset/APB2LPENR:
       description: "USART1 clock enable during sleep mode\r Set and reset by software."
       bit_offset: 14
       bit_size: 1
-    - name: USBFSLPEN
-      description: "USBFS clock enable during sleep mode\r Set and reset by software."
+    - name: USBLPEN
+      description: "USB clock enable during sleep mode\r Set and reset by software."
       bit_offset: 24
       bit_size: 1
 fieldset/APB2RSTR:
@@ -652,8 +652,8 @@ fieldset/APB2RSTR:
       description: "USART1 block reset\r Set and reset by software."
       bit_offset: 14
       bit_size: 1
-    - name: USBFSRST
-      description: "USBFS block reset\r Set and reset by software."
+    - name: USBRST
+      description: "USB block reset\r Set and reset by software."
       bit_offset: 24
       bit_size: 1
 fieldset/APB3ENR:
@@ -863,11 +863,11 @@ fieldset/CCIPR4:
       bit_offset: 2
       bit_size: 2
       enum: SYSTICKSEL
-    - name: USBFSSEL
-      description: USBFS kernel clock source selection
+    - name: USBSEL
+      description: USB kernel clock source selection
       bit_offset: 4
       bit_size: 2
-      enum: USBFSSEL
+      enum: USBSEL
     - name: I2C1SEL
       description: I2C1 kernel clock source selection
       bit_offset: 16
@@ -1599,6 +1599,9 @@ enum/PLLVCOSEL:
 enum/PPRE:
   bit_size: 3
   variants:
+    - name: Div1
+      description: rcc_pclk3 = rcc_hclk1 / 1
+      value: 0
     - name: Div2
       description: rcc_pclk3 = rcc_hclk1 / 2
       value: 4
@@ -1710,10 +1713,10 @@ enum/TIMICSEL:
 enum/TIMPRE:
   bit_size: 1
   variants:
-    - name: Mul1
+    - name: DefaultX2
       description: "The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)"
       value: 0
-    - name: Mul2
+    - name: DefaultX4
       description: "The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2"
       value: 1
 enum/USARTSEL:
@@ -1734,7 +1737,7 @@ enum/USARTSEL:
     - name: LSE
       description: LSE selected as peripheral clock
       value: 5
-enum/USBFSSEL:
+enum/USBSEL:
   bit_size: 2
   variants:
     - name: DISABLE