apply transform

data/registers/comp_h5.yaml

@@ -1,23 +1,23 @@
 block/COMP:
   description: Comparator.
   items:
-  - name: COMP_SR
+  - name: SR
     description: Comparator status register.
     byte_offset: 0
-    fieldset: COMP_SR
-  - name: COMP_ICFR
+    fieldset: SR
+  - name: ICFR
     description: Comparator interrupt clear flag register.
     byte_offset: 4
-    fieldset: COMP_ICFR
-  - name: COMP_CFGR1
+    fieldset: ICFR
+  - name: CFGR1
     description: Comparator configuration register 1.
     byte_offset: 12
-    fieldset: COMP_CFGR1
-  - name: COMP_CFGR2
+    fieldset: CFGR1
+  - name: CFGR2
     description: Comparator configuration register 2.
     byte_offset: 16
-    fieldset: COMP_CFGR2
-fieldset/COMP_CFGR1:
+    fieldset: CFGR2
+fieldset/CFGR1:
   description: Comparator configuration register 1.
   fields:
   - name: EN
@@ -68,7 +68,7 @@ fieldset/COMP_CFGR1:
     description: Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0].
     bit_offset: 31
     bit_size: 1
-fieldset/COMP_CFGR2:
+fieldset/CFGR2:
   description: Comparator configuration register 2.
   fields:
   - name: INPSEL0
@@ -79,21 +79,30 @@ fieldset/COMP_CFGR2:
     description: Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0].
     bit_offset: 31
     bit_size: 1
-fieldset/COMP_ICFR:
+fieldset/ICFR:
   description: Comparator interrupt clear flag register.
   fields:
-  - name: CC1IF
+  - name: CCIF
     description: Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register.
     bit_offset: 16
     bit_size: 1
-fieldset/COMP_SR:
+    array:
+      len: 1
+      stride: 0
+fieldset/SR:
   description: Comparator status register.
   fields:
-  - name: C1VAL
-    description: COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
-    bit_offset: 0
-    bit_size: 1
-  - name: C1IF
+  - name: CIF
     description: COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.
     bit_offset: 16
     bit_size: 1
+    array:
+      len: 1
+      stride: 0
+  - name: CVAL
+    description: COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 1
+      stride: 0

transforms/COMP_h.yaml

@@ -4,6 +4,15 @@ transforms:
     from: ^(COMP)\d$
     to: $1
 
+  - !RenameRegisters
+    block: COMP
+    from: ^COMP_(.+)$
+    to: $1
+
+  - !Rename
+    from: ^COMP_(.+)$
+    to: $1
+
   - !MakeFieldArray
     fieldsets: ^(SR|ICFR)$
     from: (C?C)\d(IF|VAL)