diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml
index 6549042..3551c30 100644
--- a/data/registers/rcc_f1.yaml
+++ b/data/registers/rcc_f1.yaml
@@ -64,64 +64,6 @@ enum/ADCPRE:
   - description: PCLK2 divided by 16
     name: Div8
     value: 3
-enum/AFIOEN:
-  bit_size: 1
-  variants:
-  - description: The selected clock is disabled
-    name: Disabled
-    value: 0
-  - description: The selected clock is enabled
-    name: Enabled
-    value: 1
-enum/AFIORST:
-  bit_size: 1
-  variants:
-  - description: Reset the selected module
-    name: Reset
-    value: 1
-enum/BDRST:
-  bit_size: 1
-  variants:
-  - description: Reset not activated
-    name: Disabled
-    value: 0
-  - description: Reset the entire RTC domain
-    name: Enabled
-    value: 1
-enum/CSSCW:
-  bit_size: 1
-  variants:
-  - description: Clear CSSF flag
-    name: Clear
-    value: 1
-enum/CSSFR:
-  bit_size: 1
-  variants:
-  - description: No clock security interrupt caused by HSE clock failure
-    name: NotInterrupted
-    value: 0
-  - description: Clock security interrupt caused by HSE clock failure
-    name: Interrupted
-    value: 1
-enum/CSSON:
-  bit_size: 1
-  variants:
-  - description: Clock security system disabled (clock detector OFF)
-    name: 'Off'
-    value: 0
-  - description: Clock security system enable (clock detector ON if the HSE is ready,
-      OFF if not)
-    name: 'On'
-    value: 1
-enum/DMA1EN:
-  bit_size: 1
-  variants:
-  - description: The selected clock is disabled
-    name: Disabled
-    value: 0
-  - description: The selected clock is enabled
-    name: Enabled
-    value: 1
 enum/HPRE:
   bit_size: 4
   variants:
@@ -152,33 +94,6 @@ enum/HPRE:
   - description: SYSCLK divided by 512
     name: Div512
     value: 15
-enum/HSEBYP:
-  bit_size: 1
-  variants:
-  - description: HSE crystal oscillator not bypassed
-    name: NotBypassed
-    value: 0
-  - description: HSE crystal oscillator bypassed with external clock
-    name: Bypassed
-    value: 1
-enum/HSION:
-  bit_size: 1
-  variants:
-  - description: Clock Off
-    name: 'Off'
-    value: 0
-  - description: Clock On
-    name: 'On'
-    value: 1
-enum/HSIRDYR:
-  bit_size: 1
-  variants:
-  - description: Clock not ready
-    name: NotReady
-    value: 0
-  - description: Clock ready
-    name: Ready
-    value: 1
 enum/I2S2SRC:
   bit_size: 1
   variants:
@@ -188,75 +103,6 @@ enum/I2S2SRC:
   - description: PLL3 VCO clock selected as I2S clock entry
     name: PLL3
     value: 1
-enum/LSEBYP:
-  bit_size: 1
-  variants:
-  - description: LSE crystal oscillator not bypassed
-    name: NotBypassed
-    value: 0
-  - description: LSE crystal oscillator bypassed with external clock
-    name: Bypassed
-    value: 1
-enum/LSEON:
-  bit_size: 1
-  variants:
-  - description: LSE oscillator Off
-    name: 'Off'
-    value: 0
-  - description: LSE oscillator On
-    name: 'On'
-    value: 1
-enum/LSERDYR:
-  bit_size: 1
-  variants:
-  - description: LSE oscillator not ready
-    name: NotReady
-    value: 0
-  - description: LSE oscillator ready
-    name: Ready
-    value: 1
-enum/LSION:
-  bit_size: 1
-  variants:
-  - description: LSI oscillator Off
-    name: 'Off'
-    value: 0
-  - description: LSI oscillator On
-    name: 'On'
-    value: 1
-enum/LSIRDYCW:
-  bit_size: 1
-  variants:
-  - description: Clear interrupt flag
-    name: Clear
-    value: 1
-enum/LSIRDYFR:
-  bit_size: 1
-  variants:
-  - description: No clock ready interrupt
-    name: NotInterrupted
-    value: 0
-  - description: Clock ready interrupt
-    name: Interrupted
-    value: 1
-enum/LSIRDYIE:
-  bit_size: 1
-  variants:
-  - description: Interrupt disabled
-    name: Disabled
-    value: 0
-  - description: Interrupt enabled
-    name: Enabled
-    value: 1
-enum/LSIRDYR:
-  bit_size: 1
-  variants:
-  - description: LSI oscillator not ready
-    name: NotReady
-    value: 0
-  - description: LSI oscillator ready
-    name: Ready
-    value: 1
 enum/MCO:
   bit_size: 4
   variants:
@@ -284,21 +130,6 @@ enum/OTGFSPRE:
   - description: PLL clock is not divided
     name: DIV1
     value: 1
-enum/OTGFSRST:
-  bit_size: 1
-  variants:
-  - description: Reset the selected module
-    name: Reset
-    value: 1
-enum/PINRSTFR:
-  bit_size: 1
-  variants:
-  - description: No reset has occured
-    name: NoReset
-    value: 0
-  - description: A reset has occured
-    name: Reset
-    value: 1
 enum/PLL2MUL:
   bit_size: 4
   variants:
@@ -476,21 +307,6 @@ enum/PREDIV1SRC:
   - description: PLL2 selected as PREDIV1 clock entry
     name: PLL2
     value: 1
-enum/RMVFW:
-  bit_size: 1
-  variants:
-  - description: Clears the reset flag
-    name: Clear
-    value: 1
-enum/RTCEN:
-  bit_size: 1
-  variants:
-  - description: RTC clock disabled
-    name: Disabled
-    value: 0
-  - description: RTC clock enabled
-    name: Enabled
-    value: 1
 enum/RTCSEL:
   bit_size: 2
   variants:
@@ -530,21 +346,6 @@ enum/SWSR:
   - description: PLL used as system clock
     name: PLL
     value: 2
-enum/TIM2EN:
-  bit_size: 1
-  variants:
-  - description: The selected clock is disabled
-    name: Disabled
-    value: 0
-  - description: The selected clock is enabled
-    name: Enabled
-    value: 1
-enum/TIM2RST:
-  bit_size: 1
-  variants:
-  - description: Reset the selected module
-    name: Reset
-    value: 1
 enum/USBPRE:
   bit_size: 1
   variants:
@@ -560,57 +361,46 @@ fieldset/AHBENR:
   - bit_offset: 0
     bit_size: 1
     description: DMA1 clock enable
-    enum: DMA1EN
     name: DMA1EN
   - bit_offset: 1
     bit_size: 1
     description: DMA2 clock enable
-    enum: DMA1EN
     name: DMA2EN
   - bit_offset: 2
     bit_size: 1
     description: SRAM interface clock enable
-    enum: DMA1EN
     name: SRAMEN
   - bit_offset: 4
     bit_size: 1
     description: FLITF clock enable
-    enum: DMA1EN
     name: FLITFEN
   - bit_offset: 6
     bit_size: 1
     description: CRC clock enable
-    enum: DMA1EN
     name: CRCEN
   - bit_offset: 8
     bit_size: 1
     description: FSMC clock enable
-    enum: DMA1EN
     name: FSMCEN
   - bit_offset: 10
     bit_size: 1
     description: SDIO clock enable
-    enum: DMA1EN
     name: SDIOEN
   - bit_offset: 12
     bit_size: 1
     description: USB OTG FS clock enable
-    enum: DMA1EN
     name: OTGFSEN
   - bit_offset: 14
     bit_size: 1
     description: Ethernet MAC clock enable
-    enum: DMA1EN
     name: ETHMACEN
   - bit_offset: 15
     bit_size: 1
     description: Ethernet MAC TX clock enable
-    enum: DMA1EN
     name: ETHMACTXEN
   - bit_offset: 16
     bit_size: 1
     description: Ethernet MAC RX clock enable
-    enum: DMA1EN
     name: ETHMACRXEN
 fieldset/AHBRSTR:
   description: AHB peripheral clock reset register (RCC_AHBRSTR)
@@ -618,12 +408,10 @@ fieldset/AHBRSTR:
   - bit_offset: 12
     bit_size: 1
     description: USB OTG FS reset
-    enum: OTGFSRST
     name: OTGFSRST
   - bit_offset: 14
     bit_size: 1
     description: Ethernet MAC reset
-    enum: OTGFSRST
     name: ETHMACRST
 fieldset/APB1ENR:
   description: APB1 peripheral clock enable register (RCC_APB1ENR)
@@ -631,132 +419,106 @@ fieldset/APB1ENR:
   - bit_offset: 0
     bit_size: 1
     description: Timer 2 clock enable
-    enum: TIM2EN
     name: TIM2EN
   - bit_offset: 1
     bit_size: 1
     description: Timer 3 clock enable
-    enum: TIM2EN
     name: TIM3EN
   - bit_offset: 2
     bit_size: 1
     description: Timer 4 clock enable
-    enum: TIM2EN
     name: TIM4EN
   - bit_offset: 3
     bit_size: 1
     description: Timer 5 clock enable
-    enum: TIM2EN
     name: TIM5EN
   - bit_offset: 4
     bit_size: 1
     description: Timer 6 clock enable
-    enum: TIM2EN
     name: TIM6EN
   - bit_offset: 5
     bit_size: 1
     description: Timer 7 clock enable
-    enum: TIM2EN
     name: TIM7EN
   - bit_offset: 6
     bit_size: 1
     description: Timer 12 clock enable
-    enum: TIM2EN
     name: TIM12EN
   - bit_offset: 7
     bit_size: 1
     description: Timer 13 clock enable
-    enum: TIM2EN
     name: TIM13EN
   - bit_offset: 8
     bit_size: 1
     description: Timer 14 clock enable
-    enum: TIM2EN
     name: TIM14EN
   - bit_offset: 11
     bit_size: 1
     description: Window watchdog clock enable
-    enum: TIM2EN
     name: WWDGEN
   - bit_offset: 14
     bit_size: 1
     description: SPI 2 clock enable
-    enum: TIM2EN
     name: SPI2EN
   - bit_offset: 15
     bit_size: 1
     description: SPI 3 clock enable
-    enum: TIM2EN
     name: SPI3EN
   - bit_offset: 17
     bit_size: 1
     description: USART 2 clock enable
-    enum: TIM2EN
     name: USART2EN
   - bit_offset: 18
     bit_size: 1
     description: USART 3 clock enable
-    enum: TIM2EN
     name: USART3EN
   - bit_offset: 19
     bit_size: 1
     description: UART 4 clock enable
-    enum: TIM2EN
     name: UART4EN
   - bit_offset: 20
     bit_size: 1
     description: UART 5 clock enable
-    enum: TIM2EN
     name: UART5EN
   - bit_offset: 21
     bit_size: 1
     description: I2C 1 clock enable
-    enum: TIM2EN
     name: I2C1EN
   - bit_offset: 22
     bit_size: 1
     description: I2C 2 clock enable
-    enum: TIM2EN
     name: I2C2EN
   - bit_offset: 23
     bit_size: 1
     description: USB clock enable
-    enum: TIM2EN
     name: USBEN
   - bit_offset: 25
     bit_size: 1
     description: CAN clock enable
-    enum: TIM2EN
     name: CANEN
   - bit_offset: 25
     bit_size: 1
     description: CAN1 clock enable
-    enum: TIM2EN
     name: CAN1EN
   - bit_offset: 26
     bit_size: 1
     description: CAN2 clock enable
-    enum: TIM2EN
     name: CAN2EN
   - bit_offset: 27
     bit_size: 1
     description: Backup interface clock enable
-    enum: TIM2EN
     name: BKPEN
   - bit_offset: 28
     bit_size: 1
     description: Power interface clock enable
-    enum: TIM2EN
     name: PWREN
   - bit_offset: 29
     bit_size: 1
     description: DAC interface clock enable
-    enum: TIM2EN
     name: DACEN
   - bit_offset: 30
     bit_size: 1
     description: CEC clock enable
-    enum: TIM2EN
     name: CECEN
 fieldset/APB1RSTR:
   description: APB1 peripheral reset register (RCC_APB1RSTR)
@@ -764,132 +526,106 @@ fieldset/APB1RSTR:
   - bit_offset: 0
     bit_size: 1
     description: Timer 2 reset
-    enum: TIM2RST
     name: TIM2RST
   - bit_offset: 1
     bit_size: 1
     description: Timer 3 reset
-    enum: TIM2RST
     name: TIM3RST
   - bit_offset: 2
     bit_size: 1
     description: Timer 4 reset
-    enum: TIM2RST
     name: TIM4RST
   - bit_offset: 3
     bit_size: 1
     description: Timer 5 reset
-    enum: TIM2RST
     name: TIM5RST
   - bit_offset: 4
     bit_size: 1
     description: Timer 6 reset
-    enum: TIM2RST
     name: TIM6RST
   - bit_offset: 5
     bit_size: 1
     description: Timer 7 reset
-    enum: TIM2RST
     name: TIM7RST
   - bit_offset: 6
     bit_size: 1
     description: Timer 12 reset
-    enum: TIM2RST
     name: TIM12RST
   - bit_offset: 7
     bit_size: 1
     description: Timer 13 reset
-    enum: TIM2RST
     name: TIM13RST
   - bit_offset: 8
     bit_size: 1
     description: Timer 14 reset
-    enum: TIM2RST
     name: TIM14RST
   - bit_offset: 11
     bit_size: 1
     description: Window watchdog reset
-    enum: TIM2RST
     name: WWDGRST
   - bit_offset: 14
     bit_size: 1
     description: SPI2 reset
-    enum: TIM2RST
     name: SPI2RST
   - bit_offset: 15
     bit_size: 1
     description: SPI3 reset
-    enum: TIM2RST
     name: SPI3RST
   - bit_offset: 17
     bit_size: 1
     description: USART 2 reset
-    enum: TIM2RST
     name: USART2RST
   - bit_offset: 18
     bit_size: 1
     description: USART 3 reset
-    enum: TIM2RST
     name: USART3RST
   - bit_offset: 19
     bit_size: 1
     description: USART 4 reset
-    enum: TIM2RST
     name: UART4RST
   - bit_offset: 20
     bit_size: 1
     description: USART 5 reset
-    enum: TIM2RST
     name: UART5RST
   - bit_offset: 21
     bit_size: 1
     description: I2C1 reset
-    enum: TIM2RST
     name: I2C1RST
   - bit_offset: 22
     bit_size: 1
     description: I2C2 reset
-    enum: TIM2RST
     name: I2C2RST
   - bit_offset: 23
     bit_size: 1
     description: USB reset
-    enum: TIM2RST
     name: USBRST
   - bit_offset: 25
     bit_size: 1
     description: CAN reset
-    enum: TIM2RST
     name: CANRST
   - bit_offset: 25
     bit_size: 1
     description: CAN1 reset
-    enum: TIM2RST
     name: CAN1RST
   - bit_offset: 26
     bit_size: 1
     description: CAN2 reset
-    enum: TIM2RST
     name: CAN2RST
   - bit_offset: 27
     bit_size: 1
     description: Backup interface reset
-    enum: TIM2RST
     name: BKPRST
   - bit_offset: 28
     bit_size: 1
     description: Power interface reset
-    enum: TIM2RST
     name: PWRRST
   - bit_offset: 29
     bit_size: 1
     description: DAC interface reset
-    enum: TIM2RST
     name: DACRST
   - bit_offset: 30
     bit_size: 1
     description: CEC reset
-    enum: TIM2RST
     name: CECRST
 fieldset/APB2ENR:
   description: APB2 peripheral clock enable register (RCC_APB2ENR)
@@ -897,107 +633,86 @@ fieldset/APB2ENR:
   - bit_offset: 0
     bit_size: 1
     description: Alternate function I/O clock enable
-    enum: AFIOEN
     name: AFIOEN
   - bit_offset: 2
     bit_size: 1
     description: I/O port A clock enable
-    enum: AFIOEN
     name: IOPAEN
   - bit_offset: 3
     bit_size: 1
     description: I/O port B clock enable
-    enum: AFIOEN
     name: IOPBEN
   - bit_offset: 4
     bit_size: 1
     description: I/O port C clock enable
-    enum: AFIOEN
     name: IOPCEN
   - bit_offset: 5
     bit_size: 1
     description: I/O port D clock enable
-    enum: AFIOEN
     name: IOPDEN
   - bit_offset: 6
     bit_size: 1
     description: I/O port E clock enable
-    enum: AFIOEN
     name: IOPEEN
   - bit_offset: 7
     bit_size: 1
     description: I/O port F clock enable
-    enum: AFIOEN
     name: IOPFEN
   - bit_offset: 8
     bit_size: 1
     description: I/O port G clock enable
-    enum: AFIOEN
     name: IOPGEN
   - bit_offset: 9
     bit_size: 1
     description: ADC 1 interface clock enable
-    enum: AFIOEN
     name: ADC1EN
   - bit_offset: 10
     bit_size: 1
     description: ADC 2 interface clock enable
-    enum: AFIOEN
     name: ADC2EN
   - bit_offset: 11
     bit_size: 1
     description: TIM1 Timer clock enable
-    enum: AFIOEN
     name: TIM1EN
   - bit_offset: 12
     bit_size: 1
     description: SPI 1 clock enable
-    enum: AFIOEN
     name: SPI1EN
   - bit_offset: 13
     bit_size: 1
     description: TIM8 Timer clock enable
-    enum: AFIOEN
     name: TIM8EN
   - bit_offset: 14
     bit_size: 1
     description: USART1 clock enable
-    enum: AFIOEN
     name: USART1EN
   - bit_offset: 15
     bit_size: 1
     description: ADC3 interface clock enable
-    enum: AFIOEN
     name: ADC3EN
   - bit_offset: 16
     bit_size: 1
     description: TIM15 Timer clock enable
-    enum: AFIOEN
     name: TIM15EN
   - bit_offset: 17
     bit_size: 1
     description: TIM16 Timer clock enable
-    enum: AFIOEN
     name: TIM16EN
   - bit_offset: 18
     bit_size: 1
     description: TIM17 Timer clock enable
-    enum: AFIOEN
     name: TIM17EN
   - bit_offset: 19
     bit_size: 1
     description: TIM9 Timer clock enable
-    enum: AFIOEN
     name: TIM9EN
   - bit_offset: 20
     bit_size: 1
     description: TIM10 Timer clock enable
-    enum: AFIOEN
     name: TIM10EN
   - bit_offset: 21
     bit_size: 1
     description: TIM11 Timer clock enable
-    enum: AFIOEN
     name: TIM11EN
 fieldset/APB2RSTR:
   description: APB2 peripheral reset register (RCC_APB2RSTR)
@@ -1005,107 +720,86 @@ fieldset/APB2RSTR:
   - bit_offset: 0
     bit_size: 1
     description: Alternate function I/O reset
-    enum: AFIORST
     name: AFIORST
   - bit_offset: 2
     bit_size: 1
     description: IO port A reset
-    enum: AFIORST
     name: IOPARST
   - bit_offset: 3
     bit_size: 1
     description: IO port B reset
-    enum: AFIORST
     name: IOPBRST
   - bit_offset: 4
     bit_size: 1
     description: IO port C reset
-    enum: AFIORST
     name: IOPCRST
   - bit_offset: 5
     bit_size: 1
     description: IO port D reset
-    enum: AFIORST
     name: IOPDRST
   - bit_offset: 6
     bit_size: 1
     description: IO port E reset
-    enum: AFIORST
     name: IOPERST
   - bit_offset: 7
     bit_size: 1
     description: IO port F reset
-    enum: AFIORST
     name: IOPFRST
   - bit_offset: 8
     bit_size: 1
     description: IO port G reset
-    enum: AFIORST
     name: IOPGRST
   - bit_offset: 9
     bit_size: 1
     description: ADC 1 interface reset
-    enum: AFIORST
     name: ADC1RST
   - bit_offset: 10
     bit_size: 1
     description: ADC 2 interface reset
-    enum: AFIORST
     name: ADC2RST
   - bit_offset: 11
     bit_size: 1
     description: TIM1 timer reset
-    enum: AFIORST
     name: TIM1RST
   - bit_offset: 12
     bit_size: 1
     description: SPI 1 reset
-    enum: AFIORST
     name: SPI1RST
   - bit_offset: 13
     bit_size: 1
     description: TIM8 timer reset
-    enum: AFIORST
     name: TIM8RST
   - bit_offset: 14
     bit_size: 1
     description: USART1 reset
-    enum: AFIORST
     name: USART1RST
   - bit_offset: 15
     bit_size: 1
     description: ADC 3 interface reset
-    enum: AFIORST
     name: ADC3RST
   - bit_offset: 16
     bit_size: 1
     description: TIM15 timer reset
-    enum: AFIORST
     name: TIM15RST
   - bit_offset: 17
     bit_size: 1
     description: TIM16 timer reset
-    enum: AFIORST
     name: TIM16RST
   - bit_offset: 18
     bit_size: 1
     description: TIM17 timer reset
-    enum: AFIORST
     name: TIM17RST
   - bit_offset: 19
     bit_size: 1
     description: TIM9 timer reset
-    enum: AFIORST
     name: TIM9RST
   - bit_offset: 20
     bit_size: 1
     description: TIM10 timer reset
-    enum: AFIORST
     name: TIM10RST
   - bit_offset: 21
     bit_size: 1
     description: TIM11 timer reset
-    enum: AFIORST
     name: TIM11RST
 fieldset/BDCR:
   description: Backup domain control register (RCC_BDCR)
@@ -1113,17 +807,14 @@ fieldset/BDCR:
   - bit_offset: 0
     bit_size: 1
     description: External Low Speed oscillator enable
-    enum: LSEON
     name: LSEON
   - bit_offset: 1
     bit_size: 1
     description: External Low Speed oscillator ready
-    enum_read: LSERDYR
     name: LSERDY
   - bit_offset: 2
     bit_size: 1
     description: External Low Speed oscillator bypass
-    enum: LSEBYP
     name: LSEBYP
   - bit_offset: 8
     bit_size: 2
@@ -1133,12 +824,10 @@ fieldset/BDCR:
   - bit_offset: 15
     bit_size: 1
     description: RTC clock enable
-    enum: RTCEN
     name: RTCEN
   - bit_offset: 16
     bit_size: 1
     description: Backup domain software reset
-    enum: BDRST
     name: BDRST
 fieldset/CFGR:
   description: Clock configuration register (RCC_CFGR)
@@ -1247,117 +936,94 @@ fieldset/CIR:
   - bit_offset: 0
     bit_size: 1
     description: LSI Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: LSIRDYF
   - bit_offset: 1
     bit_size: 1
     description: LSE Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: LSERDYF
   - bit_offset: 2
     bit_size: 1
     description: HSI Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: HSIRDYF
   - bit_offset: 3
     bit_size: 1
     description: HSE Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: HSERDYF
   - bit_offset: 4
     bit_size: 1
     description: PLL Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: PLLRDYF
   - bit_offset: 5
     bit_size: 1
     description: PLL2 Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: PLL2RDYF
   - bit_offset: 6
     bit_size: 1
     description: PLL3 Ready Interrupt flag
-    enum_read: LSIRDYFR
     name: PLL3RDYF
   - bit_offset: 7
     bit_size: 1
     description: Clock Security System Interrupt flag
-    enum_read: CSSFR
     name: CSSF
   - bit_offset: 8
     bit_size: 1
     description: LSI Ready Interrupt Enable
-    enum: LSIRDYIE
     name: LSIRDYIE
   - bit_offset: 9
     bit_size: 1
     description: LSE Ready Interrupt Enable
-    enum: LSIRDYIE
     name: LSERDYIE
   - bit_offset: 10
     bit_size: 1
     description: HSI Ready Interrupt Enable
-    enum: LSIRDYIE
     name: HSIRDYIE
   - bit_offset: 11
     bit_size: 1
     description: HSE Ready Interrupt Enable
-    enum: LSIRDYIE
     name: HSERDYIE
   - bit_offset: 12
     bit_size: 1
     description: PLL Ready Interrupt Enable
-    enum: LSIRDYIE
     name: PLLRDYIE
   - bit_offset: 13
     bit_size: 1
     description: PLL2 Ready Interrupt Enable
-    enum: LSIRDYIE
     name: PLL2RDYIE
   - bit_offset: 14
     bit_size: 1
     description: PLL3 Ready Interrupt Enable
-    enum: LSIRDYIE
     name: PLL3RDYIE
   - bit_offset: 16
     bit_size: 1
     description: LSI Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: LSIRDYC
   - bit_offset: 17
     bit_size: 1
     description: LSE Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: LSERDYC
   - bit_offset: 18
     bit_size: 1
     description: HSI Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: HSIRDYC
   - bit_offset: 19
     bit_size: 1
     description: HSE Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: HSERDYC
   - bit_offset: 20
     bit_size: 1
     description: PLL Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: PLLRDYC
   - bit_offset: 21
     bit_size: 1
     description: PLL2 Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: PLL2RDYC
   - bit_offset: 22
     bit_size: 1
     description: PLL3 Ready Interrupt Clear
-    enum_write: LSIRDYCW
     name: PLL3RDYC
   - bit_offset: 23
     bit_size: 1
     description: Clock security system interrupt clear
-    enum_write: CSSCW
     name: CSSC
 fieldset/CR:
   description: Clock control register
@@ -1365,12 +1031,10 @@ fieldset/CR:
   - bit_offset: 0
     bit_size: 1
     description: Internal High Speed clock enable
-    enum: HSION
     name: HSION
   - bit_offset: 1
     bit_size: 1
     description: Internal High Speed clock ready flag
-    enum_read: HSIRDYR
     name: HSIRDY
   - bit_offset: 3
     bit_size: 5
@@ -1383,32 +1047,26 @@ fieldset/CR:
   - bit_offset: 16
     bit_size: 1
     description: External High Speed clock enable
-    enum: HSION
     name: HSEON
   - bit_offset: 17
     bit_size: 1
     description: External High Speed clock ready flag
-    enum_read: HSIRDYR
     name: HSERDY
   - bit_offset: 18
     bit_size: 1
     description: External High Speed clock Bypass
-    enum: HSEBYP
     name: HSEBYP
   - bit_offset: 19
     bit_size: 1
     description: Clock Security System enable
-    enum: CSSON
     name: CSSON
   - bit_offset: 24
     bit_size: 1
     description: PLL enable
-    enum: HSION
     name: PLLON
   - bit_offset: 25
     bit_size: 1
     description: PLL clock ready flag
-    enum_read: HSIRDYR
     name: PLLRDY
   - bit_offset: 26
     bit_size: 1
@@ -1417,7 +1075,6 @@ fieldset/CR:
   - bit_offset: 27
     bit_size: 1
     description: PLL2 clock ready flag
-    enum_read: HSIRDYR
     name: PLL2RDY
   - bit_offset: 28
     bit_size: 1
@@ -1426,7 +1083,6 @@ fieldset/CR:
   - bit_offset: 29
     bit_size: 1
     description: PLL3 clock ready flag
-    enum_read: HSIRDYR
     name: PLL3RDY
 fieldset/CSR:
   description: Control/status register (RCC_CSR)
@@ -1434,45 +1090,36 @@ fieldset/CSR:
   - bit_offset: 0
     bit_size: 1
     description: Internal low speed oscillator enable
-    enum: LSION
     name: LSION
   - bit_offset: 1
     bit_size: 1
     description: Internal low speed oscillator ready
-    enum_read: LSIRDYR
     name: LSIRDY
   - bit_offset: 24
     bit_size: 1
     description: Remove reset flag
-    enum_write: RMVFW
     name: RMVF
   - bit_offset: 26
     bit_size: 1
     description: PIN reset flag
-    enum_read: PINRSTFR
     name: PINRSTF
   - bit_offset: 27
     bit_size: 1
     description: POR/PDR reset flag
-    enum_read: PINRSTFR
     name: PORRSTF
   - bit_offset: 28
     bit_size: 1
     description: Software reset flag
-    enum_read: PINRSTFR
     name: SFTRSTF
   - bit_offset: 29
     bit_size: 1
     description: Independent watchdog reset flag
-    enum_read: PINRSTFR
     name: IWDGRSTF
   - bit_offset: 30
     bit_size: 1
     description: Window watchdog reset flag
-    enum_read: PINRSTFR
     name: WWDGRSTF
   - bit_offset: 31
     bit_size: 1
     description: Low-power reset flag
-    enum_read: PINRSTFR
     name: LPWRRSTF