Create rcc_f100.yaml
This commit is contained in:
Grant Miller
parent
9ea9bd5215
commit
d7674ab524
865
data/registers/rcc_f100.yaml
Normal file
865
data/registers/rcc_f100.yaml
Normal file
@ -0,0 +1,865 @@
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---
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block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: CFGR
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description: Clock configuration register (RCC_CFGR)
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byte_offset: 4
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fieldset: CFGR
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- name: CIR
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description: Clock interrupt register (RCC_CIR)
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byte_offset: 8
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fieldset: CIR
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- name: APB2RSTR
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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byte_offset: 12
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fieldset: APB2RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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byte_offset: 16
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fieldset: APB1RSTR
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- name: AHBENR
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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byte_offset: 20
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fieldset: AHBENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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byte_offset: 24
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fieldset: APB2ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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byte_offset: 28
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fieldset: APB1ENR
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- name: BDCR
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description: Backup domain control register (RCC_BDCR)
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byte_offset: 32
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fieldset: BDCR
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- name: CSR
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description: Control/status register (RCC_CSR)
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byte_offset: 36
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fieldset: CSR
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- name: CFGR2
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description: Clock configuration register 2
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byte_offset: 44
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fieldset: CFGR2
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fieldset/AHBENR:
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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fields:
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: SRAMEN
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description: SRAM interface clock enable
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bit_offset: 2
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bit_size: 1
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- name: FLASHEN
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description: FLASH clock enable
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bit_offset: 4
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 6
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bit_size: 1
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- name: FSMCEN
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description: FSMC clock enable
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bit_offset: 8
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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fields:
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- name: TIM2EN
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description: Timer 2 clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: Timer 3 clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM4EN
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description: Timer 4 clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM5EN
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description: Timer 5 clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM6EN
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description: Timer 6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: Timer 7 clock enable
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bit_offset: 5
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bit_size: 1
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- name: TIM12EN
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description: Timer 12 clock enable
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bit_offset: 6
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bit_size: 1
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- name: TIM13EN
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description: Timer 13 clock enable
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bit_offset: 7
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bit_size: 1
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- name: TIM14EN
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description: Timer 14 clock enable
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bit_offset: 8
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI 2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: SPI3EN
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description: SPI 3 clock enable
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bit_offset: 15
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bit_size: 1
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- name: USART2EN
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description: USART 2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART 3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: UART4EN
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description: UART 4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: UART5EN
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description: UART 5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C 1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C 2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: BKPEN
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description: Backup interface clock enable
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bit_offset: 27
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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- name: CECEN
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description: CEC clock enable
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bit_offset: 30
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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fields:
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- name: TIM2RST
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description: Timer 2 reset
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bit_offset: 0
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bit_size: 1
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- name: TIM3RST
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description: Timer 3 reset
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bit_offset: 1
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bit_size: 1
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- name: TIM4RST
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description: Timer 4 reset
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bit_offset: 2
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bit_size: 1
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- name: TIM5RST
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description: Timer 5 reset
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bit_offset: 3
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bit_size: 1
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- name: TIM6RST
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description: Timer 6 reset
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bit_offset: 4
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bit_size: 1
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- name: TIM7RST
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description: Timer 7 reset
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bit_offset: 5
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bit_size: 1
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- name: TIM12RST
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description: Timer 12 reset
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bit_offset: 6
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bit_size: 1
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- name: TIM13RST
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description: Timer 13 reset
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bit_offset: 7
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bit_size: 1
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- name: TIM14RST
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description: Timer 14 reset
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bit_offset: 8
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bit_size: 1
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- name: WWDGRST
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description: Window watchdog reset
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bit_offset: 11
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: SPI3RST
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description: SPI3 reset
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bit_offset: 15
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bit_size: 1
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- name: USART2RST
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description: USART 2 reset
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bit_offset: 17
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bit_size: 1
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- name: USART3RST
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description: USART 3 reset
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bit_offset: 18
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bit_size: 1
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- name: UART4RST
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description: USART 4 reset
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bit_offset: 19
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bit_size: 1
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- name: UART5RST
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description: USART 5 reset
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bit_offset: 20
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: BKPRST
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description: Backup interface reset
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bit_offset: 27
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DACRST
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description: DAC interface reset
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bit_offset: 29
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bit_size: 1
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- name: CECRST
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description: CEC reset
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bit_offset: 30
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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fields:
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- name: AFIOEN
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description: Alternate function I/O clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOAEN
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description: I/O port A clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIOBEN
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description: I/O port B clock enable
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bit_offset: 3
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bit_size: 1
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- name: GPIOCEN
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description: I/O port C clock enable
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bit_offset: 4
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bit_size: 1
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- name: GPIODEN
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description: I/O port D clock enable
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bit_offset: 5
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bit_size: 1
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- name: GPIOEEN
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description: I/O port E clock enable
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bit_offset: 6
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bit_size: 1
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- name: GPIOFEN
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description: I/O port F clock enable
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bit_offset: 7
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bit_size: 1
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- name: GPIOGEN
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description: I/O port G clock enable
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bit_offset: 8
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bit_size: 1
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- name: ADC1EN
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description: ADC 1 interface clock enable
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bit_offset: 9
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bit_size: 1
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- name: TIM1EN
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description: TIM1 Timer clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI1EN
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description: SPI 1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 14
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bit_size: 1
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- name: TIM15EN
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description: TIM15 Timer clock enable
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bit_offset: 16
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bit_size: 1
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- name: TIM16EN
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description: TIM16 Timer clock enable
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bit_offset: 17
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bit_size: 1
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- name: TIM17EN
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description: TIM17 Timer clock enable
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bit_offset: 18
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bit_size: 1
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fieldset/APB2RSTR:
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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fields:
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- name: AFIORST
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description: Alternate function I/O reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 2
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 3
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 4
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bit_size: 1
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- name: GPIODRST
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description: IO port D reset
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bit_offset: 5
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bit_size: 1
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- name: GPIOERST
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description: IO port E reset
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bit_offset: 6
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bit_size: 1
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- name: GPIOFRST
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description: IO port F reset
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bit_offset: 7
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bit_size: 1
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- name: GPIOGRST
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description: IO port G reset
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bit_offset: 8
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bit_size: 1
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- name: ADC1RST
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description: ADC 1 interface reset
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bit_offset: 9
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bit_size: 1
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- name: TIM1RST
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description: TIM1 timer reset
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bit_offset: 11
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bit_size: 1
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- name: SPI1RST
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description: SPI 1 reset
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
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description: USART1 reset
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bit_offset: 14
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bit_size: 1
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- name: TIM15RST
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description: TIM15 timer reset
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bit_offset: 16
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bit_size: 1
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- name: TIM16RST
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description: TIM16 timer reset
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bit_offset: 17
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bit_size: 1
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- name: TIM17RST
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description: TIM17 timer reset
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bit_offset: 18
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bit_size: 1
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fieldset/BDCR:
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description: Backup domain control register (RCC_BDCR)
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fields:
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- name: LSEON
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description: External Low Speed oscillator enable
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bit_offset: 0
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bit_size: 1
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- name: LSERDY
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description: External Low Speed oscillator ready
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bit_offset: 1
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bit_size: 1
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- name: LSEBYP
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description: External Low Speed oscillator bypass
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bit_offset: 2
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bit_size: 1
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||||||
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- name: RTCSEL
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description: RTC clock source selection
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bit_offset: 8
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bit_size: 2
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enum: RTCSEL
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- name: RTCEN
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description: RTC clock enable
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bit_offset: 15
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bit_size: 1
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- name: BDRST
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description: Backup domain software reset
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||||||
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bit_offset: 16
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bit_size: 1
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fieldset/CFGR:
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||||||
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description: Clock configuration register (RCC_CFGR)
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||||||
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fields:
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- name: SW
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||||||
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description: System clock Switch
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||||||
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bit_offset: 0
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||||||
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bit_size: 2
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||||||
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enum: SW
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||||||
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- name: SWS
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||||||
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description: System Clock Switch Status
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||||||
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bit_offset: 2
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||||||
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bit_size: 2
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||||||
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enum_read: SWSR
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||||||
|
- name: HPRE
|
||||||
|
description: AHB prescaler
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 4
|
||||||
|
enum: HPRE
|
||||||
|
- name: PPRE1
|
||||||
|
description: APB Low speed prescaler (APB1)
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 3
|
||||||
|
enum: PPRE1
|
||||||
|
- name: PPRE2
|
||||||
|
description: APB High speed prescaler (APB2)
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 3
|
||||||
|
enum: PPRE1
|
||||||
|
- name: ADCPRE
|
||||||
|
description: ADC prescaler
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
enum: ADCPRE
|
||||||
|
- name: PLLSRC
|
||||||
|
description: PLL entry clock source
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
enum: PLLSRC
|
||||||
|
- name: PLLXTPRE
|
||||||
|
description: HSE divider for PLL entry
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
enum: PLLXTPRE
|
||||||
|
- name: PLLMUL
|
||||||
|
description: PLL Multiplication Factor
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 4
|
||||||
|
enum: PLLMUL
|
||||||
|
- name: MCO
|
||||||
|
description: Microcontroller clock output
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
enum: MCO
|
||||||
|
fieldset/CFGR2:
|
||||||
|
description: Clock configuration register 2
|
||||||
|
fields:
|
||||||
|
- name: PREDIV1
|
||||||
|
description: PREDIV1 division factor
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
enum: PREDIV1
|
||||||
|
fieldset/CIR:
|
||||||
|
description: Clock interrupt register (RCC_CIR)
|
||||||
|
fields:
|
||||||
|
- name: LSIRDYF
|
||||||
|
description: LSI Ready Interrupt flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LSERDYF
|
||||||
|
description: LSE Ready Interrupt flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSIRDYF
|
||||||
|
description: HSI Ready Interrupt flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSERDYF
|
||||||
|
description: HSE Ready Interrupt flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLLRDYF
|
||||||
|
description: PLL Ready Interrupt flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSSF
|
||||||
|
description: Clock Security System Interrupt flag
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: LSIRDYIE
|
||||||
|
description: LSI Ready Interrupt Enable
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: LSERDYIE
|
||||||
|
description: LSE Ready Interrupt Enable
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSIRDYIE
|
||||||
|
description: HSI Ready Interrupt Enable
|
||||||
|
bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSERDYIE
|
||||||
|
description: HSE Ready Interrupt Enable
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLLRDYIE
|
||||||
|
description: PLL Ready Interrupt Enable
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
- name: LSIRDYC
|
||||||
|
description: LSI Ready Interrupt Clear
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: LSERDYC
|
||||||
|
description: LSE Ready Interrupt Clear
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSIRDYC
|
||||||
|
description: HSI Ready Interrupt Clear
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSERDYC
|
||||||
|
description: HSE Ready Interrupt Clear
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLLRDYC
|
||||||
|
description: PLL Ready Interrupt Clear
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSSC
|
||||||
|
description: Clock security system interrupt clear
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CR:
|
||||||
|
description: Clock control register
|
||||||
|
fields:
|
||||||
|
- name: HSION
|
||||||
|
description: Internal High Speed clock enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSIRDY
|
||||||
|
description: Internal High Speed clock ready flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSITRIM
|
||||||
|
description: Internal High Speed clock trimming
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 5
|
||||||
|
- name: HSICAL
|
||||||
|
description: Internal High Speed clock Calibration
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: HSEON
|
||||||
|
description: External High Speed clock enable
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSERDY
|
||||||
|
description: External High Speed clock ready flag
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: HSEBYP
|
||||||
|
description: External High Speed clock Bypass
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSSON
|
||||||
|
description: Clock Security System enable
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLLON
|
||||||
|
description: PLL enable
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLLRDY
|
||||||
|
description: PLL clock ready flag
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CSR:
|
||||||
|
description: Control/status register (RCC_CSR)
|
||||||
|
fields:
|
||||||
|
- name: LSION
|
||||||
|
description: Internal low speed oscillator enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LSIRDY
|
||||||
|
description: Internal low speed oscillator ready
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: RMVF
|
||||||
|
description: Remove reset flag
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: PINRSTF
|
||||||
|
description: PIN reset flag
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
- name: PORRSTF
|
||||||
|
description: POR/PDR reset flag
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: SFTRSTF
|
||||||
|
description: Software reset flag
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: IWDGRSTF
|
||||||
|
description: Independent watchdog reset flag
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: WWDGRSTF
|
||||||
|
description: Window watchdog reset flag
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
- name: LPWRRSTF
|
||||||
|
description: Low-power reset flag
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
enum/ADCPRE:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: Div2
|
||||||
|
description: PCLK2 divided by 2
|
||||||
|
value: 0
|
||||||
|
- name: Div4
|
||||||
|
description: PCLK2 divided by 4
|
||||||
|
value: 1
|
||||||
|
- name: Div6
|
||||||
|
description: PCLK2 divided by 8
|
||||||
|
value: 2
|
||||||
|
- name: Div8
|
||||||
|
description: PCLK2 divided by 16
|
||||||
|
value: 3
|
||||||
|
enum/HPRE:
|
||||||
|
bit_size: 4
|
||||||
|
variants:
|
||||||
|
- name: Div1
|
||||||
|
description: SYSCLK not divided
|
||||||
|
value: 0
|
||||||
|
- name: Div2
|
||||||
|
description: SYSCLK divided by 2
|
||||||
|
value: 8
|
||||||
|
- name: Div4
|
||||||
|
description: SYSCLK divided by 4
|
||||||
|
value: 9
|
||||||
|
- name: Div8
|
||||||
|
description: SYSCLK divided by 8
|
||||||
|
value: 10
|
||||||
|
- name: Div16
|
||||||
|
description: SYSCLK divided by 16
|
||||||
|
value: 11
|
||||||
|
- name: Div64
|
||||||
|
description: SYSCLK divided by 64
|
||||||
|
value: 12
|
||||||
|
- name: Div128
|
||||||
|
description: SYSCLK divided by 128
|
||||||
|
value: 13
|
||||||
|
- name: Div256
|
||||||
|
description: SYSCLK divided by 256
|
||||||
|
value: 14
|
||||||
|
- name: Div512
|
||||||
|
description: SYSCLK divided by 512
|
||||||
|
value: 15
|
||||||
|
enum/MCO:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: NoMCO
|
||||||
|
description: "MCO output disabled, no clock on MCO"
|
||||||
|
value: 0
|
||||||
|
- name: SYSCLK
|
||||||
|
description: System clock selected
|
||||||
|
value: 4
|
||||||
|
- name: HSI
|
||||||
|
description: HSI oscillator clock selected
|
||||||
|
value: 5
|
||||||
|
- name: HSE
|
||||||
|
description: HSE oscillator clock selected
|
||||||
|
value: 6
|
||||||
|
- name: PLL
|
||||||
|
description: PLL clock divided by 2 selected
|
||||||
|
value: 7
|
||||||
|
enum/PLLMUL:
|
||||||
|
bit_size: 4
|
||||||
|
variants:
|
||||||
|
- name: Mul2
|
||||||
|
description: PLL input clock x2
|
||||||
|
value: 0
|
||||||
|
- name: Mul3
|
||||||
|
description: PLL input clock x3
|
||||||
|
value: 1
|
||||||
|
- name: Mul4
|
||||||
|
description: PLL input clock x4
|
||||||
|
value: 2
|
||||||
|
- name: Mul5
|
||||||
|
description: PLL input clock x5
|
||||||
|
value: 3
|
||||||
|
- name: Mul6
|
||||||
|
description: PLL input clock x6
|
||||||
|
value: 4
|
||||||
|
- name: Mul7
|
||||||
|
description: PLL input clock x7
|
||||||
|
value: 5
|
||||||
|
- name: Mul8
|
||||||
|
description: PLL input clock x8
|
||||||
|
value: 6
|
||||||
|
- name: Mul9
|
||||||
|
description: PLL input clock x9
|
||||||
|
value: 7
|
||||||
|
- name: Mul10
|
||||||
|
description: PLL input clock x10
|
||||||
|
value: 8
|
||||||
|
- name: Mul11
|
||||||
|
description: PLL input clock x11
|
||||||
|
value: 9
|
||||||
|
- name: Mul12
|
||||||
|
description: PLL input clock x12
|
||||||
|
value: 10
|
||||||
|
- name: Mul13
|
||||||
|
description: PLL input clock x13
|
||||||
|
value: 11
|
||||||
|
- name: Mul14
|
||||||
|
description: PLL input clock x14
|
||||||
|
value: 12
|
||||||
|
- name: Mul15
|
||||||
|
description: PLL input clock x15
|
||||||
|
value: 13
|
||||||
|
- name: Mul16
|
||||||
|
description: PLL input clock x16
|
||||||
|
value: 14
|
||||||
|
- name: Mul16x
|
||||||
|
description: PLL input clock x16
|
||||||
|
value: 15
|
||||||
|
enum/PLLSRC:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: HSI_Div2
|
||||||
|
description: HSI divided by 2 selected as PLL input clock
|
||||||
|
value: 0
|
||||||
|
- name: HSE_Div_PREDIV
|
||||||
|
description: HSE divided by PREDIV selected as PLL input clock
|
||||||
|
value: 1
|
||||||
|
enum/PLLXTPRE:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Div1
|
||||||
|
description: HSE clock not divided
|
||||||
|
value: 0
|
||||||
|
- name: Div2
|
||||||
|
description: HSE clock divided by 2
|
||||||
|
value: 1
|
||||||
|
enum/PPRE1:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: Div1
|
||||||
|
description: HCLK not divided
|
||||||
|
value: 0
|
||||||
|
- name: Div2
|
||||||
|
description: HCLK divided by 2
|
||||||
|
value: 4
|
||||||
|
- name: Div4
|
||||||
|
description: HCLK divided by 4
|
||||||
|
value: 5
|
||||||
|
- name: Div8
|
||||||
|
description: HCLK divided by 8
|
||||||
|
value: 6
|
||||||
|
- name: Div16
|
||||||
|
description: HCLK divided by 16
|
||||||
|
value: 7
|
||||||
|
enum/PREDIV1:
|
||||||
|
bit_size: 4
|
||||||
|
variants:
|
||||||
|
- name: Div1
|
||||||
|
description: PREDIV input clock not divided
|
||||||
|
value: 0
|
||||||
|
- name: Div2
|
||||||
|
description: PREDIV input clock divided by 2
|
||||||
|
value: 1
|
||||||
|
- name: Div3
|
||||||
|
description: PREDIV input clock divided by 3
|
||||||
|
value: 2
|
||||||
|
- name: Div4
|
||||||
|
description: PREDIV input clock divided by 4
|
||||||
|
value: 3
|
||||||
|
- name: Div5
|
||||||
|
description: PREDIV input clock divided by 5
|
||||||
|
value: 4
|
||||||
|
- name: Div6
|
||||||
|
description: PREDIV input clock divided by 6
|
||||||
|
value: 5
|
||||||
|
- name: Div7
|
||||||
|
description: PREDIV input clock divided by 7
|
||||||
|
value: 6
|
||||||
|
- name: Div8
|
||||||
|
description: PREDIV input clock divided by 8
|
||||||
|
value: 7
|
||||||
|
- name: Div9
|
||||||
|
description: PREDIV input clock divided by 9
|
||||||
|
value: 8
|
||||||
|
- name: Div10
|
||||||
|
description: PREDIV input clock divided by 10
|
||||||
|
value: 9
|
||||||
|
- name: Div11
|
||||||
|
description: PREDIV input clock divided by 11
|
||||||
|
value: 10
|
||||||
|
- name: Div12
|
||||||
|
description: PREDIV input clock divided by 12
|
||||||
|
value: 11
|
||||||
|
- name: Div13
|
||||||
|
description: PREDIV input clock divided by 13
|
||||||
|
value: 12
|
||||||
|
- name: Div14
|
||||||
|
description: PREDIV input clock divided by 14
|
||||||
|
value: 13
|
||||||
|
- name: Div15
|
||||||
|
description: PREDIV input clock divided by 15
|
||||||
|
value: 14
|
||||||
|
- name: Div16
|
||||||
|
description: PREDIV input clock divided by 16
|
||||||
|
value: 15
|
||||||
|
enum/RTCSEL:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: NoClock
|
||||||
|
description: No clock
|
||||||
|
value: 0
|
||||||
|
- name: LSE
|
||||||
|
description: LSE oscillator clock used as RTC clock
|
||||||
|
value: 1
|
||||||
|
- name: LSI
|
||||||
|
description: LSI oscillator clock used as RTC clock
|
||||||
|
value: 2
|
||||||
|
- name: HSE
|
||||||
|
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
||||||
|
value: 3
|
||||||
|
enum/SW:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: HSI
|
||||||
|
description: HSI selected as system clock
|
||||||
|
value: 0
|
||||||
|
- name: HSE
|
||||||
|
description: HSE selected as system clock
|
||||||
|
value: 1
|
||||||
|
- name: PLL
|
||||||
|
description: PLL selected as system clock
|
||||||
|
value: 2
|
||||||
|
enum/SWSR:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: HSI
|
||||||
|
description: HSI oscillator used as system clock
|
||||||
|
value: 0
|
||||||
|
- name: HSE
|
||||||
|
description: HSE oscillator used as system clock
|
||||||
|
value: 1
|
||||||
|
- name: PLL
|
||||||
|
description: PLL used as system clock
|
||||||
|
value: 2
|
||||||
@ -177,7 +177,8 @@ perimap = [
|
|||||||
('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')),
|
('.*:USB_OTG_HS:otghs1_v1_.*', ('otghs', 'v1', 'OTG_HS')),
|
||||||
|
|
||||||
('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')),
|
('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')),
|
||||||
('STM32F10[0123].*:RCC:.*', ('rcc', 'f1', 'RCC')),
|
('STM32F100.*:RCC:.*', ('rcc', 'f100', 'RCC')),
|
||||||
|
('STM32F10[123].*:RCC:.*', ('rcc', 'f1', 'RCC')),
|
||||||
('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')),
|
('STM32F10[57].*:RCC:.*', ('rcc', 'f1cl', 'RCC')),
|
||||||
('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')),
|
('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')),
|
||||||
('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')),
|
('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')),
|
||||||
|
|||||||
Loading…
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Reference in New Issue
Block a user