More accurate USB muxes.

data/registers/rcc_h5.yaml

@@ -1626,11 +1626,11 @@ fieldset/CCIPR5:
     bit_offset: 19
     bit_size: 3
     enum: SAISEL
-  - name: CKPERSEL
+  - name: PERSEL
     description: per_ck clock source selection
     bit_offset: 30
     bit_size: 2
-    enum: CKPERSEL
+    enum: PERSEL
 fieldset/CFGR:
   description: RCC clock configuration register
   fields:
@@ -2107,7 +2107,7 @@ fieldset/SECCFGR:
     description: "Remove reset flag security\r Set and reset by software."
     bit_offset: 12
     bit_size: 1
-  - name: CKPERSELSEC
+  - name: PERSELSEC
     description: "per_ck selection security\r Set and reset by software."
     bit_offset: 13
     bit_size: 1
@@ -2144,18 +2144,6 @@ enum/CECSEL:
   - name: CSI_DIV_122
     description: csi_ker_ck/122 selected as kernel clock
     value: 2
-enum/CKPERSEL:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: hsi_ker_ck selected as kernel clock (default after reset)
-    value: 0
-  - name: CSI
-    description: csi_ker_ck selected as kernel clock
-    value: 1
-  - name: HSE
-    description: hse_ck selected as kernel clock
-    value: 2
 enum/DACHOLDSEL:
   bit_size: 1
   variants:
@@ -2465,6 +2453,18 @@ enum/OCTOSPISEL:
   - name: PER
     description: per_ck selected as kernel clock
     value: 3
+enum/PERSEL:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: hsi_ker_ck selected as kernel clock (default after reset)
+    value: 0
+  - name: CSI
+    description: csi_ker_ck selected as kernel clock
+    value: 1
+  - name: HSE
+    description: hse_ck selected as kernel clock
+    value: 2
 enum/PLLDIV:
   bit_size: 7
   variants:

data/registers/rcc_h50.yaml

@@ -910,11 +910,11 @@ fieldset/CCIPR5:
     bit_offset: 8
     bit_size: 2
     enum: FDCANSEL
-  - name: CKPERSEL
+  - name: PERSEL
     description: per_ck clock source selection
     bit_offset: 30
     bit_size: 2
-    enum: CKPERSEL
+    enum: PERSEL
 fieldset/CFGR:
   description: RCC clock configuration register
   fields:
@@ -1353,18 +1353,6 @@ enum/ADCDACSEL:
   - name: CSI
     description: csi_ker_ck selected as kernel clock
     value: 5
-enum/CKPERSEL:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: hsi_ker_ck selected as kernel clock (default after reset)
-    value: 0
-  - name: CSI
-    description: csi_ker_ck selected as kernel clock
-    value: 1
-  - name: HSE
-    description: hse_ck selected as kernel clock
-    value: 2
 enum/DACHOLDSEL:
   bit_size: 1
   variants:
@@ -1644,6 +1632,18 @@ enum/MCOPRE:
   - name: Div15
     description: Divide by 15
     value: 15
+enum/PERSEL:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: hsi_ker_ck selected as kernel clock (default after reset)
+    value: 0
+  - name: CSI
+    description: csi_ker_ck selected as kernel clock
+    value: 1
+  - name: HSE
+    description: hse_ck selected as kernel clock
+    value: 2
 enum/PLLDIV:
   bit_size: 7
   variants:

data/registers/rcc_h7.yaml

@@ -3081,11 +3081,11 @@ fieldset/D1CCIPR:
     bit_offset: 16
     bit_size: 1
     enum: SDMMCSEL
-  - name: CKPERSEL
+  - name: PERSEL
     description: per_ck clock source selection
     bit_offset: 28
     bit_size: 2
-    enum: CKPERSEL
+    enum: PERSEL
 fieldset/D1CFGR:
   description: RCC Domain 1 Clock Configuration Register
   fields:
@@ -3541,18 +3541,6 @@ enum/CECSEL:
   - name: CSI
     description: csi_ker selected as peripheral clock
     value: 2
-enum/CKPERSEL:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as peripheral clock
-    value: 0
-  - name: CSI
-    description: CSI selected as peripheral clock
-    value: 1
-  - name: HSE
-    description: HSE selected as peripheral clock
-    value: 2
 enum/DFSDMSEL:
   bit_size: 1
   variants:
@@ -3838,6 +3826,18 @@ enum/MCOPRE:
   - name: Div15
     description: Divide by 15
     value: 15
+enum/PERSEL:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: HSI selected as peripheral clock
+    value: 0
+  - name: CSI
+    description: CSI selected as peripheral clock
+    value: 1
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 2
 enum/PLLDIV:
   bit_size: 7
   variants:

data/registers/rcc_h7ab.yaml

@@ -2027,11 +2027,11 @@ fieldset/D1CCIPR:
     bit_offset: 16
     bit_size: 1
     enum: SDMMCSEL
-  - name: CKPERSEL
+  - name: PERSEL
     description: per_ck clock source selection
     bit_offset: 28
     bit_size: 2
-    enum: CKPERSEL
+    enum: PERSEL
 fieldset/D1CFGR:
   description: RCC Domain 1 Clock Configuration Register
   fields:
@@ -2455,18 +2455,6 @@ enum/CECSEL:
   - name: CSI
     description: csi_ker selected as peripheral clock
     value: 2
-enum/CKPERSEL:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as peripheral clock
-    value: 0
-  - name: CSI
-    description: CSI selected as peripheral clock
-    value: 1
-  - name: HSE
-    description: HSE selected as peripheral clock
-    value: 2
 enum/DFSDMSEL:
   bit_size: 1
   variants:
@@ -2752,6 +2740,18 @@ enum/MCOPRE:
   - name: Div15
     description: Divide by 15
     value: 15
+enum/PERSEL:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: HSI selected as peripheral clock
+    value: 0
+  - name: CSI
+    description: CSI selected as peripheral clock
+    value: 1
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 2
 enum/PLLDIV:
   bit_size: 7
   variants:

data/registers/rcc_h7rm0433.yaml

@@ -3064,11 +3064,11 @@ fieldset/D1CCIPR:
     bit_offset: 16
     bit_size: 1
     enum: SDMMCSEL
-  - name: CKPERSEL
+  - name: PERSEL
     description: per_ck clock source selection
     bit_offset: 28
     bit_size: 2
-    enum: CKPERSEL
+    enum: PERSEL
 fieldset/D1CFGR:
   description: RCC Domain 1 Clock Configuration Register
   fields:
@@ -3524,18 +3524,6 @@ enum/CECSEL:
   - name: CSI
     description: csi_ker selected as peripheral clock
     value: 2
-enum/CKPERSEL:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as peripheral clock
-    value: 0
-  - name: CSI
-    description: CSI selected as peripheral clock
-    value: 1
-  - name: HSE
-    description: HSE selected as peripheral clock
-    value: 2
 enum/DFSDMSEL:
   bit_size: 1
   variants:
@@ -3821,6 +3809,18 @@ enum/MCOPRE:
   - name: Div15
     description: Divide by 15
     value: 15
+enum/PERSEL:
+  bit_size: 2
+  variants:
+  - name: HSI
+    description: HSI selected as peripheral clock
+    value: 0
+  - name: CSI
+    description: CSI selected as peripheral clock
+    value: 1
+  - name: HSE
+    description: HSE selected as peripheral clock
+    value: 2
 enum/PLLDIV:
   bit_size: 7
   variants:

stm32-data-gen/src/rcc.rs

@@ -285,6 +285,9 @@ impl ParsedRccs {
             ("I2C2", &["I2C1235"]),
             ("I2C3", &["I2C1235"]),
             ("I2C5", &["I2C1235"]),
+            ("USB", &["USB", "CLK48", "ICLK"]),
+            ("USB_OTG_FS", &["USB", "CLK48", "ICLK"]),
+            ("USB_OTG_HS", &["USB", "CLK48", "ICLK"]),
         ];
 
         let rcc = self.rccs.get(rcc_version)?;
@@ -315,7 +318,20 @@ impl ParsedRccs {
                 }
                 rcc::KernelClock::Mux(mux.mux.clone())
             }
-            None => rcc::KernelClock::Clock(maybe_kernel_clock),
+            None => {
+                if peri_name.starts_with("USB") {
+                    if rcc_version.starts_with("f1") || rcc_version.starts_with("f3") {
+                        maybe_kernel_clock = "USB".to_string();
+                    } else if rcc_version.starts_with("f2") {
+                        maybe_kernel_clock = "PLL1_Q".to_string();
+                    } else if rcc_version.starts_with("l1") {
+                        maybe_kernel_clock = "PLL1_VCO_DIV_2".to_string();
+                    } else {
+                        panic!("rcc_{}: peripheral {} missing mux", rcc_version, peri_name)
+                    }
+                }
+                rcc::KernelClock::Clock(maybe_kernel_clock)
+            }
         };
 
         Some(peripheral::Rcc {