From d5d131a702fad345121ffa8df7b2e710ea41c83d Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Tue, 21 Nov 2023 14:57:43 +0000 Subject: [PATCH] rcc: g4,l5: add missing enums for FDCANSEL; fix a few incorrect descs --- data/registers/rcc_g4.yaml | 19 ++++++++++++++++--- data/registers/rcc_l5.yaml | 13 +++++++++++++ 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index 8100553..67cf1ec 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1006,17 +1006,18 @@ fieldset/CCIPR: bit_offset: 18 bit_size: 2 - name: SAI1SEL - description: Low power timer 2 clock source selection + description: SAI1 clock source selection bit_offset: 20 bit_size: 2 - name: I2S23SEL - description: SAI1 clock source selection + description: I2S23 clock source selection bit_offset: 22 bit_size: 2 - name: FDCANSEL - description: SAI2 clock source selection + description: FDCAN clock source selection bit_offset: 24 bit_size: 2 + enum: FDCANSEL - name: CLK48SEL description: 48 MHz clock source selection bit_offset: 26 @@ -1352,6 +1353,18 @@ enum/ADCSEL: - name: SYS description: System clock selected as ADC clock value: 2 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: HSE used as FDCAN clock source + value: 0 + - name: PLL1_Q + description: PLLQCLK used as FDCAN clock source + value: 1 + - name: PCLK1 + description: PCLK used as FDCAN clock source + value: 2 enum/CLK48SEL: bit_size: 2 variants: diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 56959ec..6e74237 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1374,6 +1374,7 @@ fieldset/CCIPR: description: FDCAN clock source selection bit_offset: 24 bit_size: 2 + enum: FDCANSEL - name: CLK48SEL description: 48 MHz clock source selection bit_offset: 26 @@ -1937,6 +1938,18 @@ enum/ADCSEL: - name: SYS description: SYSCLK clock selected value: 3 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: HSE clock selected + value: 0 + - name: PLL1_Q + description: PLL "Q" clock selected + value: 1 + - name: PLLSAI1_P + description: PLLSAI "P" clock selected + value: 2 enum/CLK48SEL: bit_size: 2 variants: