From d5950c28936b62118b3d5b4b421ec3f3923010ec Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 11 Jan 2024 00:11:10 +0800 Subject: [PATCH] apply transform on syscfg_f0 --- data/registers/syscfg_f0.yaml | 376 +++++++++------------------------- transforms/SYSCFG_F0.yaml | 13 ++ 2 files changed, 114 insertions(+), 275 deletions(-) create mode 100644 transforms/SYSCFG_F0.yaml diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml index de839ae..7a36165 100644 --- a/data/registers/syscfg_f0.yaml +++ b/data/registers/syscfg_f0.yaml @@ -25,125 +25,179 @@ fieldset/CFGR1: bit_size: 2 enum: MEM_MODE - name: PA11_PA12_RMP - description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) + description: | + PA11 and PA12 remapping bit for small packages (28 and 20 pins) + 0: Pin pair PA9/PA10 mapped on the pins + 1: Pin pair PA11/PA12 mapped instead of PA9/PA10 bit_offset: 4 bit_size: 1 - enum: PA11_PA12_RMP - name: IR_MOD description: IR Modulation Envelope signal selection bit_offset: 6 bit_size: 2 enum: IR_MOD - name: ADC_DMA_RMP - description: ADC DMA remapping bit + description: | + ADC DMA remapping bit + 0: ADC DMA request mapped on DMA channel 1 + 1: ADC DMA request mapped on DMA channel 2 bit_offset: 8 bit_size: 1 - enum: ADC_DMA_RMP - name: USART1_TX_DMA_RMP - description: USART1_TX DMA remapping bit + description: | + USART1_TX DMA remapping bit + 0: USART1_TX DMA request mapped on DMA channel 2 + 1: USART1_TX DMA request mapped on DMA channel 4 bit_offset: 9 bit_size: 1 - enum: USART1_TX_DMA_RMP - name: USART1_RX_DMA_RMP - description: USART1_RX DMA request remapping bit + description: | + USART1_RX DMA request remapping bit + 0: USART1_RX DMA request mapped on DMA channel 3 + 1: USART1_RX DMA request mapped on DMA channel 5 bit_offset: 10 bit_size: 1 - enum: USART1_RX_DMA_RMP - name: TIM16_DMA_RMP - description: TIM16 DMA request remapping bit + description: | + TIM16 DMA request remapping bit + 0: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 + 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - enum: TIM16_DMA_RMP - name: TIM17_DMA_RMP - description: TIM17 DMA request remapping bit + description: | + TIM17 DMA request remapping bit + 0: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 + 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - enum: TIM17_DMA_RMP - name: TIM16_DMA_RMP2 - description: TIM16 alternate DMA request remapping bit + description: | + TIM16 alternate DMA request remapping bit + 0: TIM16 DMA request mapped according to TIM16_DMA_RMP bit + 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 bit_offset: 13 bit_size: 1 - enum: TIM16_DMA_RMP2 - name: TIM17_DMA_RMP2 - description: TIM17 alternate DMA request remapping bit + description: | + TIM17 alternate DMA request remapping bit + 0: TIM17 DMA request mapped according to TIM16_DMA_RMP bit + 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 bit_offset: 14 bit_size: 1 - enum: TIM17_DMA_RMP2 - name: I2C_PB6_FMP - description: Fast Mode Plus (FM plus) driving capability activation bits. + description: | + Fast Mode Plus (FM plus) driving capability activation bits. + 0: PB6 pin operate in standard mode + 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed bit_offset: 16 bit_size: 1 - enum: I2C_PB6_FMP + enum: FMP - name: I2C_PB7_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB7 pin operate in standard mode + 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed bit_offset: 17 bit_size: 1 - enum: I2C_PB7_FMP + enum: FMP - name: I2C_PB8_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB8 pin operate in standard mode + 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed bit_offset: 18 bit_size: 1 - enum: I2C_PB8_FMP + enum: FMP - name: I2C_PB9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits. + description: | + Fast Mode Plus (FM+) driving capability activation bits. + 0: PB9 pin operate in standard mode + 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed bit_offset: 19 bit_size: 1 - enum: I2C_PB9_FMP + enum: FMP - name: I2C1_FMP - description: FM+ driving capability activation for I2C1 + description: | + FM+ driving capability activation for I2C1 + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers bit_offset: 20 bit_size: 1 - enum: I2C1_FMP + enum: FMP - name: I2C2_FMP - description: FM+ driving capability activation for I2C2 + description: | + FM+ driving capability activation for I2C2 + 0: FM+ mode is controlled by I2C_Pxx_FMP bits only + 1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers bit_offset: 21 bit_size: 1 - enum: I2C2_FMP + enum: FMP - name: I2C_PA9_FMP - description: Fast Mode Plus (FM+) driving capability activation bits + description: | + Fast Mode Plus (FM+) driving capability activation bits + 0: PA9 pin operate in standard mode + 1: I2C FM+ mode enabled on PA9 and the Speed control is bypassed bit_offset: 22 bit_size: 1 - enum: I2C_PA9_FMP + enum: FMP - name: I2C_PA10_FMP - description: Fast Mode Plus (FM+) driving capability activation bits + description: | + Fast Mode Plus (FM+) driving capability activation bits + 0: PA10 pin operate in standard mode + 1: I2C FM+ mode enabled on PA10 and the Speed control is bypassed bit_offset: 23 bit_size: 1 - enum: I2C_PA10_FMP + enum: FMP - name: SPI2_DMA_RMP - description: SPI2 DMA request remapping bit + description: | + SPI2 DMA request remapping bit + 0: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively + 1: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 24 bit_size: 1 - enum: SPI2_DMA_RMP - name: USART2_DMA_RMP - description: USART2 DMA request remapping bit + description: | + USART2 DMA request remapping bit + 0: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively + 1: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 25 bit_size: 1 - enum: USART2_DMA_RMP - name: USART3_DMA_RMP - description: USART3 DMA request remapping bit + description: | + USART3 DMA request remapping bit + 0: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) + 1: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively bit_offset: 26 bit_size: 1 - enum: USART3_DMA_RMP - name: I2C1_DMA_RMP - description: I2C1 DMA request remapping bit + description: | + I2C1 DMA request remapping bit + 0: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively + 1: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively bit_offset: 27 bit_size: 1 - enum: I2C1_DMA_RMP - name: TIM1_DMA_RMP - description: TIM1 DMA request remapping bit + description: | + TIM1 DMA request remapping bit + 0: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively + 1: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 bit_offset: 28 bit_size: 1 - enum: TIM1_DMA_RMP - name: TIM2_DMA_RMP - description: TIM2 DMA request remapping bit + description: | + TIM2 DMA request remapping bit + 0: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively + 1: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 bit_offset: 29 bit_size: 1 - enum: TIM2_DMA_RMP - name: TIM3_DMA_RMP - description: TIM3 DMA request remapping bit + description: | + TIM3 DMA request remapping bit + 0: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 + 1: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 bit_offset: 30 bit_size: 1 - enum: TIM3_DMA_RMP fieldset/CFGR2: description: configuration register 2 fields: @@ -151,17 +205,14 @@ fieldset/CFGR2: description: Cortex-M0 LOCKUP bit enable bit bit_offset: 0 bit_size: 1 - enum: LOCKUP_LOCK - name: SRAM_PARITY_LOCK description: SRAM parity lock bit bit_offset: 1 bit_size: 1 - enum: SRAM_PARITY_LOCK - name: PVD_LOCK description: PVD lock enable bit bit_offset: 2 bit_size: 1 - enum: PVD_LOCK - name: SRAM_PEF description: SRAM parity flag bit_offset: 8 @@ -176,43 +227,7 @@ fieldset/EXTICR: array: len: 4 stride: 4 -enum/ADC_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: ADC DMA request mapped on DMA channel 1 - value: 0 - - name: Remapped - description: ADC DMA request mapped on DMA channel 2 - value: 1 -enum/I2C1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively - value: 0 - - name: Remapped - description: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively - value: 1 -enum/I2C1_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers - value: 1 -enum/I2C2_FMP: - bit_size: 1 - variants: - - name: Standard - description: FM+ mode is controlled by I2C_Pxx_FMP bits only - value: 0 - - name: FMP - description: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers - value: 1 -enum/I2C_PA10_FMP: +enum/FMP: bit_size: 1 variants: - name: Standard @@ -221,51 +236,6 @@ enum/I2C_PA10_FMP: - name: FMP description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed value: 1 -enum/I2C_PA9_FMP: - bit_size: 1 - variants: - - name: Standard - description: PA9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PA9 and the Speed control is bypassed - value: 1 -enum/I2C_PB6_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB6 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed - value: 1 -enum/I2C_PB7_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB7 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB7 and the Speed control is bypassed - value: 1 -enum/I2C_PB8_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB8 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB8 and the Speed control is bypassed - value: 1 -enum/I2C_PB9_FMP: - bit_size: 1 - variants: - - name: Standard - description: PB9 pin operate in standard mode - value: 0 - - name: FMP - description: I2C FM+ mode enabled on PB9 and the Speed control is bypassed - value: 1 enum/IR_MOD: bit_size: 2 variants: @@ -278,15 +248,6 @@ enum/IR_MOD: - name: USART4 description: USART4 selected value: 2 -enum/LOCKUP_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input - value: 1 enum/MEM_MODE: bit_size: 2 variants: @@ -302,138 +263,3 @@ enum/MEM_MODE: - name: SRAM description: Embedded SRAM mapped at 0x0000_0000 value: 3 -enum/PA11_PA12_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: Pin pair PA9/PA10 mapped on the pins - value: 0 - - name: Remapped - description: Pin pair PA11/PA12 mapped instead of PA9/PA10 - value: 1 -enum/PVD_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: PVD interrupt disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: PVD interrupt connected to TIM1/15/16/17 Break input - value: 1 -enum/SPI2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively - value: 0 - - name: Remapped - description: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively - value: 1 -enum/SRAM_PARITY_LOCK: - bit_size: 1 - variants: - - name: Disconnected - description: SRAM parity error disconnected from TIM1/15/16/17 Break input - value: 0 - - name: Connected - description: SRAM parity error connected to TIM1/15/16/17 Break input - value: 1 -enum/TIM16_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 - value: 0 - - name: Remapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 - value: 1 -enum/TIM16_DMA_RMP2: - bit_size: 1 - variants: - - name: NotAlternateRemapped - description: TIM16 DMA request mapped according to TIM16_DMA_RMP bit - value: 0 - - name: AlternateRemapped - description: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 - value: 1 -enum/TIM17_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 - value: 0 - - name: Remapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 - value: 1 -enum/TIM17_DMA_RMP2: - bit_size: 1 - variants: - - name: NotAlternateRemapped - description: TIM17 DMA request mapped according to TIM16_DMA_RMP bit - value: 0 - - name: AlternateRemapped - description: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 - value: 1 -enum/TIM1_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively - value: 0 - - name: Remapped - description: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 - value: 1 -enum/TIM2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively - value: 0 - - name: Remapped - description: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 - value: 1 -enum/TIM3_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 - value: 0 - - name: Remapped - description: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 - value: 1 -enum/USART1_RX_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART1_RX DMA request mapped on DMA channel 3 - value: 0 - - name: Remapped - description: USART1_RX DMA request mapped on DMA channel 5 - value: 1 -enum/USART1_TX_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART1_TX DMA request mapped on DMA channel 2 - value: 0 - - name: Remapped - description: USART1_TX DMA request mapped on DMA channel 4 - value: 1 -enum/USART2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively - value: 0 - - name: Remapped - description: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively - value: 1 -enum/USART3_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) - value: 0 - - name: Remapped - description: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively - value: 1 diff --git a/transforms/SYSCFG_F0.yaml b/transforms/SYSCFG_F0.yaml new file mode 100644 index 0000000..e1fd25f --- /dev/null +++ b/transforms/SYSCFG_F0.yaml @@ -0,0 +1,13 @@ +transforms: + - !DeleteEnums + from: .*_RMP2? + bit_size: 1 + keep_desc: true + + - !MergeEnums + from: .*_FMP + to: FMP + keep_desc: true + + - !DeleteEnums + from: ^(LOCKUP_LOCK|PVD_LOCK|SRAM_PARITY_LOCK)$