Use signals from MCU xml
Use MCU xml as a source of truth for signal and pin assignments This has some nice side-effects as exposing analog signals without handling them as special cases and not having __some__ (or maybe all) pins not exposed in the chip package occur in the yamls But the most useful part probably is the better support for F1 series, which don't have all pins defined in GPIO due to not being remappable
This commit is contained in:
Nikita Strygin
Dario Nieuwenhuis
parent
8e9e8522d1
commit
d50f6b4676
@ -471,6 +471,7 @@ def parse_pin_name(pin_name):
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return port, pin
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def get_peri_addr(defines, pname):
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possible_defines = alt_peri_defines.get(pname) or [f'{pname}_BASE', pname]
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for d in possible_defines:
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@ -478,6 +479,7 @@ def get_peri_addr(defines, pname):
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return addr
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return None
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def parse_chips():
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os.makedirs('data/chips', exist_ok=True)
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@ -503,7 +505,7 @@ def parse_chips():
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print(f)
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r = xmltodict.parse(open(f, 'rb'))['Mcu']
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r = xmltodict.parse(open(f, 'rb'), force_list=['Signal'])['Mcu']
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package_names = expand_name(r['@RefName'])
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package_rams = r['Ram']
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@ -590,25 +592,6 @@ def parse_chips():
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chip_af = removesuffix(chip_af, '_gpio_v1_0')
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chip_af = af[chip_af]
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# Analog pins are in the MCU XML, not in the GPIO XML.
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analog_pins = {}
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for pin_name, pin in chip['pins'].items():
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for signal in children(pin, 'Signal'):
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if p := parse_signal_name(signal['@Name']):
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peri_name, signal_name = p
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if peri_name.startswith('ADC') or peri_name.startswith('DAC') or peri_name.startswith('COMP') or peri_name.startswith('OPAMP'):
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if peri_name not in analog_pins:
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analog_pins[peri_name] = []
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analog_pins[peri_name].append(OrderedDict({
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'pin': pin_name,
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'signal': signal_name,
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}))
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for pname, p in analog_pins.items():
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p = remove_duplicates(p)
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sort_pins(p)
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analog_pins[pname] = p
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cores = []
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for core_xml in children(chip['xml'], 'Core'):
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core_name = corename(core_xml)
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@ -656,6 +639,25 @@ def parse_chips():
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if pname not in peri_kinds and (addr := get_peri_addr(defines, pname)):
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peri_kinds[pname] = 'unknown'
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# get possible used GPIOs for each peripheral from the chip xml
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# it's not the full info we would want (stuff like AFIO info which comes from GPIO xml),
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# but we actually need to use it because of F1 line
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# which doesn't include non-remappable peripherals in GPIO xml
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# and some weird edge cases like STM32F030C6 (see merge_periph_pins_info)
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periph_pins = OrderedDict()
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for pin_name, pin in chip['pins'].items():
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for signal in pin['Signal']:
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signal = signal['@Name']
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# TODO: What are those signals (well, GPIO is clear) Which peripheral do they belong to?
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if signal not in {'GPIO', 'CEC', 'AUDIOCLK', 'VDDTCXO'}:
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periph, signal = signal.split('_', maxsplit=1)
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pins = periph_pins.setdefault(periph, [])
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pins.append(OrderedDict(pin=pin_name, signal=signal))
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for periph, pins in periph_pins.items():
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pins = remove_duplicates(pins)
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sort_pins(pins)
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periph_pins[periph] = pins
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peris = {}
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for pname, pkind in peri_kinds.items():
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addr = get_peri_addr(defines, pname)
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@ -672,9 +674,12 @@ def parse_chips():
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if block := match_peri(chip_name + ':' + pname + ':' + pkind):
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p['block'] = block
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if pins := chip_af.get(pname):
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p['pins'] = pins
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elif pins := analog_pins.get(pname):
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if pins := periph_pins.get(pname):
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# merge the core xml info with GPIO xml info to hopefully get the full picture
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# if the peripheral does not exist in the GPIO xml (one of the notable one is ADC)
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# it probably doesn't need any AFIO writes to work
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if af_pins := chip_af.get(pname):
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pins = merge_periph_pins_info('STM32F1' in chip_name, pname, pins, af_pins)
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p['pins'] = pins
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if chip_nvic in chip_interrupts:
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@ -806,6 +811,44 @@ def parse_chips():
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f.write(yaml.dump(chip, width=500))
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SIGNAL_REMAP = {
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# for some godforsaken reason UART4's and UART5's CTS are called CTS_NSS in the GPIO xml
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# so try to match with these
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'CTS': 'CTS_NSS'
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}
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def merge_periph_pins_info(is_f1, periph_name, core_pins, af_pins):
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if is_f1:
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# TODO: actually handle the F1 AFIO information when it will be extracted
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return core_pins
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# covert to dict
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af_pins = {(v['pin'], v['signal']): v for v in af_pins}
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for pin in core_pins:
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af = af_pins.get((pin['pin'], pin['signal']), {'af': None})['af']
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# try to look for a signal with another name
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if af is None and (remap := SIGNAL_REMAP.get(pin['signal'])):
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af = af_pins.get((pin['pin'], remap), {'af': None})['af']
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# it appears that for __some__ STM32 MCUs there is no AFIO specified in GPIO file
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# (notably - STM32F030C6 with it's I2C1 on PF6 and PF7)
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# but the peripheral can actually be mapped to different pins
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# this breaks embassy's model, so we pretend that it's AF 0
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# Reference Manual states that there's no GPIOF_AFR register
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# but according to Cube-generated core it's OK to write to AFIO reg, it seems to be ignored
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# TODO: are there any more signals that have this "feature"
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if af is None and periph_name == 'I2C1':
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af = 0
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if af is not None:
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# Kinda not nice to modify this dict, but doesn't seem to be a problem
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pin['af'] = af
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return core_pins
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pass
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af = {}
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