Add support for parsing dual core chips
This modifies the chip format to include an array of cores, and within each core the interrupts and peripherals for that core.
This commit is contained in:
Ulf Lilleengen
parent
83b10acc02
commit
d4fad162ac
138
parse.py
138
parse.py
@ -13,6 +13,12 @@ def removeprefix(value: str, prefix: str, /) -> str:
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else:
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return value[:]
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def corename(d):
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if m := re.match('.*Cortex-M(\d+)(\+?)', d):
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name = "cm" + str(m.group(1))
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if m.group(2) == "+":
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name += "p"
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return name
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def removesuffix(value: str, suffix: str, /) -> str:
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if value.endswith(suffix):
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@ -134,6 +140,8 @@ def parse_value(val, defines):
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def parse_header(f):
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irqs = {}
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defines = {}
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cores = []
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cur_core = 'all'
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accum = ''
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for l in open(f, 'r', encoding='utf-8', errors='ignore'):
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@ -144,11 +152,54 @@ def parse_header(f):
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continue
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accum = ''
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# Scoped by a single core
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if m:= re.match('.*if defined.*CORE_CM(\\d+)(PLUS)?.*', l):
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cur_core = "cm" + str(m.group(1))
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if m.group(2) != None:
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cur_core += "p"
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#print("Cur core is ", cur_core, "matched", l)
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found = False
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for core in cores:
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if core == cur_core:
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found = True
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if not found:
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cores.append(cur_core)
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#print("Switching to core", cur_core, "for", f)
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elif m:= re.match('.*else.*', l):
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cur_core = "all"
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if m:= re.match('.*else.*CORE_CM(\\d+)(PLUS)?.*', l):
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cur_core = "cm" + str(m.group(1))
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if m.group(2) != None:
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cur_core += "p"
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#print("Cur core is ", cur_core, "matched", l)
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elif len(cores) > 1:
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# Pick the second core assuming we've already parsed one
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cur_core = cores[1]
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found = False
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for core in cores:
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if core == cur_core:
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found = True
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if not found:
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cores.append(cur_core)
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#print("Switching to core", cur_core, "for", f)
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elif m:= re.match('.*endif.*', l):
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#print("Switching to common core for", f)
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cur_core = "all"
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if cur_core not in irqs:
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#print("Registering new core", cur_core)
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irqs[cur_core] = {}
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if cur_core not in defines:
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defines[cur_core] = {}
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if m := re.match('([a-zA-Z0-9_]+)_IRQn += (\\d+),? +/\\*!< (.*) \\*/', l):
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irqs[m.group(1)] = int(m.group(2))
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#print("Found irq for", cur_core)
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irqs[cur_core][m.group(1)] = int(m.group(2))
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if m := re.match('#define +([0-9A-Za-z_]+)\\(', l):
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defines[m.group(1)] = -1
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defines[cur_core][m.group(1)] = -1
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if m := re.match('#define +([0-9A-Za-z_]+) +(.*)', l):
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name = m.group(1)
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val = m.group(2)
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@ -156,10 +207,23 @@ def parse_header(f):
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if name == 'FLASH_SIZE':
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continue
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val = val.split('/*')[0].strip()
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val = parse_value(val, defines)
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defines[name] = val
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val = parse_value(val, defines[cur_core])
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#print("Found define for", cur_core)
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defines[cur_core][name] = val
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#print("Found", len(cores), "cores for", f)
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#print("Found", len(irqs['all']), "shared interrupts for", f)
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if len(cores) == 0:
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cores.append("all")
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for core in cores:
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if core != "all":
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irqs[core].update(irqs['all'])
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defines[core].update(defines['all'])
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return {
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'cores': cores,
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'interrupts': irqs,
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'defines': defines,
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}
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@ -240,14 +304,17 @@ perimap = [
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('.*:DAC:dacif_v3_0', 'dac_v2/DAC'),
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('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
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('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
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('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
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('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
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('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
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('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
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('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
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('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
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('STM32WL55.*:SYS:.*', 'syscfg_wl55/SYSCFG'),
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('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
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('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
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('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
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('STM32WL.*:RCC:.*', 'rcc_wl55/RCC'),
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('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
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('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
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('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
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@ -266,10 +333,10 @@ rng_clock_map = [
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('STM32L4.*:RNG:.*', 'AHB2'),
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('STM32F4.*:RNG:.*', 'AHB2'),
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('STM32H7.*:RNG:.*', 'AHB2'),
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('STM32WB55.*:RNG:.*', 'AHB3')
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('STM32WB55.*:RNG:.*', 'AHB3'),
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('STM32WL55.*:RNG:.*', 'AHB3')
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]
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def match_peri(peri):
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for r, block in perimap:
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if re.match(r, peri):
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@ -368,16 +435,28 @@ def parse_chips():
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core = r['Core']
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family = r['@Family']
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# multicores have a list here. Just keep the first, to not break the schema.
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cores = []
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if isinstance(core, list):
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core = core[0]
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for core in core:
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cores.append(OrderedDict(
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{
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'name': corename(core),
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'peripherals': {},
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}))
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else:
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cores.append(OrderedDict(
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{
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'name': corename(core),
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'peripherals': {},
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}))
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if chip_name not in chips:
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chips[chip_name] = OrderedDict({
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'name': chip_name,
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'family': family,
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'line': r['@Line'],
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'core': core,
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'cores': cores,
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'flash': flash,
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'ram': ram,
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'gpio_af': gpio_af,
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@ -411,7 +490,6 @@ def parse_chips():
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continue
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if pname.startswith('ADC'):
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if not 'ADC_COMMON' in peris:
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print(f'adding ADC_COMMON')
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peris['ADC_COMMON'] = 'ADC_COMMON:'+removesuffix(ip['@Version'], '_Cube')
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peris[pname] = pkind
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pins[pname] = []
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@ -458,18 +536,33 @@ def parse_chips():
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raise Exception("missing header for {}".format(chip_name))
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h = headers_parsed[h]
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chip['interrupts'] = h['interrupts']
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# print("Got", len(chip['cores']), "cores")
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for core in chip['cores']:
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core_name = core['name']
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if not core_name in h['interrupts'] or not core_name in h['defines']:
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core_name = 'all'
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#print("Defining for core", core_name)
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# Gather all interrupts and defines for this core
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interrupts = h['interrupts'][core_name]
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defines = h['defines'][core_name]
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core['interrupts'] = interrupts
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# print("INterrupts for", core, ":", interrupts)
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#print("Defines for", core, ":", defines)
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peris = {}
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for pname, pkind in chip['peripherals'].items():
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addr = h['defines'].get(pname)
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addr = defines.get(pname)
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if addr is None:
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if pname == 'ADC_COMMON':
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addr = h['defines'].get('ADC1_COMMON')
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addr = defines.get('ADC_COMMON')
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if addr is None:
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addr = h['defines'].get('ADC12_COMMON')
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addr = defines.get('ADC1_COMMON')
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if addr is None:
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addr = h['defines'].get('ADC123_COMMON')
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addr = defines.get('ADC12_COMMON')
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if addr is None:
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addr = defines.get('ADC123_COMMON')
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if addr is None:
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continue
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@ -507,7 +600,7 @@ def parse_chips():
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# Handle GPIO specially.
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for p in range(20):
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port = 'GPIO' + chr(ord('A')+p)
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if addr := h['defines'].get(port + '_BASE'):
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if addr := defines.get(port + '_BASE'):
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block = 'gpio_v2/GPIO'
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if chip['family'] == 'STM32F1':
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block = 'gpio_v1/GPIO'
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@ -519,7 +612,7 @@ def parse_chips():
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peris[port] = p
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# Handle DMA specially.
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for dma in ('DMA1', "DMA2"):
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if addr := h['defines'].get(dma + '_BASE'):
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if addr := defines.get(dma + '_BASE'):
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block = 'dma_v1/DMA'
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if chip['family'] in ('STM32F4', 'STM32F7', 'STM32H7'):
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block = 'dma_v2/DMA'
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@ -531,7 +624,7 @@ def parse_chips():
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peris[dma] = p
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# EXTI is not in the cubedb XMLs
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if addr := h['defines'].get('EXTI_BASE'):
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if addr := defines.get('EXTI_BASE'):
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peris['EXTI'] = OrderedDict({
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'address': addr,
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'kind': 'EXTI',
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@ -539,7 +632,7 @@ def parse_chips():
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})
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# FLASH is not in the cubedb XMLs
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if addr := h['defines'].get('FLASH_R_BASE'):
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if addr := defines.get('FLASH_R_BASE'):
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kind = 'FLASH:' + chip_name[:7] + '_flash_v1_0'
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flash_peri = OrderedDict({
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'address': addr,
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@ -550,7 +643,7 @@ def parse_chips():
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peris['FLASH'] = flash_peri
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# DBGMCU is not in the cubedb XMLs
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if addr := h['defines'].get('DBGMCU_BASE'):
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if addr := defines.get('DBGMCU_BASE'):
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kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0'
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dbg_peri = OrderedDict({
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'address': addr,
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@ -561,7 +654,7 @@ def parse_chips():
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peris['DBGMCU'] = dbg_peri
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# CRS is not in the cubedb XMLs
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if addr := h['defines'].get('CRS_BASE'):
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if addr := defines.get('CRS_BASE'):
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kind = 'CRS:' + chip_name[:7] + '_crs_v1_0'
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crs_peri = OrderedDict({
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'address': addr,
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@ -570,10 +663,11 @@ def parse_chips():
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if block := match_peri(kind):
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crs_peri['block'] = block
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peris['CRS'] = crs_peri
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chip['peripherals'] = peris
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core['peripherals'] = peris
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# remove all pins from the root of the chip before emitting.
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del chip['pins']
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del chip['peripherals']
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with open('data/chips/'+chip_name+'.yaml', 'w') as f:
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f.write(yaml.dump(chip))
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