diff --git a/data/registers/flash_u5.yaml b/data/registers/flash_u5.yaml new file mode 100644 index 0000000..c3640ce --- /dev/null +++ b/data/registers/flash_u5.yaml @@ -0,0 +1,3306 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: "FLASH access control register " + byte_offset: 0 + fieldset: ACR + - name: NSKEYR + description: "FLASH non-secure key register " + byte_offset: 8 + fieldset: NSKEYR + - name: SECKEYR + description: "FLASH secure key register " + byte_offset: 12 + fieldset: SECKEYR + - name: OPTKEYR + description: "FLASH option key register " + byte_offset: 16 + fieldset: OPTKEYR + - name: PDKEY1R + description: "FLASH bank 1 power-down key register " + byte_offset: 24 + fieldset: PDKEY1R + - name: PDKEY2R + description: "FLASH bank 2 power-down key register " + byte_offset: 28 + fieldset: PDKEY2R + - name: NSSR + description: "FLASH non-secure status register " + byte_offset: 32 + fieldset: NSSR + - name: SECSR + description: "FLASH secure status register " + byte_offset: 36 + fieldset: SECSR + - name: NSCR + description: "FLASH non-secure control register " + byte_offset: 40 + fieldset: NSCR + - name: SECCR + description: "FLASH secure control register " + byte_offset: 44 + fieldset: SECCR + - name: ECCR + description: "FLASH ECC register " + byte_offset: 48 + fieldset: ECCR + - name: OPSR + description: "FLASH operation status register " + byte_offset: 52 + fieldset: OPSR + - name: OPTR + description: "FLASH option register " + byte_offset: 64 + fieldset: OPTR + - name: NSBOOTADD0R + description: "FLASH non-secure boot address 0 register\t" + byte_offset: 68 + fieldset: NSBOOTADD0R + - name: NSBOOTADD1R + description: "FLASH non-secure boot address 1 register\t" + byte_offset: 72 + fieldset: NSBOOTADD1R + - name: SECBOOTADD0R + description: "FLASH secure boot address 0 register " + byte_offset: 76 + fieldset: SECBOOTADD0R + - name: SECWM1R1 + description: "FLASH secure watermark1 register 1 " + byte_offset: 80 + fieldset: SECWM1R1 + - name: SECWM1R2 + description: "FLASH secure watermark1 register 2 " + byte_offset: 84 + fieldset: SECWM1R2 + - name: WRP1AR + description: "FLASH WRP1 area A address register " + byte_offset: 88 + fieldset: WRP1AR + - name: WRP1BR + description: "FLASH WRP1 area B address register " + byte_offset: 92 + fieldset: WRP1BR + - name: SECWM2R1 + description: "FLASH secure watermark2 register 1 " + byte_offset: 96 + fieldset: SECWM2R1 + - name: SECWM2R2 + description: "FLASH secure watermark2 register 2 " + byte_offset: 100 + fieldset: SECWM2R2 + - name: WRP2AR + description: "FLASH WPR2 area A address register " + byte_offset: 104 + fieldset: WRP2AR + - name: WRP2BR + description: "FLASH WPR2 area B address register " + byte_offset: 108 + fieldset: WRP2BR + - name: OEM1KEYR1 + description: "FLASH OEM1 key register 1 " + byte_offset: 112 + fieldset: OEM1KEYR1 + - name: OEM1KEYR2 + description: "FLASH OEM1 key register 2 " + byte_offset: 116 + fieldset: OEM1KEYR2 + - name: OEM2KEYR1 + description: "FLASH OEM2 key register 1 " + byte_offset: 120 + fieldset: OEM2KEYR1 + - name: OEM2KEYR2 + description: "FLASH OEM2 key register 2 " + byte_offset: 124 + fieldset: OEM2KEYR2 + - name: SEC1BBR1 + description: FLASH secure block based bank 1 register 1 + byte_offset: 128 + fieldset: SEC1BBR1 + - name: SEC1BBR2 + description: FLASH secure block based bank 1 register 2 + byte_offset: 132 + fieldset: SEC1BBR2 + - name: SEC1BBR3 + description: FLASH secure block based bank 1 register 3 + byte_offset: 136 + fieldset: SEC1BBR3 + - name: SEC1BBR4 + description: FLASH secure block based bank 1 register 4 + byte_offset: 140 + fieldset: SEC1BBR4 + - name: SEC2BBR1 + description: FLASH secure block based bank 2 register 1 + byte_offset: 160 + fieldset: SEC2BBR1 + - name: SEC2BBR2 + description: FLASH secure block based bank 2 register 2 + byte_offset: 164 + fieldset: SEC2BBR2 + - name: SEC2BBR3 + description: FLASH secure block based bank 2 register 3 + byte_offset: 168 + fieldset: SEC2BBR3 + - name: SEC2BBR4 + description: FLASH secure block based bank 2 register 4 + byte_offset: 172 + fieldset: SEC2BBR4 + - name: SECHDPCR + description: "FLASH secure HDP control register " + byte_offset: 192 + fieldset: SECHDPCR + - name: PRIVCFGR + description: "FLASH privilege configuration register " + byte_offset: 196 + fieldset: PRIVCFGR + - name: PRIV1BBR1 + description: FLASH privilege block based bank 1 register 1 + byte_offset: 208 + fieldset: PRIV1BBR1 + - name: PRIV1BBR2 + description: FLASH privilege block based bank 1 register 2 + byte_offset: 212 + fieldset: PRIV1BBR2 + - name: PRIV1BBR3 + description: FLASH privilege block based bank 1 register 3 + byte_offset: 216 + fieldset: PRIV1BBR3 + - name: PRIV1BBR4 + description: FLASH privilege block based bank 1 register 4 + byte_offset: 220 + fieldset: PRIV1BBR4 + - name: PRIV2BBR1 + description: FLASH privilege block based bank 2 register 1 + byte_offset: 240 + fieldset: PRIV2BBR1 + - name: PRIV2BBR2 + description: FLASH privilege block based bank 2 register 2 + byte_offset: 244 + fieldset: PRIV2BBR2 + - name: PRIV2BBR3 + description: FLASH privilege block based bank 2 register 3 + byte_offset: 248 + fieldset: PRIV2BBR3 + - name: PRIV2BBR4 + description: FLASH privilege block based bank 2 register 4 + byte_offset: 252 + fieldset: PRIV2BBR4 +fieldset/ACR: + description: "FLASH access control register " + fields: + - name: LATENCY + description: "Latency\r These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time.\r ..." + bit_offset: 0 + bit_size: 4 + - name: PRFTEN + description: "Prefetch enable\r This bit enables the prefetch buffer in the embedded Flash memory." + bit_offset: 8 + bit_size: 1 + - name: LPM + description: "Low-power read mode\r This bit puts the Flash memory in low-power read mode." + bit_offset: 11 + bit_size: 1 + enum: LPM + - name: PDREQ1 + description: "Bank 1 power-down mode request\r This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked." + bit_offset: 12 + bit_size: 1 + enum: PDREQ + - name: PDREQ2 + description: "Bank 2 power-down mode request\r This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked." + bit_offset: 13 + bit_size: 1 + enum: PDREQ + - name: SLEEP_PD + description: "Flash memory power-down mode during Sleep mode\r This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode.\r The Flash must not be put in power-down while a program or an erase operation is on-going." + bit_offset: 14 + bit_size: 1 + enum: SLEEP_PD +fieldset/ECCR: + description: "FLASH ECC register " + fields: + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 20 + - name: BK_ECC + description: ECC fail bank + bit_offset: 21 + bit_size: 1 + enum: BK_ECC + - name: SYSF_ECC + description: "System Flash memory ECC fail\r This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory." + bit_offset: 22 + bit_size: 1 + - name: ECCIE + description: "ECC correction interrupt enable\r This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set." + bit_offset: 24 + bit_size: 1 + enum: ECCIE + - name: ECCC + description: "ECC correction\r This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1." + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: "ECC detection\r This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1." + bit_offset: 31 + bit_size: 1 +fieldset/NSBOOTADD0R: + description: "FLASH non-secure boot address 0 register\t" + fields: + - name: NSBOOTADD0 + description: "Non-secure boot base address 0\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/NSBOOTADD1R: + description: "FLASH non-secure boot address 1 register\t" + fields: + - name: NSBOOTADD1 + description: "Non-secure boot address 1\r The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000)\r NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)\r NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/NSCR: + description: "FLASH non-secure control register " + fields: + - name: PG + description: Non-secure programming + bit_offset: 0 + bit_size: 1 + enum: NSCR_PG + - name: PER + description: Non-secure page erase + bit_offset: 1 + bit_size: 1 + enum: NSCR_PER + - name: MER1 + description: "Non-secure bank 1 mass erase\r This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Non-secure page number selection\r These bits select the page to erase.\r ..." + bit_offset: 3 + bit_size: 7 + - name: BKER + description: Non-secure bank selection for page erase + bit_offset: 11 + bit_size: 1 + enum: NSCR_BKER + - name: BWR + description: "Non-secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: MER2 + description: "Non-secure bank 2 mass erase\r This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set." + bit_offset: 15 + bit_size: 1 + - name: STRT + description: "Non-secure start\r This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR." + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: "Options modification start\r This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR." + bit_offset: 17 + bit_size: 1 + - name: EOPIE + description: "Non-secure end of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1." + bit_offset: 24 + bit_size: 1 + enum: NSCR_EOPIE + - name: ERRIE + description: "Non-secure error interrupt enable\r This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1." + bit_offset: 25 + bit_size: 1 + enum: NSCR_ERRIE + - name: OBL_LAUNCH + description: "Force the option byte loading\r When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set." + bit_offset: 27 + bit_size: 1 + enum: OBL_LAUNCH + - name: OPTLOCK + description: "Option lock\r This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit.\r In case of an unsuccessful unlock operation, this bit remains set until the next reset." + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: "Non-secure lock\r This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 +fieldset/NSKEYR: + description: "FLASH non-secure key register " + fields: + - name: NSKEY + description: Flash memory non-secure key + bit_offset: 0 + bit_size: 32 +fieldset/NSSR: + description: "FLASH non-secure status register " + fields: + - name: EOP + description: Non-secure end of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Non-secure operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Non-secure programming error\r This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Non-secure write protection error\r This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Non-secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Non-secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Non-secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: OPTWERR + description: "Option write error\r This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 13 + bit_size: 1 + - name: BSY + description: "Non-secure busy\r This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Non-secure wait data to write\r This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory." + bit_offset: 17 + bit_size: 1 + - name: OEM1LOCK + description: "OEM1 lock\r This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active." + bit_offset: 18 + bit_size: 1 + - name: OEM2LOCK + description: "OEM2 lock\r This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active." + bit_offset: 19 + bit_size: 1 + - name: PD1 + description: "Bank 1 in power-down mode\r This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken." + bit_offset: 20 + bit_size: 1 + - name: PD2 + description: "Bank 2 in power-down mode\r This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken." + bit_offset: 21 + bit_size: 1 +fieldset/OEM1KEYR1: + description: "FLASH OEM1 key register 1 " + fields: + - name: OEM1KEY + description: OEM1 least significant bytes key + bit_offset: 0 + bit_size: 32 +fieldset/OEM1KEYR2: + description: "FLASH OEM1 key register 2 " + fields: + - name: OEM1KEY + description: OEM1 most significant bytes key + bit_offset: 0 + bit_size: 32 +fieldset/OEM2KEYR1: + description: "FLASH OEM2 key register 1 " + fields: + - name: OEM2KEY + description: OEM2 least significant bytes key + bit_offset: 0 + bit_size: 32 +fieldset/OEM2KEYR2: + description: "FLASH OEM2 key register 2 " + fields: + - name: OEM2KEY + description: OEM2 most significant bytes key + bit_offset: 0 + bit_size: 32 +fieldset/OPSR: + description: "FLASH operation status register " + fields: + - name: ADDR_OP + description: "Interrupted operation address\r This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0." + bit_offset: 0 + bit_size: 20 + - name: BK_OP + description: "Interrupted operation bank\r This bit indicates which Flash memory bank was accessed when reset occurred" + bit_offset: 21 + bit_size: 1 + enum: BK_OP + - name: SYSF_OP + description: "Operation in system Flash memory interrupted\r This bit indicates that the reset occurred during an operation in the system Flash memory." + bit_offset: 22 + bit_size: 1 + - name: CODE_OP + description: "Flash memory operation code\r This field indicates which Flash memory operation has been interrupted by a system reset:" + bit_offset: 29 + bit_size: 3 + enum: CODE_OP +fieldset/OPTKEYR: + description: "FLASH option key register " + fields: + - name: OPTKEY + description: Option byte key + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: "FLASH option register " + fields: + - name: RDP + description: "Readout protection level\r Others: Level 1 (memories readout protection active)\r Note: Refer to for more details." + bit_offset: 0 + bit_size: 8 + enum: RDP + - name: BOR_LEV + description: "BOR reset level\r These bits contain the VDD supply level threshold that activates/releases the reset." + bit_offset: 8 + bit_size: 3 + enum: BOR_LEV + - name: nRST_STOP + description: Reset generation in Stop mode + bit_offset: 12 + bit_size: 1 + enum: nRST_STOP + - name: nRST_STDBY + description: Reset generation in Standby mode + bit_offset: 13 + bit_size: 1 + enum: nRST_STDBY + - name: nRST_SHDW + description: Reset generation in Shutdown mode + bit_offset: 14 + bit_size: 1 + enum: nRST_SHDW + - name: SRAM1345_RST + description: "SRAM1, SRAM3 and SRAM4 erase upon system reset" + bit_offset: 15 + bit_size: 1 + - name: IWDG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + enum: IWDG_SW + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + enum: IWDG_STOP + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + enum: IWDG_STDBY + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + enum: WWDG_SW + - name: SWAP_BANK + description: Swap banks + bit_offset: 20 + bit_size: 1 + enum: SWAP_BANK + - name: DUALBANK + description: Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices + bit_offset: 21 + bit_size: 1 + enum: DUALBANK + - name: BKPRAM_ECC + description: Backup RAM ECC detection and correction enable + bit_offset: 22 + bit_size: 1 + enum: BKPRAM_ECC + - name: SRAM3_ECC + description: SRAM3 ECC detection and correction enable + bit_offset: 23 + bit_size: 1 + enum: SRAM_ECC + - name: SRAM2_ECC + description: SRAM2 ECC detection and correction enable + bit_offset: 24 + bit_size: 1 + enum: SRAM_ECC + - name: SRAM2_RST + description: SRAM2 erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software BOOT0 + bit_offset: 26 + bit_size: 1 + enum: nSWBOOT + - name: nBOOT0 + description: nBOOT0 option bit + bit_offset: 27 + bit_size: 1 + enum: nBOOT + - name: PA15_PUPEN + description: PA15 pull-up enable + bit_offset: 28 + bit_size: 1 + - name: IO_VDD_HSLV + description: "High-speed IO at low VDD voltage configuration bit\r This bit can be set only with VDD below 2.5V" + bit_offset: 29 + bit_size: 1 + enum: IO_VDD_HSLV + - name: IO_VDDIO2_HSLV + description: "High-speed IO at low VDDIO2 voltage configuration bit\r This bit can be set only with VDDIO2 below 2.5 V." + bit_offset: 30 + bit_size: 1 + enum: IO_VDDIO_HSLV + - name: TZEN + description: Global TrustZone security enable + bit_offset: 31 + bit_size: 1 +fieldset/PDKEY1R: + description: "FLASH bank 1 power-down key register " + fields: + - name: PDKEY1 + description: Bank 1 power-down key + bit_offset: 0 + bit_size: 32 +fieldset/PDKEY2R: + description: "FLASH bank 2 power-down key register " + fields: + - name: PDKEY2 + description: Bank 2 power-down key + bit_offset: 0 + bit_size: 32 +fieldset/PRIV1BBR1: + description: FLASH privilege block based bank 1 register 1 + fields: + - name: PRIV1BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV1BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV1BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV1BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV1BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV1BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV1BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV1BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV1BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV1BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV1BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV1BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV1BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV1BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV1BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV1BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV1BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV1BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV1BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV1BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV1BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV1BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV1BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV1BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV1BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV1BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV1BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV1BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV1BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV1BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV1BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV1BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV1BBR2: + description: FLASH privilege block based bank 1 register 2 + fields: + - name: PRIV1BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV1BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV1BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV1BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV1BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV1BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV1BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV1BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV1BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV1BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV1BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV1BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV1BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV1BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV1BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV1BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV1BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV1BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV1BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV1BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV1BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV1BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV1BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV1BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV1BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV1BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV1BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV1BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV1BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV1BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV1BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV1BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV1BBR3: + description: FLASH privilege block based bank 1 register 3 + fields: + - name: PRIV1BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV1BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV1BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV1BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV1BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV1BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV1BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV1BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV1BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV1BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV1BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV1BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV1BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV1BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV1BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV1BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV1BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV1BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV1BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV1BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV1BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV1BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV1BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV1BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV1BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV1BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV1BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV1BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV1BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV1BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV1BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV1BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV1BBR4: + description: FLASH privilege block based bank 1 register 4 + fields: + - name: PRIV1BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV1BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV1BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV1BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV1BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV1BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV1BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV1BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV1BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV1BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV1BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV1BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV1BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV1BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV1BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV1BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV1BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV1BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV1BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV1BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV1BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV1BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV1BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV1BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV1BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV1BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV1BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV1BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV1BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV1BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV1BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV1BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV2BBR1: + description: FLASH privilege block based bank 2 register 1 + fields: + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV2BBR2: + description: FLASH privilege block based bank 2 register 2 + fields: + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV2BBR3: + description: FLASH privilege block based bank 2 register 3 + fields: + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIV2BBR4: + description: FLASH privilege block based bank 2 register 4 + fields: + - name: PRIV2BB0 + description: page privileged/unprivileged attribution + bit_offset: 0 + bit_size: 1 + - name: PRIV2BB1 + description: page privileged/unprivileged attribution + bit_offset: 1 + bit_size: 1 + - name: PRIV2BB2 + description: page privileged/unprivileged attribution + bit_offset: 2 + bit_size: 1 + - name: PRIV2BB3 + description: page privileged/unprivileged attribution + bit_offset: 3 + bit_size: 1 + - name: PRIV2BB4 + description: page privileged/unprivileged attribution + bit_offset: 4 + bit_size: 1 + - name: PRIV2BB5 + description: page privileged/unprivileged attribution + bit_offset: 5 + bit_size: 1 + - name: PRIV2BB6 + description: page privileged/unprivileged attribution + bit_offset: 6 + bit_size: 1 + - name: PRIV2BB7 + description: page privileged/unprivileged attribution + bit_offset: 7 + bit_size: 1 + - name: PRIV2BB8 + description: page privileged/unprivileged attribution + bit_offset: 8 + bit_size: 1 + - name: PRIV2BB9 + description: page privileged/unprivileged attribution + bit_offset: 9 + bit_size: 1 + - name: PRIV2BB10 + description: page privileged/unprivileged attribution + bit_offset: 10 + bit_size: 1 + - name: PRIV2BB11 + description: page privileged/unprivileged attribution + bit_offset: 11 + bit_size: 1 + - name: PRIV2BB12 + description: page privileged/unprivileged attribution + bit_offset: 12 + bit_size: 1 + - name: PRIV2BB13 + description: page privileged/unprivileged attribution + bit_offset: 13 + bit_size: 1 + - name: PRIV2BB14 + description: page privileged/unprivileged attribution + bit_offset: 14 + bit_size: 1 + - name: PRIV2BB15 + description: page privileged/unprivileged attribution + bit_offset: 15 + bit_size: 1 + - name: PRIV2BB16 + description: page privileged/unprivileged attribution + bit_offset: 16 + bit_size: 1 + - name: PRIV2BB17 + description: page privileged/unprivileged attribution + bit_offset: 17 + bit_size: 1 + - name: PRIV2BB18 + description: page privileged/unprivileged attribution + bit_offset: 18 + bit_size: 1 + - name: PRIV2BB19 + description: page privileged/unprivileged attribution + bit_offset: 19 + bit_size: 1 + - name: PRIV2BB20 + description: page privileged/unprivileged attribution + bit_offset: 20 + bit_size: 1 + - name: PRIV2BB21 + description: page privileged/unprivileged attribution + bit_offset: 21 + bit_size: 1 + - name: PRIV2BB22 + description: page privileged/unprivileged attribution + bit_offset: 22 + bit_size: 1 + - name: PRIV2BB23 + description: page privileged/unprivileged attribution + bit_offset: 23 + bit_size: 1 + - name: PRIV2BB24 + description: page privileged/unprivileged attribution + bit_offset: 24 + bit_size: 1 + - name: PRIV2BB25 + description: page privileged/unprivileged attribution + bit_offset: 25 + bit_size: 1 + - name: PRIV2BB26 + description: page privileged/unprivileged attribution + bit_offset: 26 + bit_size: 1 + - name: PRIV2BB27 + description: page privileged/unprivileged attribution + bit_offset: 27 + bit_size: 1 + - name: PRIV2BB28 + description: page privileged/unprivileged attribution + bit_offset: 28 + bit_size: 1 + - name: PRIV2BB29 + description: page privileged/unprivileged attribution + bit_offset: 29 + bit_size: 1 + - name: PRIV2BB30 + description: page privileged/unprivileged attribution + bit_offset: 30 + bit_size: 1 + - name: PRIV2BB31 + description: page privileged/unprivileged attribution + bit_offset: 31 + bit_size: 1 +fieldset/PRIVCFGR: + description: "FLASH privilege configuration register " + fields: + - name: SPRIV + description: "Privileged protection for secure registers\r This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored." + bit_offset: 0 + bit_size: 1 + enum: SPRIV + - name: NSPRIV + description: "Privileged protection for non-secure registers\r This bit can be read by both privileged or unprivileged, secure and non-secure access.\r The NSPRIV bit can be written by a secure or non-secure privileged access. A secure or non-secure unprivileged write access on NSPRIV bit is ignored." + bit_offset: 1 + bit_size: 1 + enum: NSPRIV +fieldset/SEC1BBR1: + description: FLASH secure block based bank 1 register 1 + fields: + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC1BBR2: + description: FLASH secure block based bank 1 register 2 + fields: + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC1BBR3: + description: FLASH secure block based bank 1 register 3 + fields: + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC1BBR4: + description: FLASH secure block based bank 1 register 4 + fields: + - name: SEC1BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC1BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC1BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC1BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC1BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC1BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC1BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC1BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC1BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC1BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC1BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC1BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC1BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC1BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC1BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC1BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC1BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC1BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC1BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC1BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC1BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC1BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC1BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC1BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC1BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC1BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC1BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC1BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC1BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC1BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC1BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC1BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC2BBR1: + description: FLASH secure block based bank 2 register 1 + fields: + - name: SEC2BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC2BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC2BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC2BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC2BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC2BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC2BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC2BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC2BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC2BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC2BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC2BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC2BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC2BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC2BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC2BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC2BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC2BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC2BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC2BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC2BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC2BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC2BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC2BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC2BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC2BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC2BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC2BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC2BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC2BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC2BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC2BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC2BBR2: + description: FLASH secure block based bank 2 register 2 + fields: + - name: SEC2BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC2BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC2BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC2BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC2BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC2BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC2BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC2BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC2BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC2BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC2BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC2BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC2BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC2BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC2BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC2BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC2BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC2BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC2BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC2BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC2BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC2BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC2BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC2BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC2BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC2BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC2BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC2BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC2BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC2BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC2BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC2BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC2BBR3: + description: FLASH secure block based bank 2 register 3 + fields: + - name: SEC2BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC2BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC2BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC2BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC2BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC2BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC2BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC2BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC2BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC2BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC2BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC2BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC2BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC2BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC2BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC2BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC2BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC2BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC2BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC2BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC2BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC2BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC2BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC2BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC2BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC2BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC2BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC2BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC2BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC2BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC2BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC2BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SEC2BBR4: + description: FLASH secure block based bank 2 register 4 + fields: + - name: SEC2BB0 + description: page secure/non-secure attribution + bit_offset: 0 + bit_size: 1 + - name: SEC2BB1 + description: page secure/non-secure attribution + bit_offset: 1 + bit_size: 1 + - name: SEC2BB2 + description: page secure/non-secure attribution + bit_offset: 2 + bit_size: 1 + - name: SEC2BB3 + description: page secure/non-secure attribution + bit_offset: 3 + bit_size: 1 + - name: SEC2BB4 + description: page secure/non-secure attribution + bit_offset: 4 + bit_size: 1 + - name: SEC2BB5 + description: page secure/non-secure attribution + bit_offset: 5 + bit_size: 1 + - name: SEC2BB6 + description: page secure/non-secure attribution + bit_offset: 6 + bit_size: 1 + - name: SEC2BB7 + description: page secure/non-secure attribution + bit_offset: 7 + bit_size: 1 + - name: SEC2BB8 + description: page secure/non-secure attribution + bit_offset: 8 + bit_size: 1 + - name: SEC2BB9 + description: page secure/non-secure attribution + bit_offset: 9 + bit_size: 1 + - name: SEC2BB10 + description: page secure/non-secure attribution + bit_offset: 10 + bit_size: 1 + - name: SEC2BB11 + description: page secure/non-secure attribution + bit_offset: 11 + bit_size: 1 + - name: SEC2BB12 + description: page secure/non-secure attribution + bit_offset: 12 + bit_size: 1 + - name: SEC2BB13 + description: page secure/non-secure attribution + bit_offset: 13 + bit_size: 1 + - name: SEC2BB14 + description: page secure/non-secure attribution + bit_offset: 14 + bit_size: 1 + - name: SEC2BB15 + description: page secure/non-secure attribution + bit_offset: 15 + bit_size: 1 + - name: SEC2BB16 + description: page secure/non-secure attribution + bit_offset: 16 + bit_size: 1 + - name: SEC2BB17 + description: page secure/non-secure attribution + bit_offset: 17 + bit_size: 1 + - name: SEC2BB18 + description: page secure/non-secure attribution + bit_offset: 18 + bit_size: 1 + - name: SEC2BB19 + description: page secure/non-secure attribution + bit_offset: 19 + bit_size: 1 + - name: SEC2BB20 + description: page secure/non-secure attribution + bit_offset: 20 + bit_size: 1 + - name: SEC2BB21 + description: page secure/non-secure attribution + bit_offset: 21 + bit_size: 1 + - name: SEC2BB22 + description: page secure/non-secure attribution + bit_offset: 22 + bit_size: 1 + - name: SEC2BB23 + description: page secure/non-secure attribution + bit_offset: 23 + bit_size: 1 + - name: SEC2BB24 + description: page secure/non-secure attribution + bit_offset: 24 + bit_size: 1 + - name: SEC2BB25 + description: page secure/non-secure attribution + bit_offset: 25 + bit_size: 1 + - name: SEC2BB26 + description: page secure/non-secure attribution + bit_offset: 26 + bit_size: 1 + - name: SEC2BB27 + description: page secure/non-secure attribution + bit_offset: 27 + bit_size: 1 + - name: SEC2BB28 + description: page secure/non-secure attribution + bit_offset: 28 + bit_size: 1 + - name: SEC2BB29 + description: page secure/non-secure attribution + bit_offset: 29 + bit_size: 1 + - name: SEC2BB30 + description: page secure/non-secure attribution + bit_offset: 30 + bit_size: 1 + - name: SEC2BB31 + description: page secure/non-secure attribution + bit_offset: 31 + bit_size: 1 +fieldset/SECBOOTADD0R: + description: "FLASH secure boot address 0 register " + fields: + - name: BOOT_LOCK + description: "Boot lock\r When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0." + bit_offset: 0 + bit_size: 1 + - name: SECBOOTADD0 + description: "Secure boot base address 0\r The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state.\r Examples:\r SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000)\r SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000)\r SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)" + bit_offset: 7 + bit_size: 25 +fieldset/SECCR: + description: "FLASH secure control register " + fields: + - name: PG + description: Secure programming + bit_offset: 0 + bit_size: 1 + enum: SECCR_PG + - name: PER + description: Secure page erase + bit_offset: 1 + bit_size: 1 + enum: SECCR_PER + - name: MER1 + description: "Secure bank 1 mass erase\r This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set." + bit_offset: 2 + bit_size: 1 + - name: PNB + description: "Secure page number selection\r These bits select the page to erase:\r ..." + bit_offset: 3 + bit_size: 7 + - name: BKER + description: Secure bank selection for page erase + bit_offset: 11 + bit_size: 1 + enum: SECCR_BKER + - name: BWR + description: "Secure burst write programming mode\r When set, this bit selects the burst write programming mode." + bit_offset: 14 + bit_size: 1 + - name: MER2 + description: "Secure bank 2 mass erase\r This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set." + bit_offset: 15 + bit_size: 1 + - name: STRT + description: "Secure start\r This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden).\r This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR." + bit_offset: 16 + bit_size: 1 + - name: EOPIE + description: "Secure End of operation interrupt enable\r This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1." + bit_offset: 24 + bit_size: 1 + enum: SECCR_EOPIE + - name: ERRIE + description: Secure error interrupt enable + bit_offset: 25 + bit_size: 1 + enum: SECCR_ERRIE + - name: RDERRIE + description: Secure PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: INV + description: "Flash memory security state invert\r This bit inverts the Flash memory security state." + bit_offset: 29 + bit_size: 1 + - name: LOCK + description: "Secure lock\r This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register.\r In case of an unsuccessful unlock operation, this bit remains set until the next system reset." + bit_offset: 31 + bit_size: 1 +fieldset/SECHDPCR: + description: "FLASH secure HDP control register " + fields: + - name: HDP1_ACCDIS + description: "HDP1 area access disable\r When set, this bit is only cleared by a system reset." + bit_offset: 0 + bit_size: 1 + enum: HDP_ACCDIS + - name: HDP2_ACCDIS + description: "HDP2 area access disable\r When set, this bit is only cleared by a system reset." + bit_offset: 1 + bit_size: 1 + enum: HDP_ACCDIS +fieldset/SECKEYR: + description: "FLASH secure key register " + fields: + - name: SECKEY + description: Flash memory secure key + bit_offset: 0 + bit_size: 32 +fieldset/SECSR: + description: "FLASH secure status register " + fields: + - name: EOP + description: "Secure end of operation\r This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1." + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: "Secure operation error\r This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1." + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: "Secure programming error\r This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1." + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: "Secure write protection error\r This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: "Secure programming alignment error\r This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1." + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: "Secure size error\r This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1." + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: "Secure programming sequence error\r This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1.\r Refer to for full conditions of error flag setting." + bit_offset: 7 + bit_size: 1 + - name: BSY + description: "Secure busy\r This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs." + bit_offset: 16 + bit_size: 1 + - name: WDW + description: "Secure wait data to write\r This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory." + bit_offset: 17 + bit_size: 1 +fieldset/SECWM1R1: + description: "FLASH secure watermark1 register 1 " + fields: + - name: SECWM1_PSTRT + description: "Start page of first secure area\r This field contains the first page of the secure area in bank 1." + bit_offset: 0 + bit_size: 7 + - name: SECWM1_PEND + description: "End page of first secure area\r This field contains the last page of the secure area in bank 1." + bit_offset: 16 + bit_size: 7 +fieldset/SECWM1R2: + description: "FLASH secure watermark1 register 2 " + fields: + - name: HDP1_PEND + description: "End page of first hide protection area\r This field contains the last page of the HDP area in bank 1." + bit_offset: 16 + bit_size: 7 + - name: HDP1EN + description: Hide protection first area enable + bit_offset: 31 + bit_size: 1 +fieldset/SECWM2R1: + description: "FLASH secure watermark2 register 1 " + fields: + - name: SECWM2_PSTRT + description: "Start page of second secure area\r This field contains the first page of the secure area in bank 2." + bit_offset: 0 + bit_size: 7 + - name: SECWM2_PEND + description: "End page of second secure area\r This field contains the last page of the secure area in bank 2." + bit_offset: 16 + bit_size: 7 +fieldset/SECWM2R2: + description: "FLASH secure watermark2 register 2 " + fields: + - name: HDP2_PEND + description: "End page of hide protection second area\r HDP2_PEND contains the last page of the HDP area in bank 2." + bit_offset: 16 + bit_size: 7 + - name: HDP2EN + description: Hide protection second area enable + bit_offset: 31 + bit_size: 1 +fieldset/WRP1AR: + description: "FLASH WRP1 area A address register " + fields: + - name: WRP1A_PSTRT + description: "bank 1 WPR first area A start page\r This field contains the first page of the first WPR area for bank 1." + bit_offset: 0 + bit_size: 7 + - name: WRP1A_PEND + description: "Bank 1 WPR first area A end page\r This field contains the last page of the first WPR area in bank 1." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 1 WPR first area A unlock + bit_offset: 31 + bit_size: 1 + enum: WRPAR_UNLOCK +fieldset/WRP1BR: + description: "FLASH WRP1 area B address register " + fields: + - name: WRP1B_PSTRT + description: "Bank 1 WRP second area B start page\r This field contains the first page of the second WRP area for bank 1." + bit_offset: 0 + bit_size: 7 + - name: WRP1B_PEND + description: "Bank 1 WRP second area B end page\r This field contains the last page of the second WRP area in bank 1." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 1 WPR second area B unlock + bit_offset: 31 + bit_size: 1 + enum: WRPBR_UNLOCK +fieldset/WRP2AR: + description: "FLASH WPR2 area A address register " + fields: + - name: WRP2A_PSTRT + description: "Bank 2 WPR first area A start page\r This field contains the first page of the first WRP area for bank 2." + bit_offset: 0 + bit_size: 7 + - name: WRP2A_PEND + description: "Bank 2 WPR first area A end page\r This field contains the last page of the first WRP area in bank 2." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 2 WPR first area A unlock + bit_offset: 31 + bit_size: 1 + enum: WRPAR_UNLOCK +fieldset/WRP2BR: + description: "FLASH WPR2 area B address register " + fields: + - name: WRP2B_PSTRT + description: "Bank 2 WPR second area B start page\r This field contains the first page of the second WRP area for bank 2." + bit_offset: 0 + bit_size: 7 + - name: WRP2B_PEND + description: "Bank 2 WPR second area B end page\r This field contains the last page of the second WRP area in bank 2." + bit_offset: 16 + bit_size: 7 + - name: UNLOCK + description: Bank 2 WPR second area B unlock + bit_offset: 31 + bit_size: 1 + enum: WRPBR_UNLOCK +enum/BKPRAM_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: Backup RAM ECC check enabled + value: 0 + - name: B_0x1 + description: Backup RAM ECC check disabled + value: 1 +enum/BK_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank 1 + value: 0 + - name: B_0x1 + description: Bank 2 + value: 1 +enum/BK_OP: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank 1 + value: 0 + - name: B_0x1 + description: Bank 2 + value: 1 +enum/BOR_LEV: + bit_size: 3 + variants: + - name: B_0x0 + description: "BOR level 0 (reset level threshold around 1.7 V) " + value: 0 + - name: B_0x1 + description: "BOR level 1 (reset level threshold around 2.0 V) " + value: 1 + - name: B_0x2 + description: "BOR level 2 (reset level threshold around 2.2 V) " + value: 2 + - name: B_0x3 + description: "BOR level 3 (reset level threshold around 2.5 V) " + value: 3 + - name: B_0x4 + description: "BOR level 4 (reset level threshold around 2.8 V) " + value: 4 +enum/CODE_OP: + bit_size: 3 + variants: + - name: B_0x0 + description: No Flash operation interrupted by previous reset + value: 0 + - name: B_0x1 + description: Single write operation interrupted + value: 1 + - name: B_0x2 + description: Burst write operation interrupted + value: 2 + - name: B_0x3 + description: Page erase operation interrupted + value: 3 + - name: B_0x4 + description: Bank erase operation interrupted + value: 4 + - name: B_0x5 + description: Mass erase operation interrupted + value: 5 + - name: B_0x6 + description: Option change operation interrupted + value: 6 +enum/DUALBANK: + bit_size: 1 + variants: + - name: B_0x0 + description: Single bank Flash with contiguous address in bank 1 + value: 0 + - name: B_0x1 + description: Dual-bank Flash with contiguous addresses + value: 1 +enum/ECCIE: + bit_size: 1 + variants: + - name: B_0x0 + description: ECCC interrupt disabled + value: 0 + - name: B_0x1 + description: ECCC interrupt enabled. + value: 1 +enum/HDP_ACCDIS: + bit_size: 1 + variants: + - name: B_0x0 + description: Access to HDP2 area granted + value: 0 + - name: B_0x1 + description: Access to HDP2 area denied (SECWM2Ry option bytes modification bocked -refer to ) + value: 1 +enum/IO_VDDIO_HSLV: + bit_size: 1 + variants: + - name: B_0x0 + description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) " + value: 0 + - name: B_0x1 + description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) " + value: 1 +enum/IO_VDD_HSLV: + bit_size: 1 + variants: + - name: B_0x0 + description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) " + value: 0 + - name: B_0x1 + description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) " + value: 1 +enum/IWDG_STDBY: + bit_size: 1 + variants: + - name: B_0x0 + description: Independent watchdog counter frozen in Standby mode + value: 0 + - name: B_0x1 + description: Independent watchdog counter running in Standby mode + value: 1 +enum/IWDG_STOP: + bit_size: 1 + variants: + - name: B_0x0 + description: Independent watchdog counter frozen in Stop mode + value: 0 + - name: B_0x1 + description: Independent watchdog counter running in Stop mode + value: 1 +enum/IWDG_SW: + bit_size: 1 + variants: + - name: B_0x0 + description: Hardware independent watchdog selected + value: 0 + - name: B_0x1 + description: Software independent watchdog selected + value: 1 +enum/LPM: + bit_size: 1 + variants: + - name: B_0x0 + description: Flash not in low-power read mode + value: 0 + - name: B_0x1 + description: Flash in low-power read mode + value: 1 +enum/NSCR_BKER: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank 1 selected for non-secure page erase + value: 0 + - name: B_0x1 + description: Bank 2 selected for non-secure page erase + value: 1 +enum/NSCR_EOPIE: + bit_size: 1 + variants: + - name: B_0x0 + description: Non-secure EOP Interrupt disabled + value: 0 + - name: B_0x1 + description: Non-secure EOP Interrupt enabled + value: 1 +enum/NSCR_ERRIE: + bit_size: 1 + variants: + - name: B_0x0 + description: Non-secure OPERR error interrupt disabled + value: 0 + - name: B_0x1 + description: Non-secure OPERR error interrupt enabled + value: 1 +enum/NSCR_PER: + bit_size: 1 + variants: + - name: B_0x0 + description: Non-secure page erase disabled + value: 0 + - name: B_0x1 + description: Non-secure page erase enabled + value: 1 +enum/NSCR_PG: + bit_size: 1 + variants: + - name: B_0x0 + description: Non-secure Flash programming disabled + value: 0 + - name: B_0x1 + description: Non-secure Flash programming enabled + value: 1 +enum/NSPRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: Non-secure Flash registers can be read and written by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Non-secure Flash registers can be read and written by privileged access only. + value: 1 +enum/OBL_LAUNCH: + bit_size: 1 + variants: + - name: B_0x0 + description: Option byte loading complete + value: 0 + - name: B_0x1 + description: Option byte loading requested + value: 1 +enum/PDREQ: + bit_size: 1 + variants: + - name: B_0x0 + description: No request for bank 2 to enter power-down mode + value: 0 + - name: B_0x1 + description: Bank 2 requested to enter power-down mode + value: 1 +enum/RDP: + bit_size: 8 + variants: + - name: B_0x55 + description: "Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)" + value: 85 + - name: B_0xAA + description: Level 0 (readout protection not active) + value: 170 + - name: B_0xCC + description: Level 2 (chip readout protection active) + value: 204 +enum/SECCR_BKER: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank 1 selected for secure page erase + value: 0 + - name: B_0x1 + description: Bank 2 selected for secure page erase + value: 1 +enum/SECCR_EOPIE: + bit_size: 1 + variants: + - name: B_0x0 + description: Secure EOP Interrupt disabled + value: 0 + - name: B_0x1 + description: Secure EOP Interrupt enabled + value: 1 +enum/SECCR_ERRIE: + bit_size: 1 + variants: + - name: B_0x0 + description: Secure OPERR error interrupt disabled + value: 0 + - name: B_0x1 + description: Secure OPERR error interrupt enabled + value: 1 +enum/SECCR_PER: + bit_size: 1 + variants: + - name: B_0x0 + description: Secure page erase disabled + value: 0 + - name: B_0x1 + description: Secure page erase enabled + value: 1 +enum/SECCR_PG: + bit_size: 1 + variants: + - name: B_0x0 + description: Secure Flash programming disabled + value: 0 + - name: B_0x1 + description: Secure Flash programming enabled + value: 1 +enum/SLEEP_PD: + bit_size: 1 + variants: + - name: B_0x0 + description: Flash in Idle mode during Sleep mode + value: 0 + - name: B_0x1 + description: Flash in power-down mode during Sleep mode + value: 1 +enum/SPRIV: + bit_size: 1 + variants: + - name: B_0x0 + description: Secure Flash registers can be read and written by privileged or unprivileged access. + value: 0 + - name: B_0x1 + description: Secure Flash registers can be read and written by privileged access only. + value: 1 +enum/SRAM_ECC: + bit_size: 1 + variants: + - name: B_0x0 + description: SRAM3 ECC check enabled + value: 0 + - name: B_0x1 + description: SRAM3 ECC check disabled + value: 1 +enum/SWAP_BANK: + bit_size: 1 + variants: + - name: B_0x0 + description: Bank 1 and bank 2 addresses not swapped + value: 0 + - name: B_0x1 + description: Bank 1 and bank 2 addresses swapped + value: 1 +enum/WRPAR_UNLOCK: + bit_size: 1 + variants: + - name: B_0x0 + description: WRP2A start and end pages locked + value: 0 + - name: B_0x1 + description: WRP2A start and end pages unlocked + value: 1 +enum/WRPBR_UNLOCK: + bit_size: 1 + variants: + - name: B_0x0 + description: WRP2B start and end pages locked + value: 0 + - name: B_0x1 + description: WRP2B start and end pages unlocked + value: 1 +enum/WWDG_SW: + bit_size: 1 + variants: + - name: B_0x0 + description: Hardware window watchdog selected + value: 0 + - name: B_0x1 + description: Software window watchdog selected + value: 1 +enum/nBOOT: + bit_size: 1 + variants: + - name: B_0x0 + description: nBOOT0 = 0 + value: 0 + - name: B_0x1 + description: nBOOT0 = 1 + value: 1 +enum/nRST_SHDW: + bit_size: 1 + variants: + - name: B_0x0 + description: Reset generated when entering the Shutdown mode + value: 0 + - name: B_0x1 + description: No reset generated when entering the Shutdown mode + value: 1 +enum/nRST_STDBY: + bit_size: 1 + variants: + - name: B_0x0 + description: Reset generated when entering the Standby mode + value: 0 + - name: B_0x1 + description: No reset generate when entering the Standby mode + value: 1 +enum/nRST_STOP: + bit_size: 1 + variants: + - name: B_0x0 + description: Reset generated when entering the Stop mode + value: 0 + - name: B_0x1 + description: No reset generated when entering the Stop mode + value: 1 +enum/nSWBOOT: + bit_size: 1 + variants: + - name: B_0x0 + description: BOOT0 taken from the option bit nBOOT0 + value: 0 + - name: B_0x1 + description: BOOT0 taken from PH3/BOOT0 pin + value: 1 diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index fa21f78..9ead6d7 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -1783,7 +1783,6 @@ fieldset/CR: description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles." bit_offset: 2 bit_size: 1 - enum: MSISRDY - name: MSIPLLEN description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)." bit_offset: 3 @@ -1819,7 +1818,6 @@ fieldset/CR: description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles." bit_offset: 10 bit_size: 1 - enum: HSIRDY - name: HSI48ON description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes." bit_offset: 12 @@ -1828,7 +1826,6 @@ fieldset/CR: description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON." bit_offset: 13 bit_size: 1 - enum: HSIRDY - name: SHSION description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes." bit_offset: 14 @@ -1846,7 +1843,6 @@ fieldset/CR: description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles." bit_offset: 17 bit_size: 1 - enum: HSERDY - name: HSEBYP description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled." bit_offset: 18 @@ -1875,7 +1871,6 @@ fieldset/CR: array: len: 3 stride: 2 - enum: PLLRDY fieldset/CRRCR: description: "RCC clock recovery RC register " fields: @@ -1969,12 +1964,12 @@ fieldset/ICSCR1: description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)." bit_offset: 24 bit_size: 4 - enum: MSIKRANGE + enum: MSIRANGE - name: MSISRANGE description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)." bit_offset: 28 bit_size: 4 - enum: MSISRANGE + enum: MSIRANGE fieldset/ICSCR2: description: "RCC internal clock sources calibration register 2 " fields: @@ -2012,62 +2007,38 @@ fieldset/PLL1CFGR: description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0." bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: PLLSRC - name: PLLRGE description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz" bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: PLLRGE - name: PLLFRACEN description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator.\r In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details)." bit_offset: 4 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLM description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 8 bit_size: 4 - array: - len: 1 - stride: 0 enum: PLLM - name: PLLMBOOST description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved" bit_offset: 12 bit_size: 4 - array: - len: 1 - stride: 0 enum: PLLMBOOST - name: PLLPEN description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 16 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLQEN description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 17 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLREN description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 18 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/PLL1DIVR: description: "RCC PLL1 dividers register " fields: @@ -2075,34 +2046,20 @@ fieldset/PLL1DIVR: description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz" bit_offset: 0 bit_size: 9 - array: - len: 1 - stride: 0 - enum: PLLN - name: PLLP description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." bit_offset: 9 bit_size: 7 - array: - len: 1 - stride: 0 enum: PLLP - name: PLLQ description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 16 bit_size: 7 - array: - len: 1 - stride: 0 enum: PLLQ - name: PLLR description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 24 bit_size: 7 - array: - len: 1 - stride: 0 - enum: PLLR fieldset/PLL1FRACR: description: "RCC PLL1 fractional divider register " fields: @@ -2110,9 +2067,6 @@ fieldset/PLL1FRACR: description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1." bit_offset: 3 bit_size: 13 - array: - len: 1 - stride: 0 fieldset/PLL2CFGR: description: "RCC PLL2 configuration register " fields: @@ -2120,54 +2074,33 @@ fieldset/PLL2CFGR: description: "PLL2 entry clock source\r Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled.\r In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0." bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: PLLSRC - name: PLLRGE description: "PLL2 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL2.\r This bit must be written before enabling the PLL2.\r 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz" bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: PLLRGE - name: PLLFRACEN description: "PLL2 fractional latch enable\r Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator.\r In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details)." bit_offset: 4 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLM description: "Prescaler for PLL2\r Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 8 bit_size: 4 - array: - len: 1 - stride: 0 enum: PLLM - name: PLLPEN description: "PLL2 DIVP divider output enable\r Set and reset by software to enable the pll2_p_ck output of the PLL2.\r To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." bit_offset: 16 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLQEN description: "PLL2 DIVQ divider output enable\r Set and reset by software to enable the pll2_q_ck output of the PLL2.\r To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0." bit_offset: 17 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLREN description: "PLL2 DIVR divider output enable\r Set and reset by software to enable the pll2_r_ck output of the PLL2.\r To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used.\r This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)." bit_offset: 18 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/PLL2DIVR: description: "RCC PLL2 dividers configuration register " fields: @@ -2175,34 +2108,20 @@ fieldset/PLL2DIVR: description: "Multiplication factor for PLL2 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with:\r PLL2N between 4 and 512\r input frequency Fref2_ck between 1MHz and 16MHz" bit_offset: 0 bit_size: 9 - array: - len: 1 - stride: 0 - enum: PLLN - name: PLLP description: "PLL2 DIVP division factor\r Set and reset by software to control the frequency of the pll2_p_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 9 bit_size: 7 - array: - len: 1 - stride: 0 enum: PLLP - name: PLLQ description: "PLL2 DIVQ division factor\r Set and reset by software to control the frequency of the pll2_q_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 16 bit_size: 7 - array: - len: 1 - stride: 0 enum: PLLQ - name: PLLR description: "PLL2 DIVR division factor\r Set and reset by software to control the frequency of the pll2_r_ck clock.\r These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).\r ..." bit_offset: 24 bit_size: 7 - array: - len: 1 - stride: 0 - enum: PLLR fieldset/PLL2FRACR: description: "RCC PLL2 fractional divider register " fields: @@ -2210,9 +2129,6 @@ fieldset/PLL2FRACR: description: "Fractional part of the multiplication factor for PLL2 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.\r VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with\r PLL2N must be between 4 and 512.\r PLL2FRACN can be between 0 and 213 - 1.\r The input frequency Fref2_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL2FRACEN to 0.\r Write the new fractional value into PLL2FRACN.\r Set the bit PLL2FRACEN to 1." bit_offset: 3 bit_size: 13 - array: - len: 1 - stride: 0 fieldset/PLL3CFGR: description: "RCC PLL3 configuration register " fields: @@ -2220,40 +2136,25 @@ fieldset/PLL3CFGR: description: "PLL3 entry clock source\r Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled.\r In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00." bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: PLLSRC - name: PLLRGE description: "PLL3 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL3.\r This bit must be written before enabling the PLL3.\r 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz" bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: PLLRGE - name: PLLFRACEN description: "PLL3 fractional latch enable\r Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator.\r In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details)." bit_offset: 4 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLM description: "Prescaler for PLL3\r Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 8 bit_size: 4 - array: - len: 1 - stride: 0 enum: PLLM - name: PLLPEN description: "PLL3 DIVP divider output enable\r Set and reset by software to enable the pll3_p_ck output of the PLL3.\r To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 16 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLQEN description: "PLL3 DIVQ divider output enable\r Set and reset by software to enable the pll3_q_ck output of the PLL3.\r To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 17 @@ -2265,9 +2166,6 @@ fieldset/PLL3CFGR: description: "PLL3 DIVR divider output enable\r Set and reset by software to enable the pll3_r_ck output of the PLL3.\r To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 18 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/PLL3DIVR: description: "RCC PLL3 dividers configuration register " fields: @@ -2275,34 +2173,20 @@ fieldset/PLL3DIVR: description: "Multiplication factor for PLL3 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with:\r PLL3N between 4 and 512\r input frequency Fref3_ck between 4 and 16MHz" bit_offset: 0 bit_size: 9 - array: - len: 1 - stride: 0 - enum: PLLN - name: PLLP description: "PLL3 DIVP division factor\r Set and reset by software to control the frequency of the pll3_p_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 9 bit_size: 7 - array: - len: 1 - stride: 0 enum: PLLP - name: PLLQ description: "PLL3 DIVQ division factor\r Set and reset by software to control the frequency of the pll3_q_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 16 bit_size: 7 - array: - len: 1 - stride: 0 enum: PLLQ - name: PLLR description: "PLL3 DIVR division factor\r Set and reset by software to control the frequency of the pll3_r_ck clock.\r These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).\r ..." bit_offset: 24 bit_size: 7 - array: - len: 1 - stride: 0 - enum: PLLR fieldset/PLL3FRACR: description: "RCC PLL3 fractional divider register " fields: @@ -2310,9 +2194,6 @@ fieldset/PLL3FRACR: description: "Fractional part of the multiplication factor for PLL3 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.\r VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with:\r PLL3N must be between 4 and 512.\r PLL3FRACN can be between 0 and 213 - 1.\r The input frequency Fref3_ck must be between 4 and 16 MHz.\r In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL3FRACEN to 0.\r Write the new fractional value into PLL3FRACN.\r Set the bit PLL3FRACEN to 1." bit_offset: 3 bit_size: 13 - array: - len: 1 - stride: 0 fieldset/PRIVCFGR: description: "RCC privilege configuration register " fields: @@ -2553,28 +2434,31 @@ enum/FDCANSEL: enum/HPRE: bit_size: 4 variants: - - name: B_0x8 + - name: NONE + description: SYSCLK not divided + value: 0 + - name: DIV2 description: SYSCLK divided by 2 value: 8 - - name: B_0x9 + - name: DIV4 description: SYSCLK divided by 4 value: 9 - - name: B_0xA + - name: DIV8 description: SYSCLK divided by 8 value: 10 - - name: B_0xB + - name: DIV16 description: SYSCLK divided by 16 value: 11 - - name: B_0xC + - name: DIV64 description: SYSCLK divided by 64 value: 12 - - name: B_0xD + - name: DIV128 description: SYSCLK divided by 128 value: 13 - - name: B_0xE + - name: DIV256 description: SYSCLK divided by 256 value: 14 - - name: B_0xF + - name: DIV512 description: SYSCLK divided by 512 value: 15 enum/HSEBYP: @@ -2595,15 +2479,6 @@ enum/HSEEXT: - name: B_0x1 description: external HSE clock digital mode (through I/O Schmitt trigger) value: 1 -enum/HSERDY: - bit_size: 1 - variants: - - name: B_0x0 - description: HSE oscillator not ready - value: 0 - - name: B_0x1 - description: "HSE oscillator ready " - value: 1 enum/HSERDYF: bit_size: 1 variants: @@ -2631,15 +2506,6 @@ enum/HSESEC: - name: B_0x1 description: secure value: 1 -enum/HSIRDY: - bit_size: 1 - variants: - - name: B_0x0 - description: HSI16 oscillator not ready - value: 0 - - name: B_0x1 - description: HSI16 oscillator ready - value: 1 enum/HSIRDYF: bit_size: 1 variants: @@ -2967,55 +2833,55 @@ enum/MSIBIAS: - name: B_0x1 description: MSI bias sampling mode (ultra-low-power mode) value: 1 -enum/MSIKRANGE: +enum/MSIRANGE: bit_size: 4 variants: - - name: B_0x0 + - name: RANGE_48MHZ description: "range 0 around 48 MHz " value: 0 - - name: B_0x1 + - name: RANGE_24MHZ description: "range 1 around 24 MHz " value: 1 - - name: B_0x2 + - name: RANGE_16MHZ description: "range 2 around 16 MHz " value: 2 - - name: B_0x3 + - name: RANGE_12MHZ description: "range 3 around 12 MHz " value: 3 - - name: B_0x4 + - name: RANGE_4MHZ description: "range 4 around 4 MHz (reset value) " value: 4 - - name: B_0x5 + - name: RANGE_2MHZ description: "range 5 around 2 MHz " value: 5 - - name: B_0x6 + - name: RANGE_1_33MHZ description: "range 6 around 1.33 MHz " value: 6 - - name: B_0x7 + - name: RANGE_1MHZ description: "range 7 around 1 MHz " value: 7 - - name: B_0x8 + - name: RANGE_3_072MHZ description: "range 8 around 3.072 MHz " value: 8 - - name: B_0x9 + - name: RANGE_1_536MHZ description: "range 9 around 1.536 MHz " value: 9 - - name: B_0xA + - name: RANGE_1_024MHZ description: "range 10 around 1.024 MHz " value: 10 - - name: B_0xB + - name: RANGE_768KHZ description: "range 11 around 768 kHz " value: 11 - - name: B_0xC + - name: RANGE_400KHZ description: "range 12 around 400 kHz " value: 12 - - name: B_0xD + - name: RANGE_200KHZ description: "range 13 around 200 kHz " value: 13 - - name: B_0xE + - name: RANGE_133KHZ description: range 14 around 133 kHz value: 14 - - name: B_0xF + - name: RANGE_100KHZ description: "range 15 around 100 kHz " value: 15 enum/MSIKRDY: @@ -3084,10 +2950,10 @@ enum/MSIPLLSEL: enum/MSIRGSEL: bit_size: 1 variants: - - name: B_0x0 + - name: RCC_CSR description: "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR" value: 0 - - name: B_0x1 + - name: RCC_ICSCR1 description: "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1" value: 1 enum/MSISEC: @@ -3099,66 +2965,6 @@ enum/MSISEC: - name: B_0x1 description: secure value: 1 -enum/MSISRANGE: - bit_size: 4 - variants: - - name: B_0x0 - description: "range 0 around 48 MHz " - value: 0 - - name: B_0x1 - description: "range 1 around 24 MHz " - value: 1 - - name: B_0x2 - description: "range 2 around 16 MHz " - value: 2 - - name: B_0x3 - description: "range 3 around 12 MHz " - value: 3 - - name: B_0x4 - description: "range 4 around 4 MHz (reset value) " - value: 4 - - name: B_0x5 - description: "range 5 around 2 MHz " - value: 5 - - name: B_0x6 - description: "range 6 around 1.33 MHz " - value: 6 - - name: B_0x7 - description: "range 7 around 1 MHz " - value: 7 - - name: B_0x8 - description: "range 8 around 3.072 MHz " - value: 8 - - name: B_0x9 - description: "range 9 around 1.536 MHz " - value: 9 - - name: B_0xA - description: "range 10 around 1.024 MHz " - value: 10 - - name: B_0xB - description: "range 11 around 768 kHz " - value: 11 - - name: B_0xC - description: "range 12 around 400 kHz " - value: 12 - - name: B_0xD - description: "range 13 around 200 kHz " - value: 13 - - name: B_0xE - description: range 14 around 133 kHz - value: 14 - - name: B_0xF - description: "range 15 around 100 kHz " - value: 15 -enum/MSISRDY: - bit_size: 1 - variants: - - name: B_0x0 - description: MSIS (MSI system) oscillator not ready - value: 0 - - name: B_0x1 - description: MSIS (MSI system) oscillator ready - value: 1 enum/MSISRDYF: bit_size: 1 variants: @@ -3282,24 +3088,6 @@ enum/PLLMBOOST: - name: B_0x8 description: division by 16 value: 8 -enum/PLLN: - bit_size: 9 - variants: - - name: B_0x3 - description: "PLL1N = 4 " - value: 3 - - name: B_0x4 - description: "PLL1N = 5 " - value: 4 - - name: B_0x5 - description: "PLL1N = 6 " - value: 5 - - name: B_0x80 - description: PLL1N = 129 (default after reset) - value: 128 - - name: B_0x1FF - description: PLL1N = 512 - value: 511 enum/PLLP: bit_size: 7 variants: @@ -3336,33 +3124,6 @@ enum/PLLQ: - name: B_0x7F description: pll3_q_ck = vco3_ck / 128 value: 127 -enum/PLLR: - bit_size: 7 - variants: - - name: B_0x0 - description: "pll2_r_ck = vco2_ck " - value: 0 - - name: B_0x1 - description: pll2_r_ck = vco2_ck / 2 (default after reset) - value: 1 - - name: B_0x2 - description: pll2_r_ck = vco2_ck / 3 - value: 2 - - name: B_0x3 - description: pll2_r_ck = vco2_ck / 4 - value: 3 - - name: B_0x7F - description: pll2_r_ck = vco2_ck / 128 - value: 127 -enum/PLLRDY: - bit_size: 1 - variants: - - name: B_0x0 - description: PLL3 unlocked - value: 0 - - name: B_0x1 - description: PLL3 locked - value: 1 enum/PLLRDYF: bit_size: 1 variants: @@ -3399,31 +3160,34 @@ enum/PLLSEC: enum/PLLSRC: bit_size: 2 variants: - - name: B_0x0 + - name: NONE description: No clock sent to PLL3 value: 0 - - name: B_0x1 + - name: MSIS description: MSIS clock selected as PLL3 clock entry value: 1 - - name: B_0x2 + - name: HSI16 description: HSI16 clock selected as PLL3 clock entry value: 2 - - name: B_0x3 + - name: HSE description: HSE clock selected as PLL3 clock entry value: 3 enum/PPRE: bit_size: 3 variants: - - name: B_0x4 + - name: NONE + description: HCLK not divided + value: 0 + - name: DIV2 description: HCLK divided by 2 value: 4 - - name: B_0x5 + - name: DIV4 description: HCLK divided by 4 value: 5 - - name: B_0x6 + - name: DIV8 description: HCLK divided by 8 value: 6 - - name: B_0x7 + - name: DIV16 description: HCLK divided by 16 value: 7 enum/PRESCSEC: @@ -3597,16 +3361,16 @@ enum/STOPWUCK: enum/SW: bit_size: 2 variants: - - name: B_0x0 + - name: MSIS description: MSIS selected as system clock value: 0 - - name: B_0x1 + - name: HSI16 description: HSI16 selected as system clock value: 1 - - name: B_0x2 + - name: HSE description: HSE selected as system clock value: 2 - - name: B_0x3 + - name: PLL1R description: PLL pll1_r_ck selected as system clock value: 3 enum/SWS: