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Rename ICSEL -> I2CSEL

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This commit is contained in:
Dario Nieuwenhuis 2024-02-05 00:36:48 +01:00
parent aa5dbf859f
commit d04eaeb0d5
9 changed files with 50 additions and 50 deletions
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4
data/registers/rcc_f4.yaml
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@ -1613,7 +1613,7 @@ fieldset/DCKCFGR2:
description: FMPI2C1 kernel clock source selection
bit_offset: 22
bit_size: 2
enum: FMPICSEL
enum: FMPI2CSEL
- name: CECSEL
description: HDMI CEC clock source selection
bit_offset: 26
@ -1808,7 +1808,7 @@ enum/DSISEL:
- name: PLL1_R
description: PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)
value: 1
enum/FMPICSEL:
enum/FMPI2CSEL:
bit_size: 2
variants:
- name: PCLK1

4
data/registers/rcc_f410.yaml
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@ -733,7 +733,7 @@ fieldset/DCKCFGR2:
description: FMPI2C1 kernel clock source selection
bit_offset: 22
bit_size: 2
enum: FMPICSEL
enum: FMPI2CSEL
- name: LPTIM1SEL
description: LPTIM1SEL
bit_offset: 30
@ -792,7 +792,7 @@ fieldset/SSCGR:
description: Spread spectrum modulation enable
bit_offset: 31
bit_size: 1
enum/FMPICSEL:
enum/FMPI2CSEL:
bit_size: 2
variants:
- name: PCLK1

10
data/registers/rcc_f7.yaml
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@ -1547,22 +1547,22 @@ fieldset/DCKCFGR2:
description: I2C1 clock source selection
bit_offset: 16
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C2SEL
description: I2C2 clock source selection
bit_offset: 18
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C3SEL
description: I2C3 clock source selection
bit_offset: 20
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C4SEL
description: I2C4 clock source selection
bit_offset: 22
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: LPTIM1SEL
description: Low power timer 1 clock source selection
bit_offset: 24
@ -1767,7 +1767,7 @@ enum/HPRE:
- name: Div512
description: SYSCLK divided by 512
value: 15
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1

18
data/registers/rcc_h5.yaml
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@ -1449,11 +1449,11 @@ fieldset/CCIPR1:
bit_offset: 27
bit_size: 3
enum: USARTSEL
- name: TIMICSEL
- name: TIMI2CSEL
description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software."
bit_offset: 31
bit_size: 1
enum: TIMICSEL
enum: TIMI2CSEL
fieldset/CCIPR2:
description: RCC kernel clock configuration register
fields:
@ -1567,27 +1567,27 @@ fieldset/CCIPR4:
description: I2C1 kernel clock source selection
bit_offset: 16
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C2SEL
description: I2C2 kernel clock source selection
bit_offset: 18
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C3SEL
description: I2C3 kernel clock source selection
bit_offset: 20
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C4SEL
description: I2C4 kernel clock source selection
bit_offset: 22
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I3C1SEL
description: I3C1 kernel clock source selection
bit_offset: 24
bit_size: 2
enum: ICSEL
enum: I2CSEL
fieldset/CCIPR5:
description: RCC kernel clock configuration register
fields:
@ -2231,7 +2231,7 @@ enum/HSIDIV:
- name: Div8
description: Division by 8
value: 3
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1
@ -4121,7 +4121,7 @@ enum/SYSTICKSEL:
- name: LSE
description: lse_ck[1] selected as clock source
value: 2
enum/TIMICSEL:
enum/TIMI2CSEL:
bit_size: 1
variants:
- name: B_0x0

16
data/registers/rcc_h50.yaml
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@ -813,11 +813,11 @@ fieldset/CCIPR1:
bit_offset: 6
bit_size: 3
enum: USARTSEL
- name: TIMICSEL
- name: TIMI2CSEL
description: "TIM2, TIM3 and LPTIM2 input capture source selection\r Set and reset by software."
bit_offset: 31
bit_size: 1
enum: TIMICSEL
enum: TIMI2CSEL
fieldset/CCIPR2:
description: RCC kernel clock configuration register
fields:
@ -871,22 +871,22 @@ fieldset/CCIPR4:
description: I2C1 kernel clock source selection
bit_offset: 16
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C2SEL
description: I2C2 kernel clock source selection
bit_offset: 18
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I3C1SEL
description: I3C1 kernel clock source selection
bit_offset: 24
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I3C2SEL
description: I3C2 kernel clock source selection
bit_offset: 26
bit_size: 2
enum: ICSEL
enum: I2CSEL
fieldset/CCIPR5:
description: RCC kernel clock configuration register
fields:
@ -1440,7 +1440,7 @@ enum/HSIDIV:
- name: Div8
description: Division by 8
value: 3
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1
@ -3162,7 +3162,7 @@ enum/SYSTICKSEL:
- name: LSE
description: lse_ck[1] selected as clock source
value: 2
enum/TIMICSEL:
enum/TIMI2CSEL:
bit_size: 1
variants:
- name: B_0x0

6
data/registers/rcc_l0.yaml
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@ -513,12 +513,12 @@ fieldset/CCIPR:
description: I2C1 clock source selection
bit_offset: 12
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C3SEL
description: I2C3 clock source selection
bit_offset: 16
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: LPTIM1SEL
description: Low Power Timer clock source selection
bit_offset: 18
@ -967,7 +967,7 @@ enum/HPRE:
- name: Div512
description: system clock divided by 512
value: 15
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1

6
data/registers/rcc_l0_v2.yaml
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@ -517,12 +517,12 @@ fieldset/CCIPR:
description: I2C1 clock source selection
bit_offset: 12
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C3SEL
description: I2C3 clock source selection
bit_offset: 16
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: LPTIM1SEL
description: Low Power Timer clock source selection
bit_offset: 18
@ -1016,7 +1016,7 @@ enum/HPRE:
- name: Div512
description: system clock divided by 512
value: 15
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1

22
data/registers/rcc_u5.yaml
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@ -1576,17 +1576,17 @@ fieldset/CCIPR1:
description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 10
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C2SEL
description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 12
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C4SEL
description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 14
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: SPI2SEL
description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 16
@ -1617,11 +1617,11 @@ fieldset/CCIPR1:
bit_offset: 26
bit_size: 2
enum: ICLKSEL
- name: TIMICSEL
description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division."
- name: TIMI2CSEL
description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMI2CSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMI2CSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMI2CSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMI2CSEL configured to 0xx) before selecting or changing a clock sources division."
bit_offset: 29
bit_size: 3
enum: TIMICSEL
enum: TIMI2CSEL
fieldset/CCIPR2:
description: RCC peripherals independent clock configuration register 2
fields:
@ -1684,12 +1684,12 @@ fieldset/CCIPR2:
description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI<53>or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 24
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: I2C6SEL
description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI<53>or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 26
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: OTGHSSEL
description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 30
@ -1712,7 +1712,7 @@ fieldset/CCIPR3:
description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."
bit_offset: 6
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: LPTIM34SEL
description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."
bit_offset: 8
@ -2583,7 +2583,7 @@ enum/ICLKSEL:
- name: MSIK
description: MSIK clock selected
value: 3
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1
@ -4396,7 +4396,7 @@ enum/SYSTICKSEL:
- name: LSE
description: LSE selected
value: 2
enum/TIMICSEL:
enum/TIMI2CSEL:
bit_size: 3
variants:
- name: DISABLE

14
data/registers/rcc_wba.yaml
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@ -775,7 +775,7 @@ fieldset/CCIPR1:
description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI."
bit_offset: 10
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: LPTIM2SEL
description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1."
bit_offset: 18
@ -791,11 +791,11 @@ fieldset/CCIPR1:
bit_offset: 22
bit_size: 2
enum: SYSTICKSEL
- name: TIMICSEL
description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. \r When TIMICSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division."
- name: TIMI2CSEL
description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMI2CSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI/256. \r When TIMI2CSEL is cleared, the HSI, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMI2CSEL configured to 0) before selecting or changing a clock sources division."
bit_offset: 31
bit_size: 1
enum: TIMICSEL
enum: TIMI2CSEL
fieldset/CCIPR2:
description: RCC peripherals independent clock configuration register 2
fields:
@ -821,7 +821,7 @@ fieldset/CCIPR3:
description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI"
bit_offset: 6
bit_size: 2
enum: ICSEL
enum: I2CSEL
- name: LPTIM1SEL
description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1."
bit_offset: 10
@ -1270,7 +1270,7 @@ enum/HSEPRE:
- name: Div2
description: HSE divided, SYSCLK = HSE/2
value: 1
enum/ICSEL:
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1
@ -1546,7 +1546,7 @@ enum/SYSTICKSEL:
- name: LSE
description: LSE selected
value: 2
enum/TIMICSEL:
enum/TIMI2CSEL:
bit_size: 1
variants:
- name: HSI