Fix ADC resolution enum for stm32g4
This commit is contained in:
qff233
parent
2b7ec569a5
commit
cf5ab0f41b
810
data/registers/adc_g4.yaml
Normal file
810
data/registers/adc_g4.yaml
Normal file
@ -0,0 +1,810 @@
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block/ADC:
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description: Analog to Digital Converter
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items:
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- name: ISR
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description: interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR
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description: configuration register 1
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byte_offset: 12
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fieldset: CFGR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 16
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fieldset: CFGR2
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- name: SMPR
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description: sampling time register 1-2
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array:
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len: 2
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stride: 4
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byte_offset: 20
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fieldset: SMPR
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- name: PCSEL
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description: pre channel selection register
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byte_offset: 28
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fieldset: PCSEL
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- name: LTR1
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description: analog watchdog 1 threshold register
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byte_offset: 32
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fieldset: LTR1
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- name: HTR1
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description: analog watchdog 2 threshold register
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byte_offset: 36
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fieldset: HTR1
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- name: SQR1
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description: group regular sequencer ranks register 1
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byte_offset: 48
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fieldset: SQR1
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- name: SQR2
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description: group regular sequencer ranks register 2
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byte_offset: 52
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fieldset: SQR2
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- name: SQR3
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description: group regular sequencer ranks register 3
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byte_offset: 56
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fieldset: SQR3
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- name: SQR4
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description: group regular sequencer ranks register 4
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byte_offset: 60
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fieldset: SQR4
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- name: DR
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description: group regular conversion data register
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byte_offset: 64
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access: Read
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fieldset: DR
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- name: JSQR
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description: group injected sequencer register
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byte_offset: 76
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fieldset: JSQR
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- name: OFR
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description: offset number 1-4 register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: OFR
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- name: JDR
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description: group injected sequencer rank 1-4 register
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array:
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len: 4
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stride: 4
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byte_offset: 128
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access: Read
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fieldset: JDR
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- name: AWD2CR
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description: analog watchdog 2 configuration register
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byte_offset: 160
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fieldset: AWD2CR
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- name: AWD3CR
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description: analog watchdog 3 configuration register
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byte_offset: 164
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fieldset: AWD3CR
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- name: LTR2
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description: watchdog lower threshold register 2
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byte_offset: 176
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fieldset: LTR2
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- name: HTR2
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description: watchdog higher threshold register 2
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byte_offset: 180
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fieldset: HTR2
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- name: LTR3
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description: watchdog lower threshold register 3
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byte_offset: 184
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fieldset: LTR3
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- name: HTR3
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description: watchdog higher threshold register 3
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byte_offset: 188
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fieldset: HTR3
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- name: DIFSEL
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description: channel differential or single-ended mode selection register
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byte_offset: 192
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fieldset: DIFSEL
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- name: CALFACT
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description: calibration factors register
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byte_offset: 196
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fieldset: CALFACT
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- name: CALFACT2
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description: Calibration Factor register 2
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byte_offset: 200
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fieldset: CALFACT2
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fieldset/AWD2CR:
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description: analog watchdog 2 configuration register
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fields:
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- name: AWD2CH
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description: analog watchdog 2 monitored channel selection
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bit_offset: 0
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bit_size: 1
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array:
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len: 20
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stride: 1
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fieldset/AWD3CR:
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description: analog watchdog 3 configuration register
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fields:
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- name: AWD3CH
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description: analog watchdog 3 monitored channel selection
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bit_offset: 1
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bit_size: 1
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array:
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len: 20
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stride: 1
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fieldset/CALFACT:
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description: calibration factors register
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fields:
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- name: CALFACT_S
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description: calibration factor in single-ended mode
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bit_offset: 0
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bit_size: 11
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- name: CALFACT_D
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description: calibration factor in differential mode
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bit_offset: 16
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bit_size: 11
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fieldset/CALFACT2:
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description: Calibration Factor register 2
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fields:
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- name: LINCALFACT
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description: Linearity Calibration Factor
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bit_offset: 0
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bit_size: 30
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fieldset/CFGR:
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description: configuration register 1
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fields:
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- name: DMNGT
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description: DMA transfer enable
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bit_offset: 0
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bit_size: 2
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enum: DMNGT
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- name: RES
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description: data resolution
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bit_offset: 2
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bit_size: 3
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enum: RES
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- name: EXTSEL
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description: group regular external trigger source
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bit_offset: 5
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bit_size: 5
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- name: EXTEN
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description: group regular external trigger polarity
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bit_offset: 10
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bit_size: 2
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enum: EXTEN
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- name: OVRMOD
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description: group regular overrun configuration
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bit_offset: 12
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bit_size: 1
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enum: OVRMOD
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- name: CONT
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description: group regular continuous conversion mode
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bit_offset: 13
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bit_size: 1
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- name: AUTDLY
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description: low power auto wait
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bit_offset: 14
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bit_size: 1
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- name: DISCEN
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description: group regular sequencer discontinuous mode
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bit_offset: 16
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bit_size: 1
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- name: DISCNUM
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description: group regular sequencer discontinuous number of ranks
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bit_offset: 17
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bit_size: 3
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- name: JDISCEN
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description: group injected sequencer discontinuous mode
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bit_offset: 20
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bit_size: 1
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- name: JQM
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description: group injected contexts queue mode
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bit_offset: 21
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bit_size: 1
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enum: JQM
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- name: AWD1SGL
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description: analog watchdog 1 monitoring a single channel or all channels
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bit_offset: 22
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bit_size: 1
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enum: AWD1SGL
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- name: AWD1EN
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description: analog watchdog 1 enable on scope group regular
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bit_offset: 23
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bit_size: 1
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- name: JAWD1EN
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description: analog watchdog 1 enable on scope group injected
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bit_offset: 24
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bit_size: 1
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- name: JAUTO
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description: group injected automatic trigger mode
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bit_offset: 25
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bit_size: 1
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- name: AWD1CH
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description: analog watchdog 1 monitored channel selection
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bit_offset: 26
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bit_size: 5
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- name: JQDIS
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description: group injected contexts queue disable
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bit_offset: 31
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bit_size: 1
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: ROVSE
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description: oversampler enable on scope group regular
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bit_offset: 0
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bit_size: 1
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- name: JOVSE
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description: oversampler enable on scope group injected
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bit_offset: 1
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bit_size: 1
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- name: OVSS
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description: oversampling shift
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bit_offset: 5
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bit_size: 4
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- name: TROVS
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description: oversampling discontinuous mode (triggered mode) for group regular
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bit_offset: 9
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bit_size: 1
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enum: TROVS
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- name: ROVSM
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description: Regular Oversampling mode
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bit_offset: 10
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bit_size: 1
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enum: ROVSM
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- name: RSHIFT1
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description: Right-shift data after Offset 1 correction
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bit_offset: 11
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bit_size: 1
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- name: RSHIFT2
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description: Right-shift data after Offset 2 correction
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bit_offset: 12
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bit_size: 1
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- name: RSHIFT3
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description: Right-shift data after Offset 3 correction
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bit_offset: 13
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bit_size: 1
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- name: RSHIFT4
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description: Right-shift data after Offset 4 correction
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bit_offset: 14
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bit_size: 1
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- name: OSVR
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description: Oversampling ratio
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bit_offset: 16
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bit_size: 10
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- name: LSHIFT
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description: Left shift factor
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bit_offset: 28
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bit_size: 4
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fieldset/CR:
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description: control register
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fields:
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- name: ADEN
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description: enable
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bit_offset: 0
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bit_size: 1
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- name: ADDIS
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description: disable
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bit_offset: 1
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bit_size: 1
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- name: ADSTART
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description: group regular conversion start
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bit_offset: 2
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bit_size: 1
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- name: JADSTART
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description: group injected conversion start
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bit_offset: 3
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bit_size: 1
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- name: ADSTP
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description: group regular conversion stop
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bit_offset: 4
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bit_size: 1
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enum: ADSTP
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- name: JADSTP
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description: group injected conversion stop
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bit_offset: 5
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bit_size: 1
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enum: ADSTP
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- name: BOOST
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description: Boost mode control
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bit_offset: 8
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bit_size: 2
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enum: BOOST
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- name: ADCALLIN
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description: Linearity calibration
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bit_offset: 16
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bit_size: 1
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- name: LINCALRDYW1
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description: Linearity calibration ready Word 1
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bit_offset: 22
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bit_size: 1
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- name: LINCALRDYW2
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description: Linearity calibration ready Word 2
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bit_offset: 23
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bit_size: 1
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- name: LINCALRDYW3
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description: Linearity calibration ready Word 3
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bit_offset: 24
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bit_size: 1
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- name: LINCALRDYW4
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description: Linearity calibration ready Word 4
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bit_offset: 25
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bit_size: 1
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- name: LINCALRDYW5
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description: Linearity calibration ready Word 5
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bit_offset: 26
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bit_size: 1
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- name: LINCALRDYW6
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description: Linearity calibration ready Word 6
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bit_offset: 27
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bit_size: 1
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- name: ADVREGEN
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description: voltage regulator enable
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bit_offset: 28
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bit_size: 1
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- name: DEEPPWD
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description: deep power down enable
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bit_offset: 29
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bit_size: 1
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- name: ADCALDIF
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description: differential mode for calibration
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bit_offset: 30
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bit_size: 1
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enum: ADCALDIF
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- name: ADCAL
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description: calibration
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bit_offset: 31
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bit_size: 1
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fieldset/DIFSEL:
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description: channel differential or single-ended mode selection register
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fields:
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- name: DIFSEL
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description: channel differential or single-ended mode for channel
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bit_offset: 0
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bit_size: 1
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array:
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len: 20
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stride: 1
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enum: DIFSEL
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fieldset/DR:
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description: group regular conversion data register
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fields:
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- name: RDATA
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description: group regular conversion data
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bit_offset: 0
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bit_size: 16
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fieldset/HTR1:
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description: analog watchdog 2 threshold register
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fields:
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- name: HTR1
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description: analog watchdog 2 threshold low
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bit_offset: 0
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bit_size: 26
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fieldset/HTR2:
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description: watchdog higher threshold register 2
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fields:
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- name: HTR2
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description: Analog watchdog 2 higher threshold
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bit_offset: 0
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bit_size: 26
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fieldset/HTR3:
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description: watchdog higher threshold register 3
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fields:
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- name: HTR3
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description: Analog watchdog 3 higher threshold
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bit_offset: 0
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bit_size: 26
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fieldset/IER:
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description: interrupt enable register
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fields:
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- name: ADRDYIE
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description: ready interrupt
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bit_offset: 0
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bit_size: 1
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- name: EOSMPIE
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description: group regular end of sampling interrupt
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bit_offset: 1
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bit_size: 1
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- name: EOCIE
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description: group regular end of unitary conversion interrupt
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bit_offset: 2
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bit_size: 1
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- name: EOSIE
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description: group regular end of sequence conversions interrupt
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bit_offset: 3
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bit_size: 1
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- name: OVRIE
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description: group regular overrun interrupt
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bit_offset: 4
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bit_size: 1
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- name: JEOCIE
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description: group injected end of unitary conversion interrupt
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bit_offset: 5
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bit_size: 1
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- name: JEOSIE
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description: group injected end of sequence conversions interrupt
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bit_offset: 6
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bit_size: 1
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||||||
|
- name: AWD1IE
|
||||||
|
description: analog watchdog 1 interrupt
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: AWD2IE
|
||||||
|
description: analog watchdog 2 interrupt
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: AWD3IE
|
||||||
|
description: analog watchdog 3 interrupt
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: JQOVFIE
|
||||||
|
description: group injected contexts queue overflow interrupt
|
||||||
|
bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/ISR:
|
||||||
|
description: interrupt and status register
|
||||||
|
fields:
|
||||||
|
- name: ADRDY
|
||||||
|
description: ready flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: EOSMP
|
||||||
|
description: group regular end of sampling flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: EOC
|
||||||
|
description: group regular end of unitary conversion flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: EOS
|
||||||
|
description: group regular end of sequence conversions flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: OVR
|
||||||
|
description: group regular overrun flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: JEOC
|
||||||
|
description: group injected end of unitary conversion flag
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: JEOS
|
||||||
|
description: group injected end of sequence conversions flag
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: AWD1
|
||||||
|
description: analog watchdog 1 flag
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: AWD2
|
||||||
|
description: analog watchdog 2 flag
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: AWD3
|
||||||
|
description: analog watchdog 3 flag
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: JQOVF
|
||||||
|
description: group injected contexts queue overflow flag
|
||||||
|
bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
- name: LDORDY
|
||||||
|
description: ADC LDO output voltage ready (not always available)
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/JDR:
|
||||||
|
description: group injected sequencer rank 1 register
|
||||||
|
fields:
|
||||||
|
- name: JDATA
|
||||||
|
description: group injected sequencer rank 1 conversion data
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/JSQR:
|
||||||
|
description: group injected sequencer register
|
||||||
|
fields:
|
||||||
|
- name: JL
|
||||||
|
description: group injected sequencer scan length
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
- name: JEXTSEL
|
||||||
|
description: group injected external trigger source
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 5
|
||||||
|
- name: JEXTEN
|
||||||
|
description: group injected external trigger polarity
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 2
|
||||||
|
enum: JEXTEN
|
||||||
|
- name: JSQ1
|
||||||
|
description: group injected sequencer rank 1-4
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 5
|
||||||
|
array:
|
||||||
|
len: 4
|
||||||
|
stride: 6
|
||||||
|
fieldset/LTR1:
|
||||||
|
description: analog watchdog 1 threshold register
|
||||||
|
fields:
|
||||||
|
- name: LTR1
|
||||||
|
description: analog watchdog 1 threshold low
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 26
|
||||||
|
fieldset/LTR2:
|
||||||
|
description: watchdog lower threshold register 2
|
||||||
|
fields:
|
||||||
|
- name: LTR2
|
||||||
|
description: Analog watchdog 2 lower threshold
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 26
|
||||||
|
fieldset/LTR3:
|
||||||
|
description: watchdog lower threshold register 3
|
||||||
|
fields:
|
||||||
|
- name: LTR3
|
||||||
|
description: Analog watchdog 3 lower threshold
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 26
|
||||||
|
fieldset/OFR:
|
||||||
|
description: offset number x register
|
||||||
|
fields:
|
||||||
|
- name: OFFSET1
|
||||||
|
description: offset number x offset level
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 26
|
||||||
|
- name: OFFSET1_CH
|
||||||
|
description: offset number x channel selection
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 5
|
||||||
|
- name: SSATE
|
||||||
|
description: Signed saturation enable
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PCSEL:
|
||||||
|
description: channel preselection register
|
||||||
|
fields:
|
||||||
|
- name: PCSEL
|
||||||
|
description: Channel x (VINP[i]) pre selection
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 20
|
||||||
|
stride: 1
|
||||||
|
enum: PCSEL
|
||||||
|
fieldset/SMPR:
|
||||||
|
description: sampling time register n
|
||||||
|
fields:
|
||||||
|
- name: SMP
|
||||||
|
description: channel n * 10 + x sampling time
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
array:
|
||||||
|
len: 10
|
||||||
|
stride: 3
|
||||||
|
enum: SAMPLE_TIME
|
||||||
|
fieldset/SQR1:
|
||||||
|
description: group regular sequencer ranks register 1
|
||||||
|
fields:
|
||||||
|
- name: L
|
||||||
|
description: L3
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: SQ
|
||||||
|
description: group regular sequencer rank 1-4
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 5
|
||||||
|
array:
|
||||||
|
len: 4
|
||||||
|
stride: 6
|
||||||
|
fieldset/SQR2:
|
||||||
|
description: group regular sequencer ranks register 2
|
||||||
|
fields:
|
||||||
|
- name: SQ
|
||||||
|
description: group regular sequencer rank 5-9
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 6
|
||||||
|
fieldset/SQR3:
|
||||||
|
description: group regular sequencer ranks register 3
|
||||||
|
fields:
|
||||||
|
- name: SQ
|
||||||
|
description: group regular sequencer rank 10-14
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 6
|
||||||
|
fieldset/SQR4:
|
||||||
|
description: group regular sequencer ranks register 4
|
||||||
|
fields:
|
||||||
|
- name: SQ
|
||||||
|
description: group regular sequencer rank 15-16
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 5
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 6
|
||||||
|
enum/ADCALDIF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: SingleEnded
|
||||||
|
description: Calibration for single-ended mode
|
||||||
|
value: 0
|
||||||
|
- name: Differential
|
||||||
|
description: Calibration for differential mode
|
||||||
|
value: 1
|
||||||
|
enum/ADSTP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Stop
|
||||||
|
description: Stop conversion of channel
|
||||||
|
value: 1
|
||||||
|
enum/AWD1SGL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: All
|
||||||
|
description: Analog watchdog 1 enabled on all channels
|
||||||
|
value: 0
|
||||||
|
- name: Single
|
||||||
|
description: Analog watchdog 1 enabled on single channel selected in AWD1CH
|
||||||
|
value: 1
|
||||||
|
enum/BOOST:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: LT6_25
|
||||||
|
description: Boost mode used when clock ≤ 6.25 MHz
|
||||||
|
value: 0
|
||||||
|
- name: LT12_5
|
||||||
|
description: Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz
|
||||||
|
value: 1
|
||||||
|
- name: LT25
|
||||||
|
description: Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz
|
||||||
|
value: 2
|
||||||
|
- name: LT50
|
||||||
|
description: Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz
|
||||||
|
value: 3
|
||||||
|
enum/DIFSEL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: SingleEnded
|
||||||
|
description: Input channel is configured in single-ended mode
|
||||||
|
value: 0
|
||||||
|
- name: Differential
|
||||||
|
description: Input channel is configured in differential mode
|
||||||
|
value: 1
|
||||||
|
enum/DMNGT:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: DR
|
||||||
|
description: Store output data in DR only
|
||||||
|
value: 0
|
||||||
|
- name: DMA_OneShot
|
||||||
|
description: DMA One Shot Mode selected
|
||||||
|
value: 1
|
||||||
|
- name: DFSDM
|
||||||
|
description: DFSDM mode selected
|
||||||
|
value: 2
|
||||||
|
- name: DMA_Circular
|
||||||
|
description: DMA Circular Mode selected
|
||||||
|
value: 3
|
||||||
|
enum/EXTEN:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: Disabled
|
||||||
|
description: Trigger detection disabled
|
||||||
|
value: 0
|
||||||
|
- name: RisingEdge
|
||||||
|
description: Trigger detection on the rising edge
|
||||||
|
value: 1
|
||||||
|
- name: FallingEdge
|
||||||
|
description: Trigger detection on the falling edge
|
||||||
|
value: 2
|
||||||
|
- name: BothEdges
|
||||||
|
description: Trigger detection on both the rising and falling edges
|
||||||
|
value: 3
|
||||||
|
enum/JEXTEN:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: Disabled
|
||||||
|
description: Trigger detection disabled
|
||||||
|
value: 0
|
||||||
|
- name: RisingEdge
|
||||||
|
description: Trigger detection on the rising edge
|
||||||
|
value: 1
|
||||||
|
- name: FallingEdge
|
||||||
|
description: Trigger detection on the falling edge
|
||||||
|
value: 2
|
||||||
|
- name: BothEdges
|
||||||
|
description: Trigger detection on both the rising and falling edges
|
||||||
|
value: 3
|
||||||
|
enum/JQM:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Mode0
|
||||||
|
description: 'JSQR Mode 0: Queue maintains the last written configuration into JSQR'
|
||||||
|
value: 0
|
||||||
|
- name: Mode1
|
||||||
|
description: 'JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence'
|
||||||
|
value: 1
|
||||||
|
enum/OVRMOD:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Preserve
|
||||||
|
description: Preserve DR register when an overrun is detected
|
||||||
|
value: 0
|
||||||
|
- name: Overwrite
|
||||||
|
description: Overwrite DR register when an overrun is detected
|
||||||
|
value: 1
|
||||||
|
enum/PCSEL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotPreselected
|
||||||
|
description: Input channel x is not pre-selected
|
||||||
|
value: 0
|
||||||
|
- name: Preselected
|
||||||
|
description: Pre-select input channel x
|
||||||
|
value: 1
|
||||||
|
enum/RES:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: Bits12
|
||||||
|
description: 12-bit resolution
|
||||||
|
value: 0
|
||||||
|
- name: Bits10
|
||||||
|
description: 10-bit resolution
|
||||||
|
value: 1
|
||||||
|
- name: Bits8
|
||||||
|
description: 8-bit resolution
|
||||||
|
value: 2
|
||||||
|
- name: Bits6
|
||||||
|
description: 6-bit resolution
|
||||||
|
value: 3
|
||||||
|
enum/ROVSM:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Continued
|
||||||
|
description: Oversampling is temporary stopped and continued after injection sequence
|
||||||
|
value: 0
|
||||||
|
- name: Resumed
|
||||||
|
description: Oversampling is aborted and resumed from start after injection sequence
|
||||||
|
value: 1
|
||||||
|
enum/SAMPLE_TIME:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: Cycles1_5
|
||||||
|
description: 1.5 clock cycles
|
||||||
|
value: 0
|
||||||
|
- name: Cycles2_5
|
||||||
|
description: 2.5 clock cycles
|
||||||
|
value: 1
|
||||||
|
- name: Cycles8_5
|
||||||
|
description: 8.5 clock cycles
|
||||||
|
value: 2
|
||||||
|
- name: Cycles16_5
|
||||||
|
description: 16.5 clock cycles
|
||||||
|
value: 3
|
||||||
|
- name: Cycles32_5
|
||||||
|
description: 32.5 clock cycles
|
||||||
|
value: 4
|
||||||
|
- name: Cycles64_5
|
||||||
|
description: 64.5 clock cycles
|
||||||
|
value: 5
|
||||||
|
- name: Cycles387_5
|
||||||
|
description: 387.5 clock cycles
|
||||||
|
value: 6
|
||||||
|
- name: Cycles810_5
|
||||||
|
description: 810.5 clock cycles
|
||||||
|
value: 7
|
||||||
|
enum/TROVS:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Automatic
|
||||||
|
description: All oversampled conversions for a channel are run following a trigger
|
||||||
|
value: 0
|
||||||
|
- name: Triggered
|
||||||
|
description: Each oversampled conversion for a channel needs a new trigger
|
||||||
|
value: 1
|
||||||
@ -209,7 +209,7 @@ impl PeriMatcher {
|
|||||||
("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
|
("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
|
||||||
("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")),
|
("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")),
|
||||||
("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")),
|
("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")),
|
||||||
("STM32G4.*:ADC:.*", ("adc", "v4", "ADC")),
|
("STM32G4.*:ADC:.*", ("adc", "g4", "ADC")),
|
||||||
("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
|
("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
|
||||||
(".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")),
|
(".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")),
|
||||||
(".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")),
|
(".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")),
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user