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data/registers/pwr_h5.yaml
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@ -1,394 +1,360 @@
block/PWR: block/PWR:
description: Power control description: Power control.
items: items:
- name: PMCR - name: PMCR
description: PWR power mode control register description: PWR power mode control register.
byte_offset: 0 byte_offset: 0
fieldset: PMCR fieldset: PMCR
- name: PMSR - name: PMSR
description: PWR status register description: PWR status register.
byte_offset: 4 byte_offset: 4
fieldset: PMSR fieldset: PMSR
- name: VOSCR - name: VOSCR
description: PWR voltage scaling control register description: PWR voltage scaling control register.
byte_offset: 16 byte_offset: 16
fieldset: VOSCR fieldset: VOSCR
- name: VOSSR - name: VOSSR
description: PWR voltage scaling status register description: PWR voltage scaling status register.
byte_offset: 20 byte_offset: 20
fieldset: VOSSR fieldset: VOSSR
- name: BDCR - name: BDCR
description: PWR Backup domain control register description: PWR Backup domain control register.
byte_offset: 32 byte_offset: 32
fieldset: BDCR fieldset: BDCR
- name: DBPCR - name: DBPCR
description: PWR Backup domain control register description: PWR Backup domain control register.
byte_offset: 36 byte_offset: 36
fieldset: DBPCR fieldset: DBPCR
- name: BDSR - name: BDSR
description: PWR Backup domain status register description: PWR Backup domain status register.
byte_offset: 40 byte_offset: 40
fieldset: BDSR fieldset: BDSR
- name: UCPDR - name: UCPDR
description: PWR USB Type-C power delivery register description: PWR USB Type-C power delivery register.
byte_offset: 44 byte_offset: 44
fieldset: UCPDR fieldset: UCPDR
- name: SCCR - name: SCCR
description: PWR supply configuration control register description: PWR supply configuration control register.
byte_offset: 48 byte_offset: 48
fieldset: SCCR fieldset: SCCR
- name: VMCR - name: VMCR
description: PWR voltage monitor control register description: PWR voltage monitor control register.
byte_offset: 52 byte_offset: 52
fieldset: VMCR fieldset: VMCR
- name: USBSCR - name: USBSCR
description: PWR USB supply control register description: PWR USB supply control register.
byte_offset: 56 byte_offset: 56
fieldset: USBSCR fieldset: USBSCR
- name: VMSR - name: VMSR
description: PWR voltage monitor status register description: PWR voltage monitor status register.
byte_offset: 60 byte_offset: 60
fieldset: VMSR fieldset: VMSR
- name: WUSCR - name: WUSCR
description: PWR wakeup status clear register description: PWR wakeup status clear register.
byte_offset: 64 byte_offset: 64
fieldset: WUSCR fieldset: WUSCR
- name: WUSR - name: WUSR
description: PWR wakeup status register description: PWR wakeup status register.
byte_offset: 68 byte_offset: 68
fieldset: WUSR fieldset: WUSR
- name: WUCR - name: WUCR
description: PWR wakeup configuration register description: PWR wakeup configuration register.
byte_offset: 72 byte_offset: 72
fieldset: WUCR fieldset: WUCR
- name: IORETR - name: IORETR
description: PWR I/O retention register description: PWR I/O retention register.
byte_offset: 80 byte_offset: 80
fieldset: IORETR fieldset: IORETR
- name: SECCFGR - name: SECCFGR
description: PWR security configuration register description: PWR security configuration register.
byte_offset: 256 byte_offset: 256
fieldset: SECCFGR fieldset: SECCFGR
- name: PRIVCFGR - name: PRIVCFGR
description: PWR privilege configuration register description: PWR privilege configuration register.
byte_offset: 260 byte_offset: 260
fieldset: PRIVCFGR fieldset: PRIVCFGR
fieldset/BDCR: fieldset/BDCR:
description: PWR Backup domain control register description: PWR Backup domain control register.
fields: fields:
- name: BREN - name: BREN
description: "Backup RAM retention in Standby and V<sub>BAT</sub> modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V<sub>BAT</sub> modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and V<sub>BAT</sub> modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V<sub>BAT</sub> modes." description: Backup RAM retention in Standby and V_BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V_BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in. Run and Stop modes. However its content is lost in Standby and V_BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V_BAT modes.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: Retention
- name: MONEN - name: MONEN
description: Backup domain voltage and temperature monitoring enable description: Backup domain voltage and temperature monitoring enable.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: VBE - name: VBE
description: "V<sub>BAT</sub> charging enable\r Note: Reset only by POR,." description: 'V_BAT charging enable Note: Reset only by POR,.'
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: VBRS - name: VBRS
description: V<sub>BAT</sub> charging resistor selection description: V_BAT charging resistor selection.
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: VBRS enum: VBRS
fieldset/BDSR: fieldset/BDSR:
description: PWR Backup domain status register description: PWR Backup domain status register.
fields: fields:
- name: BRRDY - name: BRRDY
description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." description: backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready.
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: VBATL - name: VBATL
description: V<sub>BAT</sub> level monitoring versus low threshold description: V_BAT level monitoring versus low threshold.
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: VBATH - name: VBATH
description: V<sub>BAT</sub> level monitoring versus high threshold description: V_BAT level monitoring versus high threshold.
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: TEMPL - name: TEMPL
description: temperature level monitoring versus low threshold description: temperature level monitoring versus low threshold.
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
- name: TEMPH - name: TEMPH
description: temperature level monitoring versus high threshold description: temperature level monitoring versus high threshold.
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
fieldset/DBPCR: fieldset/DBPCR:
description: PWR Backup domain control register description: PWR Backup domain control register.
fields: fields:
- name: DBP - name: DBP
description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." description: Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write. access. This bit must be set to enable write access to these registers.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
fieldset/IORETR: fieldset/IORETR:
description: PWR I/O retention register description: PWR I/O retention register.
fields: fields:
- name: IORETEN - name: IORETEN
description: "IO retention enable:\r When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." description: 'IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register.'
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: JTAGIORETEN - name: JTAGIORETEN
description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode" description: IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode.
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/PMCR: fieldset/PMCR:
description: PWR power mode control register description: PWR power mode control register.
fields: fields:
- name: LPMS - name: LPMS
description: "low-power mode selection\r This bit defines the Deepsleep mode." description: low-power mode selection This bit defines the Deepsleep mode.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: LPMS
- name: SVOS - name: SVOS
description: "system Stop mode voltage scaling selection\r These bits control the V<sub>CORE</sub> voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." description: system Stop mode voltage scaling selection These bits control the V_CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance.
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum: SVOS enum: SVOS
- name: CSSF - name: CSSF
description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." description: clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware.
bit_offset: 7 bit_offset: 7
bit_size: 1 bit_size: 1
- name: FLPS - name: FLPS
description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." description: 'Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode.'
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum: PowerModeInStopMode
- name: BOOSTE - name: BOOSTE
description: "analog switch V<sub>BOOST</sub> control\r This bit enables the booster to guarantee the analog switch AC performance when the V<sub>DD</sub> supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V<sub>DD</sub> supply voltage can be monitored through the PVD and the PLS bits." description: analog switch V_BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V_DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V_DD supply voltage can be monitored through the PVD and the PLS bits.
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: AVD_READY - name: AVD_READY
description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected V<sub>DDA</sub> analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." description: analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V_DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored. (ALS bits).
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: ETHERNETSO - name: ETHERNETSO
description: ETHERNET RAM shut-off in Stop mode. description: ETHERNET RAM shut-off in Stop mode.
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: ShutOff
- name: SRAM3SO - name: SRAM3SO
description: AHB SRAM3 shut-off in Stop mode. description: AHB SRAM3 shut-off in Stop mode.
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
enum: ShutOff
- name: SRAM2_16SO - name: SRAM2_16SO
description: AHB SRAM2 16-Kbyte shut-off in Stop mode. description: AHB SRAM2 16-Kbyte shut-off in Stop mode.
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
enum: ShutOff
- name: SRAM2_48SO - name: SRAM2_48SO
description: AHB SRAM2 48-Kbyte shut-off in Stop mode. description: AHB SRAM2 48-Kbyte shut-off in Stop mode.
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
enum: ShutOff
- name: SRAM1SO - name: SRAM1SO
description: AHB SRAM1 shut-off in Stop mode description: AHB SRAM1 shut-off in Stop mode.
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
enum: ShutOff
fieldset/PMSR: fieldset/PMSR:
description: PWR status register description: PWR status register.
fields: fields:
- name: STOPF - name: STOPF
description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." description: Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit.
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: SBF - name: SBF
description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." description: System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit.
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
fieldset/PRIVCFGR: fieldset/PRIVCFGR:
description: PWR privilege configuration register description: PWR privilege configuration register.
fields: fields:
- name: SPRIV - name: SPRIV
description: "PWR secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." description: PWR secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: PRIV
- name: NSPRIV - name: NSPRIV
description: "PWR non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." description: PWR non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum: PRIV
fieldset/SCCR: fieldset/SCCR:
description: PWR supply configuration control register description: PWR supply configuration control register.
fields: fields:
- name: BYPASS - name: BYPASS
description: power management unit bypass description: power management unit bypass.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: LDOEN - name: LDOEN
description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." description: LDO enable The value is set by hardware when the package uses the LDO regulator.
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: SMPSEN - name: SMPSEN
description: "SMPS enable \r The value is set by hardware when the package uses the SMPS regulator." description: SMPS enable The value is set by hardware when the package uses the SMPS regulator.
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
fieldset/SECCFGR: fieldset/SECCFGR:
description: PWR security configuration register description: PWR security configuration register.
fields: fields:
- name: WUP1SEC - name: WUPSEC
description: WUPx secure protection description: WUPx secure protection.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: SEC array:
- name: WUP2SEC len: 8
description: WUPx secure protection stride: 1
bit_offset: 1
bit_size: 1
enum: SEC
- name: WUP3SEC
description: WUPx secure protection
bit_offset: 2
bit_size: 1
enum: SEC
- name: WUP4SEC
description: WUPx secure protection
bit_offset: 3
bit_size: 1
enum: SEC
- name: WUP5SEC
description: WUPx secure protection
bit_offset: 4
bit_size: 1
enum: SEC
- name: WUP6SEC
description: WUPx secure protection
bit_offset: 5
bit_size: 1
enum: SEC
- name: WUP7SEC
description: WUPx secure protection
bit_offset: 6
bit_size: 1
enum: SEC
- name: WUP8SEC
description: WUPx secure protection
bit_offset: 7
bit_size: 1
enum: SEC
- name: RETSEC - name: RETSEC
description: retention secure protection description: retention secure protection.
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum: SEC
- name: LPMSEC - name: LPMSEC
description: low-power modes secure protection description: low-power modes secure protection.
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum: SEC
- name: SCMSEC - name: SCMSEC
description: supply configuration and monitoring secure protection. description: supply configuration and monitoring secure protection.
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
enum: SEC
- name: VBSEC - name: VBSEC
description: backup domain secure protection description: backup domain secure protection.
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum: SEC
- name: VUSBSEC - name: VUSBSEC
description: voltage USB secure protection description: voltage USB secure protection.
bit_offset: 15 bit_offset: 15
bit_size: 1 bit_size: 1
enum: SEC
fieldset/UCPDR: fieldset/UCPDR:
description: PWR USB Type-C power delivery register description: PWR USB Type-C power delivery register.
fields: fields:
- name: UCPD_DBDIS - name: UCPD_DBDIS
description: "USB Type-C and power delivery dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable)." description: USB Type-C and power delivery dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable).
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: UCPD_STBY - name: UCPD_STBY
description: "USB Type-c and Power delivery Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register." description: USB Type-c and Power delivery Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
fieldset/USBSCR: fieldset/USBSCR:
description: PWR USB supply control register description: PWR USB supply control register.
fields: fields:
- name: USB33DEN - name: USB33DEN
description: V<sub>DDUSB</sub> voltage level detector enable description: V_DDUSB voltage level detector enable.
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: USB33SV - name: USB33SV
description: "independent USB supply valid\r This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If V<sub>DDUSB</sub> is not always present in the application, the V<sub>DDUSB</sub> voltage monitor can be used to determine whether this supply is ready or not." description: independent USB supply valid This bit is used to validate the V_DDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If V_DDUSB is not always present in the application, the V_DDUSB voltage monitor can be used to determine whether this supply is ready or not.
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
fieldset/VMCR: fieldset/VMCR:
description: PWR voltage monitor control register description: PWR voltage monitor control register.
fields: fields:
- name: PVDE - name: PVDE
description: PVD enable description: PVD enable.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: PLS - name: PLS
description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." description: programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD.
bit_offset: 1 bit_offset: 1
bit_size: 3 bit_size: 3
enum: PLS enum: PLS
- name: AVDEN - name: AVDEN
description: peripheral voltage monitor on V<sub>DDA</sub> enable description: peripheral voltage monitor on V_DDA enable.
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: ALS - name: ALS
description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." description: analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD.
bit_offset: 9 bit_offset: 9
bit_size: 2 bit_size: 2
enum: ALS enum: ALS
fieldset/VMSR: fieldset/VMSR:
description: PWR voltage monitor status register description: PWR voltage monitor status register.
fields: fields:
- name: AVDO - name: AVDO
description: "analog voltage detector output on V<sub>DDA</sub>\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." description: 'analog voltage detector output on V_DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set.'
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
enum: AVDO
- name: VDDIO2RDY - name: VDDIO2RDY
description: "voltage detector output on V<sub>DDIO2</sub>\r This bit is set and cleared by hardware." description: voltage detector output on V_DDIO2 This bit is set and cleared by hardware.
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
- name: PVDO - name: PVDO
description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." description: 'programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.'
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: PVDO
- name: USB33RDY - name: USB33RDY
description: V<sub>DDUSB</sub> ready description: V_DDUSB ready.
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
fieldset/VOSCR: fieldset/VOSCR:
description: PWR voltage scaling control register description: PWR voltage scaling control register.
fields: fields:
- name: VOS - name: VOS
description: "voltage scaling selection according to performance\r These bits control the V<sub>CORE</sub> voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." description: 'voltage scaling selection according to performance These bits control the V_CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling.'
bit_offset: 4 bit_offset: 4
bit_size: 2 bit_size: 2
enum: VOS enum: VOS
fieldset/VOSSR: fieldset/VOSSR:
description: PWR voltage scaling status register description: PWR voltage scaling status register.
fields: fields:
- name: VOSRDY - name: VOSRDY
description: Ready bit for V<sub>CORE</sub> voltage scaling output selection. description: Ready bit for V_CORE voltage scaling output selection.
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: ACTVOSRDY - name: ACTVOSRDY
description: Voltage level ready for currently used VOS description: Voltage level ready for currently used VOS.
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
- name: ACTVOS - name: ACTVOS
description: "voltage output scaling currently applied to V<sub>CORE</sub>\r This field provides the last VOS value." description: voltage output scaling currently applied to V_CORE This field provides the last VOS value.
bit_offset: 14 bit_offset: 14
bit_size: 2 bit_size: 2
enum: ACTVOS enum: VOS
fieldset/WUCR: fieldset/WUCR:
description: PWR wakeup configuration register description: PWR wakeup configuration register.
fields: fields:
- name: WUPEN - name: WUPEN
description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." description: 'enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge.'
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 1 stride: 1
- name: WUPP - name: WUPP
description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." description: wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin.
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
array: array:
@ -396,7 +362,7 @@ fieldset/WUCR:
stride: 1 stride: 1
enum: WUPP enum: WUPP
- name: WUPPUPD - name: WUPPUPD
description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." description: wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode.
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
array: array:
@ -404,178 +370,150 @@ fieldset/WUCR:
stride: 2 stride: 2
enum: WUPPUPD enum: WUPPUPD
fieldset/WUSCR: fieldset/WUSCR:
description: PWR wakeup status clear register description: PWR wakeup status clear register.
fields: fields:
- name: CWUF - name: CWUF
description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." description: clear wakeup pin flag for WUFx These bits are always read as 0.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 1 stride: 1
fieldset/WUSR: fieldset/WUSR:
description: PWR wakeup status register description: PWR wakeup status register.
fields: fields:
- name: WUF - name: WUF
description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." description: wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register.
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
array: array:
len: 8 len: 8
stride: 1 stride: 1
enum/ACTVOS:
bit_size: 2
variants:
- name: B_0x0
description: VOS3 (lowest power)
value: 0
- name: B_0x1
description: VOS2
value: 1
- name: B_0x2
description: VOS1
value: 2
- name: B_0x3
description: VOS0 (highest frequency)
value: 3
enum/ALS: enum/ALS:
bit_size: 2 bit_size: 2
variants: variants:
- name: B_0x0 - name: Level0
description: 1.7 V description: AVD level0 (VAVD0 ~ 1.7 V)
value: 0 value: 0
- name: B_0x1 - name: Level1
description: 2.1 V description: AVD level1 (VAVD1 ~ 2.1 V)
value: 1 value: 1
- name: B_0x2 - name: Level2
description: 2.5 V description: AVD level2 (VAVD2 ~ 2.5 V)
value: 2 value: 2
- name: B_0x3 - name: Level3
description: 2.8 V description: AVD level3 (VAVD3 ~ 2.8 V)
value: 3 value: 3
enum/AVDO: enum/LPMS:
bit_size: 1 bit_size: 1
variants: variants:
- name: B_0x0 - name: Stop
description: V<sub>DDA</sub> is equal or higher than the AVD threshold selected with the ALS[2:0] bits. description: Keeps Stop mode when entering DeepSleep.
value: 0 value: 0
- name: B_0x1 - name: Standby
description: V<sub>DDA</sub> is lower than the AVD threshold selected with the ALS[2:0] bits. description: Allows Standby mode when entering DeepSleep.
value: 1 value: 1
enum/PLS: enum/PLS:
bit_size: 3 bit_size: 3
variants: variants:
- name: B_0x0 - name: Level0
description: 1.95 V description: PVD level0 (VPVD0 ~ 1.95 V)
value: 0 value: 0
- name: B_0x1 - name: Level1
description: 2.1 V description: PVD level1 (VPVD1 ~ 2.10 V)
value: 1 value: 1
- name: B_0x2 - name: Level2
description: 2.25 V description: PVD level2 (VPVD2 ~ 2.25 V)
value: 2 value: 2
- name: B_0x3 - name: Level3
description: 2.4 V description: PVD level3 (VPVD3 ~ 2.40 V)
value: 3 value: 3
- name: B_0x4 - name: Level4
description: 2.55 V description: PVD level4 (VPVD4 ~ 2.55 V)
value: 4 value: 4
- name: B_0x5 - name: Level5
description: 2.7 V description: PVD level5 (VPVD5 ~ 2.70 V)
value: 5 value: 5
- name: B_0x6 - name: Level6
description: 2.85 V description: PVD level6 (VPVD6 ~ 2.85 V)
value: 6 value: 6
- name: B_0x7 - name: PVDInPin
description: PVD_IN pin description: PVD_IN pin
value: 7 value: 7
enum/PRIV: enum/PowerModeInStopMode:
bit_size: 1 bit_size: 1
variants: variants:
- name: B_0x0 - name: Normal
description: Read and write to PWR secure functions can be done by privileged or unprivileged access. description: Remains in normal mode when the system enters Stop mode (quick restart time).
value: 0 value: 0
- name: B_0x1 - name: LowPower
description: Read and write to PWR secure functions can be done by privileged access only. description: Enters low-power mode when the system enters Stop mode (low-power consumption).
value: 1 value: 1
enum/PVDO: enum/Retention:
bit_size: 1 bit_size: 1
variants: variants:
- name: B_0x0 - name: Lost
description: V<sub>DD</sub> is equal or higher than the PVD threshold selected through the PLS[2:0] bits. description: Content is lost.
value: 0 value: 0
- name: B_0x1 - name: Preserved
description: V<sub>DD</sub> is lower than the PVD threshold selected through the PLS[2:0] bits. description: Content is preserved.
value: 1
enum/SEC:
bit_size: 1
variants:
- name: B_0x0
description: PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access.
value: 0
- name: B_0x1
description: PWR_SCCR and PWR_VMCR can be read and written only with secure access.
value: 1 value: 1
enum/SVOS: enum/SVOS:
bit_size: 2 bit_size: 2
variants: variants:
- name: B_0x0 - name: Scale5
description: reserved
value: 0
- name: B_0x1
description: SVOS5 scale 5 description: SVOS5 scale 5
value: 1 value: 1
- name: B_0x2 - name: Scale4
description: SVOS4 scale 4 description: SVOS4 scale 4
value: 2 value: 2
- name: B_0x3 - name: Scale3
description: SVOS3 scale 3 (default). description: SVOS3 scale 3 (default)
value: 3 value: 3
enum/ShutOff:
bit_size: 1
variants:
- name: Kept
description: Content is kept.
value: 0
- name: Lost
description: Content is lost.
value: 1
enum/VBRS: enum/VBRS:
bit_size: 1 bit_size: 1
variants: variants:
- name: B_0x0 - name: R5kOhm
description: Charge V<sub>BAT</sub> through a 5 kΩ resistor. description: Charge VBAT through a 5 kΩ resistor.
value: 0 value: 0
- name: B_0x1 - name: R1_5kOhm
description: Charge V<sub>BAT</sub> through a 1.5 kΩ resistor. description: Charge VBAT through a 1.5 kΩ resistor.
value: 1 value: 1
enum/VOS: enum/VOS:
bit_size: 2 bit_size: 2
variants: variants:
- name: Scale3 - name: Scale3
description: scale 3 (default)
value: 0 value: 0
- name: Scale2 - name: Scale2
description: scale 2
value: 1 value: 1
- name: Scale1 - name: Scale1
description: scale 1
value: 2 value: 2
- name: Scale0 - name: Scale0
description: scale 0
value: 3 value: 3
enum/WUPP: enum/WUPP:
bit_size: 1 bit_size: 1
variants: variants:
- name: B_0x0 - name: High
description: detection on high level (rising edge) description: detection on high level (rising edge)
value: 0 value: 0
- name: B_0x1 - name: Low
description: detection on low level (falling edge) description: detection on low level (falling edge)
value: 1 value: 1
enum/WUPPUPD: enum/WUPPUPD:
bit_size: 2 bit_size: 2
variants: variants:
- name: B_0x0 - name: NoPullUp
description: no pull-up
value: 0 value: 0
- name: B_0x1 - name: PullUp
description: pull-up
value: 1 value: 1
- name: B_0x2 - name: PullDown
description: pull-down
value: 2 value: 2
- name: B_0x3
description: reserved
value: 3

15
transforms/PWR.yaml
View File

@ -1,3 +1,18 @@
transforms: transforms:
- !DeleteEnums - !DeleteEnums
from: ^(PRIV|RRSB|SEC|RADIORSB|REGPARDYVDDRFPA)$ from: ^(PRIV|RRSB|SEC|RADIORSB|REGPARDYVDDRFPA)$
- !MakeFieldArray
fieldsets: WUSC?R
from: (C?WUF)\d
to: $1
- !MakeFieldArray
fieldsets: WUCR
from: (WUPEN|WUPP(UPD)?)\d
to: $1
- !MakeFieldArray
fieldsets: SECCFGR
from: (WUP)\d(SEC)
to: $1$2