extract
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eZio Pan
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data/registers/dcache_v1.yaml
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193
data/registers/dcache_v1.yaml
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block/DCACHE:
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description: Data cache.
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items:
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- name: CR
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description: DCACHE control register.
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byte_offset: 0
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fieldset: CR
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- name: SR
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description: DCACHE status register.
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byte_offset: 4
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fieldset: SR
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- name: IER
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description: DCACHE interrupt enable register.
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byte_offset: 8
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fieldset: IER
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- name: FCR
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description: DCACHE flag clear register.
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byte_offset: 12
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fieldset: FCR
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- name: RHMONR
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description: DCACHE read-hit monitor register.
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byte_offset: 16
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fieldset: RHMONR
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- name: RMMONR
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description: DCACHE read-miss monitor register.
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byte_offset: 20
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fieldset: RMMONR
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- name: WHMONR
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description: DCACHE write-hit monitor register.
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byte_offset: 32
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fieldset: WHMONR
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- name: WMMONR
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description: DCACHE write-miss monitor register.
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byte_offset: 36
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fieldset: WMMONR
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- name: CMDRSADDRR
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description: DCACHE command range start address register.
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byte_offset: 40
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fieldset: CMDRSADDRR
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- name: CMDREADDRR
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description: DCACHE command range end address register.
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byte_offset: 44
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fieldset: CMDREADDRR
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fieldset/CMDREADDRR:
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description: DCACHE command range end address register.
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fields:
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- name: CMDENDADDR
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description: end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.
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bit_offset: 4
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bit_size: 28
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fieldset/CMDRSADDRR:
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description: DCACHE command range start address register.
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fields:
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- name: CMDSTARTADDR
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description: start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written..
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bit_offset: 4
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bit_size: 28
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fieldset/CR:
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description: DCACHE control register.
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fields:
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- name: EN
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description: enable.
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bit_offset: 0
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bit_size: 1
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- name: CACHEINV
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description: full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect.
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bit_offset: 1
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bit_size: 1
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- name: CACHECMD
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description: 'cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved.'
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bit_offset: 8
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bit_size: 3
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- name: STARTCMD
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description: starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect.
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bit_offset: 11
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bit_size: 1
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- name: RHITMEN
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description: read-hit monitor enable.
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bit_offset: 16
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bit_size: 1
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- name: RMISSMEN
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description: read-miss monitor enable.
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bit_offset: 17
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bit_size: 1
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- name: RHITMRST
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description: read-hit monitor reset.
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bit_offset: 18
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bit_size: 1
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- name: RMISSMRST
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description: read-miss monitor reset.
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bit_offset: 19
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bit_size: 1
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- name: WHITMEN
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description: write-hit monitor enable.
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bit_offset: 20
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bit_size: 1
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- name: WMISSMEN
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description: write-miss monitor enable.
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bit_offset: 21
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bit_size: 1
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- name: WHITMRST
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description: write-hit monitor reset.
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bit_offset: 22
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bit_size: 1
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- name: WMISSMRST
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description: write-miss monitor reset.
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bit_offset: 23
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bit_size: 1
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- name: HBURST
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description: output burst type for cache master port read accesses Write access is always done in INCR burst type.
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bit_offset: 31
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bit_size: 1
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fieldset/FCR:
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description: DCACHE flag clear register.
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fields:
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- name: CBSYENDF
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description: clear full invalidate busy end flag Set by software.
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bit_offset: 1
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bit_size: 1
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- name: CERRF
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description: clear cache error flag Set by software.
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bit_offset: 2
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bit_size: 1
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- name: CCMDENDF
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description: clear command end flag Set by software.
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bit_offset: 4
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bit_size: 1
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fieldset/IER:
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description: DCACHE interrupt enable register.
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fields:
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- name: BSYENDIE
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description: interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation.
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bit_offset: 1
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bit_size: 1
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- name: ERRIE
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description: interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error).
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bit_offset: 2
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bit_size: 1
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- name: CMDENDIE
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description: interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range).
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bit_offset: 4
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bit_size: 1
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fieldset/RHMONR:
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description: DCACHE read-hit monitor register.
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fields:
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- name: RHITMON
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description: cache read-hit monitor counter.
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bit_offset: 0
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bit_size: 32
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fieldset/RMMONR:
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description: DCACHE read-miss monitor register.
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fields:
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- name: RMISSMON
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description: cache read-miss monitor counter.
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bit_offset: 0
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bit_size: 16
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fieldset/SR:
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description: DCACHE status register.
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fields:
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- name: BUSYF
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description: full invalidate busy flag.
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bit_offset: 0
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bit_size: 1
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- name: BSYENDF
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description: full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1.
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bit_offset: 1
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bit_size: 1
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- name: ERRF
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description: cache error flag Cleared by writing DCACHE_FCR.CERRF = 1.
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bit_offset: 2
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bit_size: 1
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- name: BUSYCMDF
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description: command busy flag.
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bit_offset: 3
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bit_size: 1
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- name: CMDENDF
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description: command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1.
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bit_offset: 4
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bit_size: 1
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fieldset/WHMONR:
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description: DCACHE write-hit monitor register.
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fields:
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- name: WHITMON
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description: cache write-hit monitor counter.
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bit_offset: 0
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bit_size: 32
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fieldset/WMMONR:
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description: DCACHE write-miss monitor register.
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fields:
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- name: WMISSMON
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description: cache write-miss monitor counter.
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bit_offset: 0
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bit_size: 16
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