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adc/f3: more cleanup

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xoviat 2023-07-12 18:00:55 -05:00
parent cada030e1a
commit c943b0472d
1 changed files with 27 additions and 219 deletions
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246
data/registers/adc_f3.yaml
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@ -118,147 +118,123 @@ fieldset/CFGR:
description: configuration register description: configuration register
fields: fields:
- name: DMAEN - name: DMAEN
description: DMAEN description: Direct memory access enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: DMAEN
- name: DMACFG - name: DMACFG
description: DMACFG description: Direct memory access configuration
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum: DMACFG
- name: RES - name: RES
description: RES description: Data resolution
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum: RES enum: RES
- name: ALIGN - name: ALIGN
description: ALIGN description: Data alignment
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum: ALIGN enum: ALIGN
- name: EXTSEL - name: EXTSEL
description: EXTSEL description: External trigger selection for regular group
bit_offset: 6 bit_offset: 6
bit_size: 4 bit_size: 4
enum: EXTSEL enum: EXTSEL
- name: EXTEN - name: EXTEN
description: EXTEN description: External trigger enable and polarity selection for regular channels
bit_offset: 10 bit_offset: 10
bit_size: 2 bit_size: 2
enum: EXTEN enum: EXTEN
- name: OVRMOD - name: OVRMOD
description: OVRMOD description: Overrun Mode
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum: OVRMOD
- name: CONT - name: CONT
description: CONT description: Single / continuous conversion mode for regular conversions
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
enum: CONT
- name: AUTDLY - name: AUTDLY
description: AUTDLY description: Delayed conversion mode
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum: AUTDLY
- name: DISCEN - name: DISCEN
description: DISCEN description: Discontinuous mode for regular channels
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: DISCEN
- name: DISCNUM - name: DISCNUM
description: DISCNUM description: Discontinuous mode channel count
bit_offset: 17 bit_offset: 17
bit_size: 3 bit_size: 3
- name: JDISCEN - name: JDISCEN
description: JDISCEN description: Discontinuous mode on injected channels
bit_offset: 20 bit_offset: 20
bit_size: 1 bit_size: 1
enum: JDISCEN
- name: JQM - name: JQM
description: JQM description: JSQR queue mode
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
enum: JQM enum: JQM
- name: AWD1SGL - name: AWD1SGL
description: AWD1SGL description: Enable the watchdog 1 on a single channel or on all channels
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: AWD1SGL enum: AWD1SGL
- name: AWD1EN - name: AWD1EN
description: AWD1EN description: Analog watchdog 1 enable on regular channels
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
enum: AWD1EN
- name: JAWD1EN - name: JAWD1EN
description: JAWD1EN description: Analog watchdog 1 enable on injected channels
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
enum: JAWD1EN
- name: JAUTO - name: JAUTO
description: JAUTO description: Automatic injected group conversion
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
enum: JAUTO
- name: AWD1CH - name: AWD1CH
description: AWDCH1CH description: Analog watchdog 1 channel selection
bit_offset: 26 bit_offset: 26
bit_size: 5 bit_size: 5
fieldset/CR: fieldset/CR:
description: control register description: control register
fields: fields:
- name: ADEN - name: ADEN
description: ADEN description: ADC enable control
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: ADENR
enum_write: ADENW
- name: ADDIS - name: ADDIS
description: ADDIS description: ADC disable command
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_read: ADDISR
enum_write: ADDISW
- name: ADSTART - name: ADSTART
description: ADSTART description: ADC start of regular conversion
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: ADSTARTR
enum_write: ADSTARTW
- name: JADSTART - name: JADSTART
description: JADSTART description: ADC start of injected conversion
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: ADSTARTR
enum_write: ADSTARTW
- name: ADSTP - name: ADSTP
description: ADSTP description: ADC stop of regular conversion command
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: ADSTPR
enum_write: ADSTPW
- name: JADSTP - name: JADSTP
description: JADSTP description: ADC stop of injected conversion command
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: ADSTPR
enum_write: ADSTPW
- name: ADVREGEN - name: ADVREGEN
description: ADVREGEN description: ADC voltage regulator enable
bit_offset: 28 bit_offset: 28
bit_size: 2 bit_size: 2
enum: ADVREGEN enum: ADVREGEN
- name: ADCALDIF - name: ADCALDIF
description: ADCALDIF description: Differential mode for calibration
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
enum: ADCALDIF
- name: ADCAL - name: ADCAL
description: ADCAL description: ADC calibration
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
enum: ADCAL
fieldset/DIFSEL: fieldset/DIFSEL:
description: "Differential Mode Selection Register\r 2" description: "Differential Mode Selection Register\r 2"
fields: fields:
@ -613,54 +589,6 @@ fieldset/TR3:
description: HT3 description: HT3
bit_offset: 16 bit_offset: 16
bit_size: 8 bit_size: 8
enum/ADCAL:
bit_size: 1
variants:
- name: Complete
description: Calibration complete
value: 0
- name: Calibration
description: Start the calibration of the ADC
value: 1
enum/ADCALDIF:
bit_size: 1
variants:
- name: SingleEnded
description: Calibration for single-ended mode
value: 0
- name: Differential
description: Calibration for differential mode
value: 1
enum/ADDISR:
bit_size: 1
variants:
- name: NotDisabling
description: No disable command active
value: 0
- name: Disabling
description: ADC disabling
value: 1
enum/ADDISW:
bit_size: 1
variants:
- name: Disable
description: Disable the ADC
value: 1
enum/ADENR:
bit_size: 1
variants:
- name: Disabled
description: ADC disabled
value: 0
- name: Enabled
description: ADC enabled
value: 1
enum/ADENW:
bit_size: 1
variants:
- name: Enabled
description: Enable the ADC
value: 1
enum/ADRDYIE: enum/ADRDYIE:
bit_size: 1 bit_size: 1
variants: variants:
@ -670,36 +598,6 @@ enum/ADRDYIE:
- name: Enabled - name: Enabled
description: ADC ready interrupt enabled description: ADC ready interrupt enabled
value: 1 value: 1
enum/ADSTARTR:
bit_size: 1
variants:
- name: NotActive
description: No conversion ongoing
value: 0
- name: Active
description: ADC operating and may be converting
value: 1
enum/ADSTARTW:
bit_size: 1
variants:
- name: StartConversion
description: Start the ADC conversion (may be delayed for hardware triggers)
value: 1
enum/ADSTPR:
bit_size: 1
variants:
- name: NotStopping
description: No stop command active
value: 0
- name: Stopping
description: ADC stopping conversion
value: 1
enum/ADSTPW:
bit_size: 1
variants:
- name: StopConversion
description: Stop the active conversion
value: 1
enum/ADVREGEN: enum/ADVREGEN:
bit_size: 2 bit_size: 2
variants: variants:
@ -721,24 +619,6 @@ enum/ALIGN:
- name: Left - name: Left
description: Left alignment description: Left alignment
value: 1 value: 1
enum/AUTDLY:
bit_size: 1
variants:
- name: "Off"
description: Auto delayed conversion mode off
value: 0
- name: "On"
description: Auto delayed conversion mode on
value: 1
enum/AWD1EN:
bit_size: 1
variants:
- name: Disabled
description: Analog watchdog 1 disabled on regular channels
value: 0
- name: Enabled
description: Analog watchdog 1 enabled on regular channels
value: 1
enum/AWD1IE: enum/AWD1IE:
bit_size: 1 bit_size: 1
variants: variants:
@ -757,15 +637,6 @@ enum/AWD1SGL:
- name: Single - name: Single
description: Analog watchdog 1 enabled on single channel selected in AWD1CH description: Analog watchdog 1 enabled on single channel selected in AWD1CH
value: 1 value: 1
enum/CONT:
bit_size: 1
variants:
- name: Single
description: Single conversion mode
value: 0
- name: Continuous
description: Continuous conversion mode
value: 1
enum/DIFSEL_10: enum/DIFSEL_10:
bit_size: 1 bit_size: 1
variants: variants:
@ -775,33 +646,6 @@ enum/DIFSEL_10:
- name: Differential - name: Differential
description: Input channel is configured in differential mode description: Input channel is configured in differential mode
value: 1 value: 1
enum/DISCEN:
bit_size: 1
variants:
- name: Disabled
description: Discontinuous mode on regular channels disabled
value: 0
- name: Enabled
description: Discontinuous mode on regular channels enabled
value: 1
enum/DMACFG:
bit_size: 1
variants:
- name: OneShot
description: DMA One Shot Mode selected
value: 0
- name: Circular
description: DMA circular mode selected
value: 1
enum/DMAEN:
bit_size: 1
variants:
- name: Disabled
description: DMA disabled
value: 0
- name: Enabled
description: DMA enabled
value: 1
enum/EOCIE: enum/EOCIE:
bit_size: 1 bit_size: 1
variants: variants:
@ -889,33 +733,6 @@ enum/EXTSEL:
- name: TIM3_CC4 - name: TIM3_CC4
description: Timer 3 CC4 event description: Timer 3 CC4 event
value: 15 value: 15
enum/JAUTO:
bit_size: 1
variants:
- name: Disabled
description: Automatic injected group conversion disabled
value: 0
- name: Enabled
description: Automatic injected group conversion enabled
value: 1
enum/JAWD1EN:
bit_size: 1
variants:
- name: Disabled
description: Analog watchdog 1 disabled on injected channels
value: 0
- name: Enabled
description: Analog watchdog 1 enabled on injected channels
value: 1
enum/JDISCEN:
bit_size: 1
variants:
- name: Disabled
description: Discontinuous mode on injected channels disabled
value: 0
- name: Enabled
description: Discontinuous mode on injected channels enabled
value: 1
enum/JEOCIE: enum/JEOCIE:
bit_size: 1 bit_size: 1
variants: variants:
@ -1021,15 +838,6 @@ enum/OVRIE:
- name: Enabled - name: Enabled
description: Overrun interrupt enabled description: Overrun interrupt enabled
value: 1 value: 1
enum/OVRMOD:
bit_size: 1
variants:
- name: Preserve
description: Preserve DR register when an overrun is detected
value: 0
- name: Overwrite
description: Overwrite DR register when an overrun is detected
value: 1
enum/RES: enum/RES:
bit_size: 2 bit_size: 2
variants: variants: