rcc: more cleanup

data/registers/rcc_f0.yaml

@@ -1048,7 +1048,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 2
   - name: HSI48
@@ -1075,6 +1075,6 @@ enum/USBSW:
   - name: HSI48
     description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source
     value: 0
-  - name: PLLCLK
+  - name: PLL1_P
     description: PLL clock selected as USB clock source
     value: 1

data/registers/rcc_f1.yaml

@@ -822,7 +822,7 @@ enum/SW:
   - name: HSE
     description: HSE selected as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL selected as system clock
     value: 2
 enum/USBPRE:

data/registers/rcc_f100.yaml

@@ -844,6 +844,6 @@ enum/SW:
   - name: HSE
     description: HSE selected as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL selected as system clock
     value: 2

data/registers/rcc_f2.yaml

@@ -1980,6 +1980,6 @@ enum/SW:
   - name: HSE
     description: HSE selected as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL selected as system clock
     value: 2

data/registers/rcc_f3.yaml

@@ -1238,7 +1238,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 2
 enum/TIMSW:
@@ -1247,7 +1247,7 @@ enum/TIMSW:
   - name: PCLK2
     description: PCLK2 clock (doubled frequency when prescaled)
     value: 0
-  - name: PLL
+  - name: PLL1_P
     description: PLL vco output (running up to 144 MHz)
     value: 1
 enum/USARTSW:

data/registers/rcc_f3_v2.yaml

@@ -1214,7 +1214,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 2
 enum/TIMSW:
@@ -1223,7 +1223,7 @@ enum/TIMSW:
   - name: PCLK2
     description: PCLK2 clock (doubled frequency when prescaled)
     value: 0
-  - name: PLL
+  - name: PLL1_P
     description: PLL vco output (running up to 144 MHz)
     value: 1
 enum/USARTSW:

data/registers/rcc_f4.yaml

@@ -3467,7 +3467,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 2
 enum/TIMPRE:

data/registers/rcc_f410.yaml

@@ -1926,7 +1926,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 2
 enum/TIMPRE:

data/registers/rcc_f7.yaml

@@ -3144,7 +3144,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 1
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 2
 enum/TIMPRE:

data/registers/rcc_g0.yaml

@@ -1848,7 +1848,7 @@ enum/SW:
 enum/TIM15SEL:
   bit_size: 1
   variants:
-  - name: TIMPCLK
+  - name: PCLK1_TIM
     description: TIMPCLK used as TIM15 clock source
     value: 0
   - name: PLL1_Q
@@ -1857,7 +1857,7 @@ enum/TIM15SEL:
 enum/TIM1SEL:
   bit_size: 1
   variants:
-  - name: TIMPCLK
+  - name: PCLK1_TIM
     description: TIMPCLK used as TIM1 clock source
     value: 0
   - name: PLL1_Q

data/registers/rcc_h7.yaml

@@ -3697,7 +3697,7 @@ enum/LPTIM2SEL:
 enum/LPUARTSEL:
   bit_size: 3
   variants:
-  - name: RCC_PCLK_D3
+  - name: PCLK3
     description: rcc_pclk_d3 selected as peripheral clock
     value: 0
   - name: PLL2_Q

data/registers/rcc_h7ab.yaml

@@ -2632,7 +2632,7 @@ enum/LPTIM2SEL:
 enum/LPUARTSEL:
   bit_size: 3
   variants:
-  - name: RCC_PCLK_D3
+  - name: PCLK3
     description: rcc_pclk_d3 selected as peripheral clock
     value: 0
   - name: PLL2_Q

data/registers/rcc_h7rm0433.yaml

@@ -3697,7 +3697,7 @@ enum/LPTIM2SEL:
 enum/LPUARTSEL:
   bit_size: 3
   variants:
-  - name: RCC_PCLK_D3
+  - name: PCLK3
     description: rcc_pclk_d3 selected as peripheral clock
     value: 0
   - name: PLL2_Q

data/registers/rcc_l0.yaml

@@ -1201,7 +1201,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 2
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 3
 enum/UARTSEL:

data/registers/rcc_l0_v2.yaml

@@ -1240,7 +1240,7 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 2
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 3
 enum/UARTSEL:

data/registers/rcc_l1.yaml

@@ -1045,6 +1045,6 @@ enum/SW:
   - name: HSE
     description: HSE oscillator used as system clock
     value: 2
-  - name: PLL
+  - name: PLL1_P
     description: PLL used as system clock
     value: 3

data/registers/rcc_l4.yaml

@@ -2267,7 +2267,7 @@ enum/SW:
   - name: HSE
     description: HSE selected as system clock
     value: 2
-  - name: PLL
+  - name: PLL1_P
     description: PLL selected as system clock
     value: 3
 enum/SWPMI1SEL:

stm32-data-gen/src/rcc.rs

@@ -73,22 +73,17 @@ impl PeripheralToClock {
             "SAI2_EXTCLK",
             "B_0x0",
             "B_0x1",
-            "PLL",
-            "PLLCLK",
-            "RCC_PCLK_D3",
             "I2S_CKIN",
             "DAC_HOLD",
             "DAC_HOLD_2",
-            "TIMPCLK",
             "RTCCLK",
             "RTC_WKUP",
             "DSIPHY",
-            "PLLDSICLK",
         ]);
 
         for (rcc_name, ir) in &registers.registers {
             if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
-                let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = {
+                let rcc_enum_map: HashMap<&String, HashMap<&String, (&String, &Enum)>> = {
                     let rcc_blocks = &ir.blocks.get("RCC").unwrap().items;
 
                     rcc_blocks
@@ -101,10 +96,10 @@ impl PeripheralToClock {
                                     f.fields
                                         .iter()
                                         .filter_map(|f| {
-                                            let enumm = f.enumm.as_ref()?;
+                                            let enumm_name = f.enumm.as_ref()?;
-                                            let enumm = ir.enums.get(enumm)?;
+                                            let enumm = ir.enums.get(enumm_name)?;
 
-                                            Some((&f.name, enumm))
+                                            Some((&f.name, (enumm_name, enumm)))
                                         })
                                         .collect(),
                                 )
@@ -124,7 +119,7 @@ impl PeripheralToClock {
                         _ => return Ok(()),
                     };
 
-                    let enumm = match block_map.get(field) {
+                    let (enumm_name, enumm) = match block_map.get(field) {
                         Some(enumm) => enumm,
                         _ => return Ok(()),
                     };
@@ -135,15 +130,17 @@ impl PeripheralToClock {
 
                             if !allowed_variants.contains(name.as_str()) {
                                 return Err(anyhow!(
-                                    "rcc: prohibited variant name {} for rcc_{}",
+                                    "rcc: prohibited variant name {} in enum {} for rcc_{}",
                                     v.name.as_str(),
+                                    enumm_name,
                                     rcc_name
                                 ));
                             }
                         } else if !allowed_variants.contains(v.name.as_str()) {
                             return Err(anyhow!(
-                                "rcc: prohibited variant name {} for rcc_{}",
+                                "rcc: prohibited variant name {} in enum {} for rcc_{}",
                                 v.name.as_str(),
+                                enumm_name,
                                 rcc_name
                             ));
                         }