From c551c07bf12513dd8346a9fe0bc70cf79f2ea02f Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 13 Nov 2023 01:00:53 +0100 Subject: [PATCH] rcc: consistency fixes. --- data/registers/rcc_l0.yaml | 19 ++++++++----------- data/registers/rcc_l0_v2.yaml | 33 ++++++++++++++++++++------------- data/registers/rcc_l1.yaml | 19 ++++++++----------- data/registers/rcc_l5.yaml | 10 +++++----- stm32-data-gen/src/rcc.rs | 1 + 5 files changed, 42 insertions(+), 40 deletions(-) diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 5967821..e60d4f9 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1057,30 +1057,27 @@ enum/MCOSEL: enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 + - name: Range66K description: range 0 around 65.536 kHz value: 0 - - name: Range1 + - name: Range131K description: range 1 around 131.072 kHz value: 1 - - name: Range2 + - name: Range262K description: range 2 around 262.144 kHz value: 2 - - name: Range3 + - name: Range524K description: range 3 around 524.288 kHz value: 3 - - name: Range4 + - name: Range1M description: range 4 around 1.048 MHz value: 4 - - name: Range5 + - name: Range2M description: range 5 around 2.097 MHz (reset value) value: 5 - - name: Range6 + - name: Range4M description: range 6 around 4.194 MHz value: 6 - - name: Range7 - description: not allowed - value: 7 enum/PLLDIV: bit_size: 2 variants: @@ -1201,7 +1198,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 2 - - name: PLL1_P + - name: PLL1_R description: PLL used as system clock value: 3 enum/UARTSEL: diff --git a/data/registers/rcc_l0_v2.yaml b/data/registers/rcc_l0_v2.yaml index b11b209..1ea6967 100644 --- a/data/registers/rcc_l0_v2.yaml +++ b/data/registers/rcc_l0_v2.yaml @@ -528,10 +528,11 @@ fieldset/CCIPR: bit_offset: 18 bit_size: 2 enum: LPTIMSEL - - name: HSI48MSEL - description: 48 MHz HSI48 clock source selection + - name: CLK48SEL + description: 48 MHz clock source selection bit_offset: 26 bit_size: 1 + enum: CLK48SEL fieldset/CFGR: description: Clock configuration register fields: @@ -976,6 +977,15 @@ fieldset/ICSCR: description: MSI clock trimming bit_offset: 24 bit_size: 8 +enum/CLK48SEL: + bit_size: 1 + variants: + - name: PLL1_VCO_DIV_2 + description: PLL VCO divided by 2 selected + value: 0 + - name: HSI48 + description: HSI48 clock selected + value: 1 enum/HPRE: bit_size: 4 variants: @@ -1096,30 +1106,27 @@ enum/MCOSEL: enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 + - name: Range66K description: range 0 around 65.536 kHz value: 0 - - name: Range1 + - name: Range131K description: range 1 around 131.072 kHz value: 1 - - name: Range2 + - name: Range262K description: range 2 around 262.144 kHz value: 2 - - name: Range3 + - name: Range524K description: range 3 around 524.288 kHz value: 3 - - name: Range4 + - name: Range1M description: range 4 around 1.048 MHz value: 4 - - name: Range5 + - name: Range2M description: range 5 around 2.097 MHz (reset value) value: 5 - - name: Range6 + - name: Range4M description: range 6 around 4.194 MHz value: 6 - - name: Range7 - description: not allowed - value: 7 enum/PLLDIV: bit_size: 2 variants: @@ -1240,7 +1247,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 2 - - name: PLL1_P + - name: PLL1_R description: PLL used as system clock value: 3 enum/UARTSEL: diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index 62f86e7..84fba96 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -910,30 +910,27 @@ enum/MCOSEL: enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 + - name: Range66K description: range 0 around 65.536 kHz value: 0 - - name: Range1 + - name: Range131K description: range 1 around 131.072 kHz value: 1 - - name: Range2 + - name: Range262K description: range 2 around 262.144 kHz value: 2 - - name: Range3 + - name: Range524K description: range 3 around 524.288 kHz value: 3 - - name: Range4 + - name: Range1M description: range 4 around 1.048 MHz value: 4 - - name: Range5 + - name: Range2M description: range 5 around 2.097 MHz (reset value) value: 5 - - name: Range6 + - name: Range4M description: range 6 around 4.194 MHz value: 6 - - name: Range7 - description: not allowed - value: 7 enum/PLLDIV: bit_size: 2 variants: @@ -1045,6 +1042,6 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 2 - - name: PLL1_P + - name: PLL1_R description: PLL used as system clock value: 3 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 050f0b7..56959ec 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -111,10 +111,10 @@ block/RCC: description: APB2SMENR byte_offset: 128 fieldset: APB2SMENR - - name: CCIPR1 - description: CCIPR1 + - name: CCIPR + description: CCIPR byte_offset: 136 - fieldset: CCIPR1 + fieldset: CCIPR - name: BDCR description: BDCR byte_offset: 144 @@ -1319,8 +1319,8 @@ fieldset/BDCR: bit_offset: 25 bit_size: 1 enum: LSCOSEL -fieldset/CCIPR1: - description: CCIPR1 +fieldset/CCIPR: + description: CCIPR fields: - name: USART1SEL description: USART1 clock source selection diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index b0b00f6..7acb049 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -72,6 +72,7 @@ impl PeripheralToClock { "PLL1_P", "PLL1_Q", "PLL1_R", + "PLL1_VCO", // used for L0 USB "PLL2_P", "PLL2_Q", "PLL2_R",