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Merge pull request #95 from bobmcwhirter/weird_u5_headers

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Weird u5 headers
This commit is contained in:
Dario Nieuwenhuis 2021-11-02 17:35:16 +01:00 committed by GitHub
commit c40960c953
8 changed files with 6897 additions and 64 deletions
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1
.gitignore vendored
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@ -2,3 +2,4 @@
/sources /sources
/tmp /tmp
.idea/ .idea/
transform*.yaml

46
d
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@ -14,49 +14,8 @@ shift
case "$CMD" in case "$CMD" in
download-all) download-all)
./d download-mcufinder rm -rf ./sources/
./d download-svd git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
./d download-headers
./d download-cubedb
./d download-cubeprogdb
;;
download-mcufinder)
mkdir -p sources/mcufinder
wget http://stmcufinder.com/API/getFiles.php -O sources/mcufinder/files.json
wget http://stmcufinder.com/API/getMCUsForMCUFinderPC.php -O sources/mcufinder/mcus.json
;;
download-pdf)
jq -r .Files[].URL < sources/mcufinder/files.json | wget -P sources/pdf/ -N -i -
;;
download-svd)
rm -rf ./sources/git/stm32-rs
git clone --depth 1 https://github.com/stm32-rs/stm32-rs.git ./sources/git/stm32-rs
(cd ./sources/git/stm32-rs; make svdformat)
mkdir -p sources/svd
for f in ./sources/git/stm32-rs/svd/*.formatted; do
base=$(basename $f | cut -f 1 -d .)
cp $f sources/svd/$base.svd
done
;;
download-headers)
for f in F0 F1 F2 F3 F4 F7 H7 L0 L1 L4 L5 G0 G4 WB WL; do
rm -rf ./sources/git/STM32Cube$f
git clone --depth 1 https://github.com/STMicroelectronics/STM32Cube$f sources/git/STM32Cube$f
done
rm -rf sources/headers
mkdir -p sources/headers
cp sources/git/STM32Cube*/Drivers/CMSIS/Device/ST/STM32*/Include/*.h sources/headers
rm sources/headers/stm32??xx.h
rm sources/headers/system_*.h
rm sources/headers/partition_*.h
;;
download-cubedb)
rm -rf sources/cubedb
git clone --depth 1 https://github.com/embassy-rs/stm32cube-database.git sources/cubedb
;;
download-cubeprogdb)
rm -rf sources/cubeprogdb
git clone --depth 1 https://github.com/embassy-rs/stm32cubeprog-database.git sources/cubeprogdb
;; ;;
install-chiptool) install-chiptool)
cargo install --git https://github.com/embassy-rs/chiptool cargo install --git https://github.com/embassy-rs/chiptool
@ -86,3 +45,4 @@ case "$CMD" in
echo "unknown command" echo "unknown command"
;; ;;
esac esac

429
data/registers/dbgmcu_u5.yaml Normal file
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@ -0,0 +1,429 @@
---
block/DBGMCU:
description: MCU debug component
items:
- name: IDCODE
description: DBGMCU_IDCODE
byte_offset: 0
access: Read
fieldset: IDCODE
- name: CR
description: "Debug MCU configuration\r register"
byte_offset: 4
fieldset: CR
- name: APB1LFZR
description: "Debug MCU APB1L peripheral freeze\r register"
byte_offset: 8
fieldset: APB1LFZR
- name: APB1HFZR
description: Debug MCU APB1H peripheral freeze register
byte_offset: 12
fieldset: APB1HFZR
- name: APB2FZR
description: Debug MCU APB2 peripheral freeze register
byte_offset: 16
fieldset: APB2FZR
- name: APB3FZR
description: Debug MCU APB3 peripheral freeze register
byte_offset: 20
fieldset: APB3FZR
- name: AHB1FZR
description: Debug MCU AHB1 peripheral freeze register
byte_offset: 32
fieldset: AHB1FZR
- name: AHB3FZR
description: Debug MCU AHB3 peripheral freeze register
byte_offset: 40
fieldset: AHB3FZR
- name: DBGMCU_SR
description: DBGMCU status register
byte_offset: 252
access: Read
fieldset: DBGMCU_SR
- name: DBGMCU_DBG_AUTH_HOST
description: DBGMCU debug host authentication register
byte_offset: 256
access: Read
fieldset: DBGMCU_DBG_AUTH_HOST
- name: DBGMCU_DBG_AUTH_DEVICE
description: DBGMCU debug device authentication register
byte_offset: 260
access: Read
fieldset: DBGMCU_DBG_AUTH_DEVICE
- name: PIDR4
description: Debug MCU CoreSight peripheral identity register 4
byte_offset: 4048
access: Read
fieldset: PIDR4
- name: PIDR0
description: Debug MCU CoreSight peripheral identity register 0
byte_offset: 4064
access: Read
fieldset: PIDR0
- name: PIDR1
description: Debug MCU CoreSight peripheral identity register 1
byte_offset: 4068
access: Read
fieldset: PIDR1
- name: PIDR2
description: Debug MCU CoreSight peripheral identity register 2
byte_offset: 4072
access: Read
fieldset: PIDR2
- name: PIDR3
description: Debug MCU CoreSight peripheral identity register 3
byte_offset: 4076
access: Read
fieldset: PIDR3
- name: CIDR0
description: Debug MCU CoreSight component identity register 0
byte_offset: 4080
access: Read
fieldset: CIDR0
- name: CIDR1
description: Debug MCU CoreSight component identity register 1
byte_offset: 4084
access: Read
fieldset: CIDR1
- name: CIDR2
description: Debug MCU CoreSight component identity register 2
byte_offset: 4088
access: Read
fieldset: CIDR2
- name: CIDR3
description: Debug MCU CoreSight component identity register 3
byte_offset: 4092
access: Read
fieldset: CIDR3
fieldset/AHB1FZR:
description: Debug MCU AHB1 peripheral freeze register
fields:
- name: DBG_GPDMA0_STOP
description: GPDMA channel 0 stop in debug
bit_offset: 0
bit_size: 1
- name: DBG_GPDMA1_STOP
description: GPDMA channel 1 stop in debug
bit_offset: 1
bit_size: 1
- name: DBG_GPDMA2_STOP
description: GPDMA channel 2 stop in debug
bit_offset: 2
bit_size: 1
- name: DBG_GPDMA3_STOP
description: GPDMA channel 3 stop in debug
bit_offset: 3
bit_size: 1
- name: DBG_GPDMA4_STOP
description: GPDMA channel 4 stop in debug
bit_offset: 4
bit_size: 1
- name: DBG_GPDMA5_STOP
description: GPDMA channel 5 stop in debug
bit_offset: 5
bit_size: 1
- name: DBG_GPDMA6_STOP
description: GPDMA channel 6 stop in debug
bit_offset: 6
bit_size: 1
- name: DBG_GPDMA7_STOP
description: GPDMA channel 7 stop in debug
bit_offset: 7
bit_size: 1
- name: DBG_GPDMA8_STOP
description: GPDMA channel 8 stop in debug
bit_offset: 8
bit_size: 1
- name: DBG_GPDMA9_STOP
description: GPDMA channel 9 stop in debug
bit_offset: 9
bit_size: 1
- name: DBG_GPDMA10_STOP
description: GPDMA channel 10 stop in debug
bit_offset: 10
bit_size: 1
- name: DBG_GPDMA11_STOP
description: GPDMA channel 11 stop in debug
bit_offset: 11
bit_size: 1
- name: DBG_GPDMA12_STOP
description: GPDMA channel 12 stop in debug
bit_offset: 12
bit_size: 1
- name: DBG_GPDMA13_STOP
description: GPDMA channel 13 stop in debug
bit_offset: 13
bit_size: 1
- name: DBG_GPDMA14_STOP
description: GPDMA channel 14 stop in debug
bit_offset: 14
bit_size: 1
- name: DBG_GPDMA15_STOP
description: GPDMA channel 15 stop in debug
bit_offset: 15
bit_size: 1
fieldset/AHB3FZR:
description: Debug MCU AHB3 peripheral freeze register
fields:
- name: DBG_LPDMA0_STOP
description: LPDMA channel 0 stop in debug
bit_offset: 0
bit_size: 1
- name: DBG_LPDMA1_STOP
description: LPDMA channel 1 stop in debug
bit_offset: 1
bit_size: 1
- name: DBG_LPDMA2_STOP
description: LPDMA channel 2 stop in debug
bit_offset: 2
bit_size: 1
- name: DBG_LPDMA3_STOP
description: LPDMA channel 3 stop in debug
bit_offset: 3
bit_size: 1
fieldset/APB1HFZR:
description: Debug MCU APB1H peripheral freeze register
fields:
- name: DBG_I2C4_STOP
description: I2C4 stop in debug
bit_offset: 1
bit_size: 1
- name: DBG_LPTIM2_STOP
description: LPTIM2 stop in debug
bit_offset: 5
bit_size: 1
fieldset/APB1LFZR:
description: "Debug MCU APB1L peripheral freeze\r register"
fields:
- name: DBG_TIM2_STOP
description: TIM2 stop in debug
bit_offset: 0
bit_size: 1
- name: DBG_TIM3_STOP
description: TIM3 stop in debug
bit_offset: 1
bit_size: 1
- name: DBG_TIM4_STOP
description: TIM4 stop in debug
bit_offset: 2
bit_size: 1
- name: DBG_TIM5_STOP
description: TIM5 stop in debug
bit_offset: 3
bit_size: 1
- name: DBG_TIM6_STOP
description: TIM6 stop in debug
bit_offset: 4
bit_size: 1
- name: DBG_TIM7_STOP
description: TIM7 stop in debug
bit_offset: 5
bit_size: 1
- name: DBG_WWDG_STOP
description: Window watchdog counter stop in debug
bit_offset: 11
bit_size: 1
- name: DBG_IWDG_STOP
description: Independent watchdog counter stop in debug
bit_offset: 12
bit_size: 1
- name: DBG_I2C1_STOP
description: I2C1 SMBUS timeout stop in debug
bit_offset: 21
bit_size: 1
- name: DBG_I2C2_STOP
description: I2C2 SMBUS timeout stop in debug
bit_offset: 22
bit_size: 1
fieldset/APB2FZR:
description: Debug MCU APB2 peripheral freeze register
fields:
- name: DBG_TIM1_STOP
description: "TIM1 counter stopped when core is\r halted"
bit_offset: 11
bit_size: 1
- name: DBG_TIM8_STOP
description: TIM8 stop in debug
bit_offset: 13
bit_size: 1
- name: DBG_TIM15_STOP
description: "TIM15 counter stopped when core is\r halted"
bit_offset: 16
bit_size: 1
- name: DBG_TIM16_STOP
description: "TIM16 counter stopped when core is\r halted"
bit_offset: 17
bit_size: 1
- name: DBG_TIM17_STOP
description: DBG_TIM17_STOP
bit_offset: 18
bit_size: 1
fieldset/APB3FZR:
description: Debug MCU APB3 peripheral freeze register
fields:
- name: DBG_I2C3_STOP
description: I2C3 stop in debug
bit_offset: 10
bit_size: 1
- name: DBG_LPTIM1_STOP
description: LPTIM1 stop in debug
bit_offset: 17
bit_size: 1
- name: DBG_LPTIM3_STOP
description: LPTIM3 stop in debug
bit_offset: 18
bit_size: 1
- name: DBG_LPTIM4_STOP
description: LPTIM4 stop in debug
bit_offset: 19
bit_size: 1
- name: DBG_RTC_STOP
description: RTC stop in debug
bit_offset: 30
bit_size: 1
fieldset/CIDR0:
description: Debug MCU CoreSight component identity register 0
fields:
- name: PREAMBLE
description: "component identification bits [7:0]"
bit_offset: 0
bit_size: 8
fieldset/CIDR1:
description: Debug MCU CoreSight component identity register 1
fields:
- name: PREAMBLE
description: "component identification bits [11:8]"
bit_offset: 0
bit_size: 4
- name: CLASS
description: "component identification bits [15:12] - component class"
bit_offset: 4
bit_size: 4
fieldset/CIDR2:
description: Debug MCU CoreSight component identity register 2
fields:
- name: PREAMBLE
description: "component identification bits [23:16]"
bit_offset: 0
bit_size: 8
fieldset/CIDR3:
description: Debug MCU CoreSight component identity register 3
fields:
- name: PREAMBLE
description: "component identification bits [31:24]"
bit_offset: 0
bit_size: 8
fieldset/CR:
description: "Debug MCU configuration\r register"
fields:
- name: DBG_STOP
description: Debug Stop mode
bit_offset: 1
bit_size: 1
- name: DBG_STANDBY
description: Debug Standby mode
bit_offset: 2
bit_size: 1
- name: TRACE_IOEN
description: "Trace pin assignment\r control"
bit_offset: 4
bit_size: 1
- name: TRACE_EN
description: "trace port and clock\r enable"
bit_offset: 5
bit_size: 1
- name: TRACE_MODE
description: "Trace pin assignment\r control"
bit_offset: 6
bit_size: 2
fieldset/DBGMCU_DBG_AUTH_DEVICE:
description: DBGMCU debug device authentication register
fields:
- name: AUTH_ID
description: "Device specific ID\r \tDevice specific ID used for RDP regression."
bit_offset: 0
bit_size: 32
fieldset/DBGMCU_DBG_AUTH_HOST:
description: DBGMCU debug host authentication register
fields:
- name: AUTH_KEY
description: "Device authentication key\r \tThe device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory."
bit_offset: 0
bit_size: 32
fieldset/DBGMCU_SR:
description: DBGMCU status register
fields:
- name: AP_PRESENT
description: "Bit n identifies whether access port AP n is present in device\r \tBit n = 0: APn absent\r \tBit n = 1: APn present"
bit_offset: 0
bit_size: 8
- name: AP_LOCKED
description: "DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)\r \tBit n = 0: APn locked\r \tBit n = 1: APn enabled"
bit_offset: 8
bit_size: 8
fieldset/IDCODE:
description: DBGMCU_IDCODE
fields:
- name: DEV_ID
description: Device dentification
bit_offset: 0
bit_size: 12
- name: REV_ID
description: Revision
bit_offset: 16
bit_size: 16
fieldset/PIDR0:
description: Debug MCU CoreSight peripheral identity register 0
fields:
- name: PARTNUM
description: "part number bits [7:0]"
bit_offset: 0
bit_size: 8
fieldset/PIDR1:
description: Debug MCU CoreSight peripheral identity register 1
fields:
- name: PARTNUM
description: "part number bits [11:8]"
bit_offset: 0
bit_size: 4
- name: JEP106ID
description: "JEP106 identity code bits [3:0]"
bit_offset: 4
bit_size: 4
fieldset/PIDR2:
description: Debug MCU CoreSight peripheral identity register 2
fields:
- name: JEP106ID
description: "JEP106 identity code bits [6:4]"
bit_offset: 0
bit_size: 3
- name: JEDEC
description: JEDEC assigned value
bit_offset: 3
bit_size: 1
- name: REVISION
description: component revision number
bit_offset: 4
bit_size: 4
fieldset/PIDR3:
description: Debug MCU CoreSight peripheral identity register 3
fields:
- name: CMOD
description: customer modified
bit_offset: 0
bit_size: 4
- name: REVAND
description: metal fix version
bit_offset: 4
bit_size: 4
fieldset/PIDR4:
description: Debug MCU CoreSight peripheral identity register 4
fields:
- name: JEP106CON
description: JEP106 continuation code
bit_offset: 0
bit_size: 4
- name: KCOUNT_4
description: register file size
bit_offset: 4
bit_size: 4

125
data/registers/exti_u5.yaml Normal file
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@ -0,0 +1,125 @@
---
block/EXTI:
description: External interrupt/event controller
items:
- name: RTSR
description: Rising Trigger selection register
array:
len: 2
stride: 32
byte_offset: 0
fieldset: LINES
- name: FTSR
description: Falling Trigger selection register
array:
len: 2
stride: 32
byte_offset: 4
fieldset: LINES
- name: SWIER
description: Software interrupt event register
array:
len: 2
stride: 32
byte_offset: 8
fieldset: LINES
- name: RPR
description: Rising pending register
array:
len: 2
stride: 32
byte_offset: 12
fieldset: LINES
- name: FPR
description: Falling pending register
array:
len: 2
stride: 32
byte_offset: 16
fieldset: LINES
- name: SECCFGR
description: Security configuration register
array:
len: 2
stride: 36
byte_offset: 20
fieldset: SECCFGR
- name: PRIVCFGR
description: Privilege configuration register
array:
len: 2
stride: 28
byte_offset: 24
fieldset: PRIVCFGR
- name: EXTICR
description: Configuration register
array:
len: 4
stride: 4
byte_offset: 96
fieldset: EXTICR
- name: LOCKRG
description: EXTI lock register
byte_offset: 112
fieldset: LOCKRG
- name: IMR
description: Interrupt mask register
array:
len: 2
stride: 16
byte_offset: 128
fieldset: LINES
- name: EMR
description: Event mask register
array:
len: 2
stride: 16
byte_offset: 132
fieldset: LINES
fieldset/EXTICR:
description: external interrupt configuration register 1
fields:
- name: EXTI
description: EXTI configuration bits
bit_offset: 0
bit_size: 8
array:
len: 4
stride: 8
fieldset/LINES:
description: EXTI lines register, 1 bit per line
fields:
- name: LINE
description: EXTI line
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
fieldset/LOCKRG:
description: EXTI lock register
fields:
- name: LOCK
description: LOCK
bit_offset: 0
bit_size: 1
fieldset/PRIVCFGR:
description: Privilege configuration register
fields:
- name: PRIV
description: Security enable on event input x
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
fieldset/SECCFGR:
description: Security configuration register
fields:
- name: SEC
description: Security enable on event input x
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1

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data/registers/pwr_u5.yaml Normal file
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data/registers/rcc_u5.yaml Normal file
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data/registers/syscfg_u5.yaml Normal file
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@ -0,0 +1,241 @@
---
block/SYSCFG:
description: System configuration controller
items:
- name: SECCFGR
description: "SYSCFG secure configuration\r register"
byte_offset: 0
fieldset: SECCFGR
- name: CFGR1
description: configuration register 1
byte_offset: 4
fieldset: CFGR1
- name: FPUIMR
description: FPU interrupt mask register
byte_offset: 8
fieldset: FPUIMR
- name: CNSLCKR
description: "SYSCFG CPU non-secure lock\r register"
byte_offset: 12
fieldset: CNSLCKR
- name: CSLOCKR
description: "SYSCFG CPU secure lock\r register"
byte_offset: 16
fieldset: CSLOCKR
- name: CFGR2
description: configuration register 2
byte_offset: 20
fieldset: CFGR2
- name: MESR
description: memory erase status register
byte_offset: 24
fieldset: MESR
- name: CCCSR
description: compensation cell control/status register
byte_offset: 28
fieldset: CCCSR
- name: CCVR
description: compensation cell value register
byte_offset: 32
access: Read
fieldset: CCVR
- name: CCCR
description: compensation cell code register
byte_offset: 36
fieldset: CCCR
- name: RSSCMDR
description: RSS command register
byte_offset: 44
fieldset: RSSCMDR
- name: UCPDR
description: USB Type C and Power Delivery register
byte_offset: 112
fieldset: UCPDR
fieldset/CCCR:
description: compensation cell code register
fields:
- name: NCC1
description: NCC1
bit_offset: 0
bit_size: 4
- name: PCC1
description: PCC1
bit_offset: 4
bit_size: 4
- name: NCC2
description: NCC2
bit_offset: 8
bit_size: 4
- name: PCC2
description: PCC2
bit_offset: 12
bit_size: 4
fieldset/CCCSR:
description: compensation cell control/status register
fields:
- name: EN1
description: EN1
bit_offset: 0
bit_size: 1
- name: CS1
description: CS1
bit_offset: 1
bit_size: 1
- name: EN2
description: EN2
bit_offset: 2
bit_size: 1
- name: CS2
description: CS2
bit_offset: 3
bit_size: 1
- name: RDY1
description: RDY1
bit_offset: 8
bit_size: 1
- name: RDY2
description: RDY2
bit_offset: 9
bit_size: 1
fieldset/CCVR:
description: compensation cell value register
fields:
- name: NCV1
description: NCV1
bit_offset: 0
bit_size: 4
- name: PCV1
description: PCV1
bit_offset: 4
bit_size: 4
- name: NCV2
description: NCV2
bit_offset: 8
bit_size: 4
- name: PCV2
description: PCV2
bit_offset: 12
bit_size: 4
fieldset/CFGR1:
description: configuration register 1
fields:
- name: BOOSTEN
description: "I/O analog switch voltage booster\r enable"
bit_offset: 8
bit_size: 1
- name: ANASWVDD
description: "GPIO analog switch control voltage\r selection"
bit_offset: 9
bit_size: 1
- name: PB6_FMP
description: PB6_FMP
bit_offset: 16
bit_size: 1
- name: PB7_FMP
description: PB7_FMP
bit_offset: 17
bit_size: 1
- name: PB8_FMP
description: PB8_FMP
bit_offset: 18
bit_size: 1
- name: PB9_FMP
description: PB9_FMP
bit_offset: 19
bit_size: 1
fieldset/CFGR2:
description: configuration register 2
fields:
- name: CLL
description: "LOCKUP (hardfault) output enable\r bit"
bit_offset: 0
bit_size: 1
- name: SPL
description: SRAM ECC lock bit
bit_offset: 1
bit_size: 1
- name: PVDL
description: PVD lock enable bit
bit_offset: 2
bit_size: 1
- name: ECCL
description: ECC Lock
bit_offset: 3
bit_size: 1
fieldset/CNSLCKR:
description: "SYSCFG CPU non-secure lock\r register"
fields:
- name: LOCKNSVTOR
description: VTOR_NS register lock
bit_offset: 0
bit_size: 1
- name: LOCKNSMPU
description: "Non-secure MPU registers\r lock"
bit_offset: 1
bit_size: 1
fieldset/CSLOCKR:
description: "SYSCFG CPU secure lock\r register"
fields:
- name: LOCKSVTAIRCR
description: LOCKSVTAIRCR
bit_offset: 0
bit_size: 1
- name: LOCKSMPU
description: LOCKSMPU
bit_offset: 1
bit_size: 1
- name: LOCKSAU
description: LOCKSAU
bit_offset: 2
bit_size: 1
fieldset/FPUIMR:
description: FPU interrupt mask register
fields:
- name: FPU_IE
description: "Floating point unit interrupts enable\r bits"
bit_offset: 0
bit_size: 6
fieldset/MESR:
description: memory erase status register
fields:
- name: MCLR
description: MCLR
bit_offset: 0
bit_size: 1
- name: IPMEE
description: IPMEE
bit_offset: 16
bit_size: 1
fieldset/RSSCMDR:
description: RSS command register
fields:
- name: RSSCMD
description: RSS commands
bit_offset: 0
bit_size: 16
fieldset/SECCFGR:
description: "SYSCFG secure configuration\r register"
fields:
- name: SYSCFGSEC
description: "SYSCFG clock control\r security"
bit_offset: 0
bit_size: 1
- name: CLASSBSEC
description: CLASSBSEC
bit_offset: 1
bit_size: 1
- name: FPUSEC
description: FPUSEC
bit_offset: 3
bit_size: 1
fieldset/UCPDR:
description: USB Type C and Power Delivery register
fields:
- name: CC1ENRXFILTER
description: CC1ENRXFILTER
bit_offset: 0
bit_size: 1
- name: CC2ENRXFILTER
description: CC2ENRXFILTER
bit_offset: 1
bit_size: 1

49
parse.py
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@ -148,6 +148,8 @@ def parse_value(val, defines):
val = val.strip() val = val.strip()
if val == '': if val == '':
return 0 return 0
if m := re.match('(0([1-9][0-9]*)(U))', val):
return int(m.group(2), 10)
if m := re.match('((0x[0-9a-fA-F]+|\\d+))(|u|ul|U|UL)$', val): if m := re.match('((0x[0-9a-fA-F]+|\\d+))(|u|ul|U|UL)$', val):
return int(m.group(1), 0) return int(m.group(1), 0)
if m := re.match('([0-9A-Za-z_]+)$', val): if m := re.match('([0-9A-Za-z_]+)$', val):
@ -159,6 +161,8 @@ def parse_value(val, defines):
return parse_value(m.group(1), defines) return parse_value(m.group(1), defines)
# if m := re.match('\\*?\\(u?int(8|16|32|64)_t\\ *)(.*)$', val): # if m := re.match('\\*?\\(u?int(8|16|32|64)_t\\ *)(.*)$', val):
# return parse_value(m.group(1), defines) # return parse_value(m.group(1), defines)
if m := re.match('(.*)/(.*)$', val):
return parse_value(m.group(1), defines) / parse_value(m.group(2), defines)
if m := re.match('(.*)<<(.*)$', val): if m := re.match('(.*)<<(.*)$', val):
return (parse_value(m.group(1), defines) << parse_value(m.group(2), defines)) & 0xFFFFFFFF return (parse_value(m.group(1), defines) << parse_value(m.group(2), defines)) & 0xFFFFFFFF
if m := re.match('(.*)>>(.*)$', val): if m := re.match('(.*)>>(.*)$', val):
@ -350,15 +354,16 @@ perimap = [
('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'), ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'), ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
('.*:DCMI:cci_v2_0', 'dcmi_v1/DCMI'), ('.*:DCMI:cci_v2_0', 'dcmi_v1/DCMI'),
('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'), ('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'),
('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
('STM32F7.*:SYS:.*', 'syscfg_f7/SYSCFG'), ('STM32F7.*:SYS:.*', 'syscfg_f7/SYSCFG'),
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
('STM32L1.*:SYS:.*', 'syscfg_l1/SYSCFG'), ('STM32L1.*:SYS:.*', 'syscfg_l1/SYSCFG'),
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'), ('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'), ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
('STM32WB.*:SYS:.*', 'syscfg_wb/SYSCFG'), ('STM32U5.*:SYS:.*', 'syscfg_u5/SYSCFG'),
('STM32WB.*:SYS:.*', 'syscfg_wb/SYSCFG'),
('STM32WL5.*:SYS:.*', 'syscfg_wl5/SYSCFG'), ('STM32WL5.*:SYS:.*', 'syscfg_wl5/SYSCFG'),
('STM32WLE.*:SYS:.*', 'syscfg_wle/SYSCFG'), ('STM32WLE.*:SYS:.*', 'syscfg_wle/SYSCFG'),
@ -392,6 +397,7 @@ perimap = [
('STM32L1.*:RCC:.*', 'rcc_l1/RCC'), ('STM32L1.*:RCC:.*', 'rcc_l1/RCC'),
('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
('STM32L5.*:RCC:.*', 'rcc_l5/RCC'), ('STM32L5.*:RCC:.*', 'rcc_l5/RCC'),
('STM32U5.*:RCC:.*', 'rcc_u5/RCC'),
('STM32WB.*:RCC:.*', 'rcc_wb/RCC'), ('STM32WB.*:RCC:.*', 'rcc_wb/RCC'),
('STM32WL5.*:RCC:.*', 'rcc_wl5/RCC'), ('STM32WL5.*:RCC:.*', 'rcc_wl5/RCC'),
('STM32WLE.*:RCC:.*', 'rcc_wle/RCC'), ('STM32WLE.*:RCC:.*', 'rcc_wle/RCC'),
@ -401,6 +407,7 @@ perimap = [
('STM32L5.*:EXTI:.*', 'exti_l5/EXTI'), ('STM32L5.*:EXTI:.*', 'exti_l5/EXTI'),
('STM32G0.*:EXTI:.*', 'exti_g0/EXTI'), ('STM32G0.*:EXTI:.*', 'exti_g0/EXTI'),
('STM32H7.*:EXTI:.*', 'exti_h7/EXTI'), ('STM32H7.*:EXTI:.*', 'exti_h7/EXTI'),
('STM32U5.*:EXTI:.*', 'exti_u5/EXTI'),
('STM32WB.*:EXTI:.*', 'exti_w/EXTI'), ('STM32WB.*:EXTI:.*', 'exti_w/EXTI'),
('STM32WL5.*:EXTI:.*', 'exti_w/EXTI'), ('STM32WL5.*:EXTI:.*', 'exti_w/EXTI'),
('STM32WLE.*:EXTI:.*', 'exti_wle/EXTI'), ('STM32WLE.*:EXTI:.*', 'exti_wle/EXTI'),
@ -414,6 +421,7 @@ perimap = [
('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'), ('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),
('.*:STM32F7_pwr_v1_0', 'pwr_f7/PWR'), ('.*:STM32F7_pwr_v1_0', 'pwr_f7/PWR'),
('.*:STM32L1_pwr_v1_0', 'pwr_l1/PWR'), ('.*:STM32L1_pwr_v1_0', 'pwr_l1/PWR'),
('.*:STM32U5_pwr_v1_0', 'pwr_u5/PWR'),
('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'), ('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'),
('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'), ('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'),
@ -442,6 +450,7 @@ perimap = [
('.*:STM32L0_dbgmcu_v1_0', 'dbgmcu_l0/DBGMCU'), ('.*:STM32L0_dbgmcu_v1_0', 'dbgmcu_l0/DBGMCU'),
('.*:STM32L1_dbgmcu_v1_0', 'dbgmcu_l1/DBGMCU'), ('.*:STM32L1_dbgmcu_v1_0', 'dbgmcu_l1/DBGMCU'),
('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'), ('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'),
('.*:STM32U5_dbgmcu_v1_0', 'dbgmcu_u5/DBGMCU'),
('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'), ('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'),
('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'), ('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'),
@ -581,6 +590,7 @@ def chip_name_from_package_name(x):
('(STM32L5....).x[PQ]', '\\1'), ('(STM32L5....).x[PQ]', '\\1'),
('(STM32L0....).xS', '\\1'), ('(STM32L0....).xS', '\\1'),
('(STM32H7....).xQ', '\\1'), ('(STM32H7....).xQ', '\\1'),
('(STM32U5....).xQ', '\\1'),
('(STM32......).x', '\\1'), ('(STM32......).x', '\\1'),
] ]
@ -1070,16 +1080,17 @@ def parse_chips():
core['dma_channels'] = chs core['dma_channels'] = chs
# Process peripheral - DMA channel associations # Process peripheral - DMA channel associations
for pname, p in peris.items(): if chip_dma is not None:
if (peri_chs := dma_channels[chip_dma]['peripherals'].get(pname)) is not None: for pname, p in peris.items():
p['dma_channels'] = { if (peri_chs := dma_channels[chip_dma]['peripherals'].get(pname)) is not None:
req: [ p['dma_channels'] = {
ch req: [
for ch in req_chs ch
if ('channel' not in ch) or ch['channel'] in chs for ch in req_chs
] if ('channel' not in ch) or ch['channel'] in chs
for req, req_chs in peri_chs.items() ]
} for req, req_chs in peri_chs.items()
}
# remove all pins from the root of the chip before emitting. # remove all pins from the root of the chip before emitting.
del chip['pins'] del chip['pins']