From c25b401647255a60450b147a8dd3a4401a3951ec Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 23:40:12 +0800 Subject: [PATCH] extract lptim_v2a from l5 --- data/registers/lptim_v2a.yaml | 280 ++++++++++++++++++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 data/registers/lptim_v2a.yaml diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml new file mode 100644 index 0000000..1ef25d7 --- /dev/null +++ b/data/registers/lptim_v2a.yaml @@ -0,0 +1,280 @@ +block/LPTIM1: + description: Low power timer. + items: + - name: ISR + description: Interrupt and Status Register. + byte_offset: 0 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register. + byte_offset: 4 + access: Write + fieldset: ICR + - name: IER + description: Interrupt Enable Register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: Configuration Register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: Control Register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: Compare Register. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: Autoreload Register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: Counter Register. + byte_offset: 28 + access: Read + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 + fieldset: OR + - name: RCR + description: LPTIM repetition register. + byte_offset: 40 + fieldset: RCR +fieldset/ARR: + description: Autoreload Register. + fields: + - name: ARR + description: Auto reload value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: Configuration Register. + fields: + - name: CKSEL + description: Clock selector. + bit_offset: 0 + bit_size: 1 + - name: CKPOL + description: Clock Polarity. + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: Configurable digital filter for external clock. + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: Configurable digital filter for trigger. + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: Clock prescaler. + bit_offset: 9 + bit_size: 3 + - name: TRIGSEL + description: Trigger selector. + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity. + bit_offset: 17 + bit_size: 2 + - name: TIMOUT + description: Timeout enable. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: Waveform shape polarity. + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: Registers update mode. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled. + bit_offset: 23 + bit_size: 1 + - name: ENC + description: Encoder mode enable. + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: Compare Register. + fields: + - name: CMP + description: Compare value. + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: Counter Register. + fields: + - name: CNT + description: Counter value. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: Control Register. + fields: + - name: ENABLE + description: LPTIM Enable. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in single mode. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in continuous mode. + bit_offset: 2 + bit_size: 1 + - name: RSTARE + description: Reset after read enable. + bit_offset: 3 + bit_size: 1 + - name: COUNTRST + description: Counter reset. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: Interrupt Clear Register. + fields: + - name: CMPMCF + description: compare match Clear Flag. + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match Clear Flag. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge Clear Flag. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register update OK Clear Flag. + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK Clear Flag. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: Direction change to UP Clear Flag. + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: Direction change to down Clear Flag. + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag. + bit_offset: 8 + bit_size: 1 +fieldset/IER: + description: Interrupt Enable Register. + fields: + - name: CMPMIE + description: Compare match Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register update OK Interrupt Enable. + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: Direction change to UP Interrupt Enable. + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: Direction change to down Interrupt Enable. + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: REPOKIE. + bit_offset: 8 + bit_size: 1 +fieldset/ISR: + description: Interrupt and Status Register. + fields: + - name: CMPM + description: Compare match. + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register update OK. + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK. + bit_offset: 4 + bit_size: 1 + - name: UP + description: Counter direction change down to up. + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: Counter direction change up to down. + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update Ok. + bit_offset: 8 + bit_size: 1 +fieldset/OR: + description: LPTIM option register. + fields: + - name: OR_0 + description: Option register bit 0. + bit_offset: 0 + bit_size: 1 + - name: OR_1 + description: Option register bit 1. + bit_offset: 1 + bit_size: 1 +fieldset/RCR: + description: LPTIM repetition register. + fields: + - name: REP + description: Repetition register value. + bit_offset: 0 + bit_size: 8