Split f410 and f4 RCC yamls

f410 has the RNGEN at a different position

data/registers/rcc_f4.yaml

@@ -740,33 +740,6 @@ enum/PLLP:
   - description: PLLP=8
     name: Div8
     value: 3
-enum/PLLRDYFR:
-  bit_size: 1
-  variants:
-  - description: No clock ready interrupt
-    name: NotInterrupted
-    value: 0
-  - description: Clock ready interrupt
-    name: Interrupted
-    value: 1
-enum/PLLRDYIE:
-  bit_size: 1
-  variants:
-  - description: Interrupt disabled
-    name: Disabled
-    value: 0
-  - description: Interrupt enabled
-    name: Enabled
-    value: 1
-enum/PLLRDYR:
-  bit_size: 1
-  variants:
-  - description: Clock not ready
-    name: NotReady
-    value: 0
-  - description: Clock ready
-    name: Ready
-    value: 1
 enum/PLLSAIDIVQ:
   bit_size: 5
   variants:

parse.py

@@ -319,6 +319,7 @@ perimap = [
     ('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
     ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
     ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
+    ('STM32F410.*:RCC:.*', 'rcc_f410/RCC'),
     ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
     ('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'),
     ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),