diff --git a/data/extra/family/STM32L4+.yaml b/data/extra/family/STM32L4+.yaml
new file mode 100644
index 0000000..a72291a
--- /dev/null
+++ b/data/extra/family/STM32L4+.yaml
@@ -0,0 +1,4 @@
+peripherals:
+    VREFINTCAL: 
+        address: 0x1FFF75AA
+        block: vrefintcal_v1/VREFINTCAL
diff --git a/data/registers/adc_v3.yaml b/data/registers/adc_v3.yaml
new file mode 100644
index 0000000..1b77899
--- /dev/null
+++ b/data/registers/adc_v3.yaml
@@ -0,0 +1,675 @@
+---
+block/ADC:
+  description: Analog-to-Digital Converter
+  items:
+    - name: ISR
+      description: interrupt and status register
+      byte_offset: 0
+      fieldset: ISR
+    - name: IER
+      description: interrupt enable register
+      byte_offset: 4
+      fieldset: IER
+    - name: CR
+      description: control register
+      byte_offset: 8
+      fieldset: CR
+    - name: CFGR
+      description: configuration register
+      byte_offset: 12
+      fieldset: CFGR
+    - name: CFGR2
+      description: configuration register
+      byte_offset: 16
+      fieldset: CFGR2
+    - name: SMPR1
+      description: sample time register 1
+      byte_offset: 20
+      fieldset: SMPR1
+    - name: SMPR2
+      description: sample time register 2
+      byte_offset: 24
+      fieldset: SMPR2
+    - name: TR1
+      description: watchdog threshold register 1
+      byte_offset: 32
+      fieldset: TR1
+    - name: TR2
+      description: watchdog threshold register
+      byte_offset: 36
+      fieldset: TR2
+    - name: TR3
+      description: watchdog threshold register 3
+      byte_offset: 40
+      fieldset: TR3
+    - name: SQR1
+      description: regular sequence register 1
+      byte_offset: 48
+      fieldset: SQR1
+    - name: SQR2
+      description: regular sequence register 2
+      byte_offset: 52
+      fieldset: SQR2
+    - name: SQR3
+      description: regular sequence register 3
+      byte_offset: 56
+      fieldset: SQR3
+    - name: SQR4
+      description: regular sequence register 4
+      byte_offset: 60
+      fieldset: SQR4
+    - name: DR
+      description: regular Data Register
+      byte_offset: 64
+      access: Read
+      fieldset: DR
+    - name: JSQR
+      description: injected sequence register
+      byte_offset: 76
+      fieldset: JSQR
+    - name: OFR
+      description: offset register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 96
+      fieldset: OFR1
+    - name: JDR
+      description: injected data register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 128
+      access: Read
+      fieldset: JDR1
+    - name: AWD2CR
+      description: Analog Watchdog 2 Configuration Register
+      byte_offset: 160
+      fieldset: AWD2CR
+    - name: AWD3CR
+      description: Analog Watchdog 3 Configuration Register
+      byte_offset: 164
+      fieldset: AWD3CR
+    - name: DIFSEL
+      description: Differential Mode Selection Register 2
+      byte_offset: 176
+      fieldset: DIFSEL
+    - name: CALFACT
+      description: Calibration Factors
+      byte_offset: 180
+      fieldset: CALFACT
+fieldset/AWD2CR:
+  description: Analog Watchdog 2 Configuration Register
+  fields:
+    - name: AWD2CH
+      description: AWD2CH
+      bit_offset: 1
+      bit_size: 18
+fieldset/AWD3CR:
+  description: Analog Watchdog 3 Configuration Register
+  fields:
+    - name: AWD3CH
+      description: AWD3CH
+      bit_offset: 1
+      bit_size: 18
+fieldset/CALFACT:
+  description: Calibration Factors
+  fields:
+    - name: CALFACT_S
+      description: CALFACT_S
+      bit_offset: 0
+      bit_size: 7
+    - name: CALFACT_D
+      description: CALFACT_D
+      bit_offset: 16
+      bit_size: 7
+fieldset/CFGR:
+  description: configuration register
+  fields:
+    - name: DMAEN
+      description: DMAEN
+      bit_offset: 0
+      bit_size: 1
+    - name: DMACFG
+      description: DMACFG
+      bit_offset: 1
+      bit_size: 1
+    - name: RES
+      description: RES
+      bit_offset: 3
+      bit_size: 2
+      enum: RES
+    - name: ALIGN
+      description: ALIGN
+      bit_offset: 5
+      bit_size: 1
+    - name: EXTSEL
+      description: EXTSEL
+      bit_offset: 6
+      bit_size: 4
+    - name: EXTEN
+      description: EXTEN
+      bit_offset: 10
+      bit_size: 2
+    - name: OVRMOD
+      description: OVRMOD
+      bit_offset: 12
+      bit_size: 1
+    - name: CONT
+      description: CONT
+      bit_offset: 13
+      bit_size: 1
+    - name: AUTDLY
+      description: AUTDLY
+      bit_offset: 14
+      bit_size: 1
+    - name: AUTOFF
+      description: AUTOFF
+      bit_offset: 15
+      bit_size: 1
+    - name: DISCEN
+      description: DISCEN
+      bit_offset: 16
+      bit_size: 1
+    - name: DISCNUM
+      description: DISCNUM
+      bit_offset: 17
+      bit_size: 3
+    - name: JDISCEN
+      description: JDISCEN
+      bit_offset: 20
+      bit_size: 1
+    - name: JQM
+      description: JQM
+      bit_offset: 21
+      bit_size: 1
+    - name: AWD1SGL
+      description: AWD1SGL
+      bit_offset: 22
+      bit_size: 1
+    - name: AWD1EN
+      description: AWD1EN
+      bit_offset: 23
+      bit_size: 1
+    - name: JAWD1EN
+      description: JAWD1EN
+      bit_offset: 24
+      bit_size: 1
+    - name: JAUTO
+      description: JAUTO
+      bit_offset: 25
+      bit_size: 1
+    - name: AWDCH1CH
+      description: AWDCH1CH
+      bit_offset: 26
+      bit_size: 5
+fieldset/CFGR2:
+  description: configuration register
+  fields:
+    - name: ROVSE
+      description: DMAEN
+      bit_offset: 0
+      bit_size: 1
+    - name: JOVSE
+      description: DMACFG
+      bit_offset: 1
+      bit_size: 1
+    - name: OVSR
+      description: RES
+      bit_offset: 2
+      bit_size: 3
+    - name: OVSS
+      description: ALIGN
+      bit_offset: 5
+      bit_size: 4
+    - name: TOVS
+      description: EXTSEL
+      bit_offset: 9
+      bit_size: 1
+    - name: ROVSM
+      description: EXTEN
+      bit_offset: 10
+      bit_size: 1
+fieldset/CR:
+  description: control register
+  fields:
+    - name: ADEN
+      description: ADEN
+      bit_offset: 0
+      bit_size: 1
+    - name: ADDIS
+      description: ADDIS
+      bit_offset: 1
+      bit_size: 1
+    - name: ADSTART
+      description: ADSTART
+      bit_offset: 2
+      bit_size: 1
+    - name: JADSTART
+      description: JADSTART
+      bit_offset: 3
+      bit_size: 1
+    - name: ADSTP
+      description: ADSTP
+      bit_offset: 4
+      bit_size: 1
+    - name: JADSTP
+      description: JADSTP
+      bit_offset: 5
+      bit_size: 1
+    - name: ADVREGEN
+      description: ADVREGEN
+      bit_offset: 28
+      bit_size: 1
+    - name: DEEPPWD
+      description: DEEPPWD
+      bit_offset: 29
+      bit_size: 1
+    - name: ADCALDIF
+      description: ADCALDIF
+      bit_offset: 30
+      bit_size: 1
+    - name: ADCAL
+      description: ADCAL
+      bit_offset: 31
+      bit_size: 1
+fieldset/DIFSEL:
+  description: Differential Mode Selection Register 2
+  fields:
+    - name: DIFSEL_1_15
+      description: Differential mode for channels 15 to 1
+      bit_offset: 1
+      bit_size: 15
+    - name: DIFSEL_16_18
+      description: Differential mode for channels 18 to 16
+      bit_offset: 16
+      bit_size: 3
+fieldset/DR:
+  description: regular Data Register
+  fields:
+    - name: regularDATA
+      description: regularDATA
+      bit_offset: 0
+      bit_size: 16
+fieldset/IER:
+  description: interrupt enable register
+  fields:
+    - name: ADRDYIE
+      description: ADRDYIE
+      bit_offset: 0
+      bit_size: 1
+    - name: EOSMPIE
+      description: EOSMPIE
+      bit_offset: 1
+      bit_size: 1
+    - name: EOCIE
+      description: EOCIE
+      bit_offset: 2
+      bit_size: 1
+    - name: EOSIE
+      description: EOSIE
+      bit_offset: 3
+      bit_size: 1
+    - name: OVRIE
+      description: OVRIE
+      bit_offset: 4
+      bit_size: 1
+    - name: JEOCIE
+      description: JEOCIE
+      bit_offset: 5
+      bit_size: 1
+    - name: JEOSIE
+      description: JEOSIE
+      bit_offset: 6
+      bit_size: 1
+    - name: AWD1IE
+      description: AWD1IE
+      bit_offset: 7
+      bit_size: 1
+    - name: AWD2IE
+      description: AWD2IE
+      bit_offset: 8
+      bit_size: 1
+    - name: AWD3IE
+      description: AWD3IE
+      bit_offset: 9
+      bit_size: 1
+    - name: JQOVFIE
+      description: JQOVFIE
+      bit_offset: 10
+      bit_size: 1
+fieldset/ISR:
+  description: interrupt and status register
+  fields:
+    - name: ADRDY
+      description: ADRDY
+      bit_offset: 0
+      bit_size: 1
+    - name: EOSMP
+      description: EOSMP
+      bit_offset: 1
+      bit_size: 1
+    - name: EOC
+      description: EOC
+      bit_offset: 2
+      bit_size: 1
+    - name: EOS
+      description: EOS
+      bit_offset: 3
+      bit_size: 1
+    - name: OVR
+      description: OVR
+      bit_offset: 4
+      bit_size: 1
+    - name: JEOC
+      description: JEOC
+      bit_offset: 5
+      bit_size: 1
+    - name: JEOS
+      description: JEOS
+      bit_offset: 6
+      bit_size: 1
+    - name: AWD
+      description: AWD1
+      bit_offset: 7
+      bit_size: 1
+      array:
+        len: 3
+        stride: 1
+    - name: JQOVF
+      description: JQOVF
+      bit_offset: 10
+      bit_size: 1
+fieldset/JDR1:
+  description: injected data register 1
+  fields:
+    - name: JDATA
+      description: JDATA1
+      bit_offset: 0
+      bit_size: 16
+      array:
+        len: 1
+        stride: 0
+fieldset/JDR2:
+  description: injected data register 2
+  fields:
+    - name: JDATA
+      description: JDATA2
+      bit_offset: 0
+      bit_size: 16
+      array:
+        len: 1
+        stride: 0
+fieldset/JDR3:
+  description: injected data register 3
+  fields:
+    - name: JDATA
+      description: JDATA3
+      bit_offset: 0
+      bit_size: 16
+      array:
+        len: 1
+        stride: 0
+fieldset/JDR4:
+  description: injected data register 4
+  fields:
+    - name: JDATA
+      description: JDATA4
+      bit_offset: 0
+      bit_size: 16
+      array:
+        len: 1
+        stride: 0
+fieldset/JSQR:
+  description: injected sequence register
+  fields:
+    - name: JL
+      description: JL
+      bit_offset: 0
+      bit_size: 2
+    - name: JEXTSEL
+      description: JEXTSEL
+      bit_offset: 2
+      bit_size: 4
+    - name: JEXTEN
+      description: JEXTEN
+      bit_offset: 6
+      bit_size: 2
+    - name: JSQ
+      description: JSQ1
+      bit_offset: 8
+      bit_size: 5
+      array:
+        len: 4
+        stride: 6
+fieldset/OFR1:
+  description: offset register 1
+  fields:
+    - name: OFFSET
+      description: OFFSET1
+      bit_offset: 0
+      bit_size: 12
+      array:
+        len: 1
+        stride: 0
+    - name: OFFSET1_CH
+      description: OFFSET1_CH
+      bit_offset: 26
+      bit_size: 5
+    - name: OFFSET1_EN
+      description: OFFSET1_EN
+      bit_offset: 31
+      bit_size: 1
+fieldset/OFR2:
+  description: offset register 2
+  fields:
+    - name: OFFSET
+      description: OFFSET2
+      bit_offset: 0
+      bit_size: 12
+      array:
+        len: 1
+        stride: 0
+    - name: OFFSET2_CH
+      description: OFFSET2_CH
+      bit_offset: 26
+      bit_size: 5
+    - name: OFFSET2_EN
+      description: OFFSET2_EN
+      bit_offset: 31
+      bit_size: 1
+fieldset/OFR3:
+  description: offset register 3
+  fields:
+    - name: OFFSET
+      description: OFFSET3
+      bit_offset: 0
+      bit_size: 12
+      array:
+        len: 1
+        stride: 0
+    - name: OFFSET3_CH
+      description: OFFSET3_CH
+      bit_offset: 26
+      bit_size: 5
+    - name: OFFSET3_EN
+      description: OFFSET3_EN
+      bit_offset: 31
+      bit_size: 1
+fieldset/OFR4:
+  description: offset register 4
+  fields:
+    - name: OFFSET
+      description: OFFSET4
+      bit_offset: 0
+      bit_size: 12
+      array:
+        len: 1
+        stride: 0
+    - name: OFFSET4_CH
+      description: OFFSET4_CH
+      bit_offset: 26
+      bit_size: 5
+    - name: OFFSET4_EN
+      description: OFFSET4_EN
+      bit_offset: 31
+      bit_size: 1
+fieldset/SMPR1:
+  description: sample time register 1
+  fields:
+    - name: SMP
+      description: Channel 0 sampling time selection
+      bit_offset: 0
+      bit_size: 3
+      enum: SAMPLE_TIME
+      array:
+        len: 10
+        stride: 3
+fieldset/SMPR2:
+  description: sample time register 2
+  fields:
+    - name: SMP
+      description: Channel 10 sampling time selection
+      bit_offset: 0
+      bit_size: 3
+      enum: SAMPLE_TIME
+      array:
+        len: 9
+        stride: 3
+fieldset/SQR1:
+  description: regular sequence register 1
+  fields:
+    - name: L
+      description: Regular channel sequence length
+      bit_offset: 0
+      bit_size: 4
+    - name: SQ
+      description: SQ1
+      bit_offset: 6
+      bit_size: 5
+      array:
+        len: 4
+        stride: 6
+fieldset/SQR2:
+  description: regular sequence register 2
+  fields:
+    - name: SQ
+      description: SQ5
+      bit_offset: 0
+      bit_size: 5
+      array:
+        len: 5
+        stride: 6
+fieldset/SQR3:
+  description: regular sequence register 3
+  fields:
+    - name: SQ
+      description: SQ10
+      bit_offset: 0
+      bit_size: 5
+      array:
+        len: 5
+        stride: 6
+fieldset/SQR4:
+  description: regular sequence register 4
+  fields:
+    - name: SQ
+      description: SQ15
+      bit_offset: 0
+      bit_size: 5
+      array:
+        len: 2
+        stride: 6
+fieldset/TR1:
+  description: watchdog threshold register 1
+  fields:
+    - name: LT
+      description: LT1
+      bit_offset: 0
+      bit_size: 12
+      array:
+        len: 1
+        stride: 0
+    - name: HT
+      description: HT1
+      bit_offset: 16
+      bit_size: 12
+      array:
+        len: 1
+        stride: 0
+fieldset/TR2:
+  description: watchdog threshold register
+  fields:
+    - name: LT
+      description: LT2
+      bit_offset: 0
+      bit_size: 8
+      array:
+        len: 1
+        stride: 0
+    - name: HT
+      description: HT2
+      bit_offset: 16
+      bit_size: 8
+      array:
+        len: 1
+        stride: 0
+fieldset/TR3:
+  description: watchdog threshold register 3
+  fields:
+    - name: LT
+      description: LT3
+      bit_offset: 0
+      bit_size: 8
+      array:
+        len: 1
+        stride: 0
+    - name: HT
+      description: HT3
+      bit_offset: 16
+      bit_size: 8
+      array:
+        len: 1
+        stride: 0
+enum/SAMPLE_TIME:
+  bit_size: 3
+  variants:
+    - name: Cycles2_5
+      description: 2.5 ADC cycles
+      value: 0
+    - name: Cycles6_5
+      description: 6.5 ADC cycles
+      value: 1
+    - name: Cycles12_5
+      description: 12.5 ADC cycles
+      value: 2
+    - name: Cycles24_5
+      description: 24.5 ADC cycles
+      value: 3
+    - name: Cycles47_5
+      description: 47.5 ADC cycles
+      value: 4
+    - name: Cycles92_5
+      description: 92.5 ADC cycles
+      value: 5
+    - name: Cycles247_5
+      description: 247.5 ADC cycles
+      value: 6
+    - name: Cycles640_5
+      description: 640.5 ADC cycles
+      value: 7
+enum/RES:
+  bit_size: 2
+  variants:
+    - name: TwelveBit
+      description: 12-bit resolution
+      value: 0
+    - name: TenBit
+      description: 10-bit resolution
+      value: 1
+    - name: EightBit
+      description: 8-bit resolution
+      value: 2
+    - name: SixBit
+      description: 6-bit resolution
+      value: 3
diff --git a/data/registers/adccommon_v3.yaml b/data/registers/adccommon_v3.yaml
new file mode 100644
index 0000000..e9ae7b0
--- /dev/null
+++ b/data/registers/adccommon_v3.yaml
@@ -0,0 +1,155 @@
+---
+block/ADC_COMMON:
+  description: Analog-to-Digital Converter
+  items:
+    - name: CSR
+      description: ADC Common status register
+      byte_offset: 0
+      access: Read
+      fieldset: CSR
+    - name: CCR
+      description: ADC common control register
+      byte_offset: 8
+      fieldset: CCR
+    - name: CDR
+      description: ADC common regular data register for dual and triple modes
+      byte_offset: 12
+      access: Read
+      fieldset: CDR
+fieldset/CCR:
+  description: ADC common control register
+  fields:
+    - name: MULT
+      description: Multi ADC mode selection
+      bit_offset: 0
+      bit_size: 5
+    - name: DELAY
+      description: Delay between 2 sampling phases
+      bit_offset: 8
+      bit_size: 4
+    - name: DMACFG
+      description: DMA configuration (for multi-ADC mode)
+      bit_offset: 13
+      bit_size: 1
+    - name: MDMA
+      description: Direct memory access mode for multi ADC mode
+      bit_offset: 14
+      bit_size: 2
+    - name: CKMODE
+      description: ADC clock mode
+      bit_offset: 16
+      bit_size: 2
+    - name: VREFEN
+      description: VREFINT enable
+      bit_offset: 22
+      bit_size: 1
+    - name: CH18SEL
+      description: CH18 selection (Vbat)
+      bit_offset: 23
+      bit_size: 1
+    - name: CH17SEL
+      description: CH17 selection (temperature)
+      bit_offset: 24
+      bit_size: 1
+fieldset/CDR:
+  description: ADC common regular data register for dual and triple modes
+  fields:
+    - name: RDATA_MST
+      description: Regular data of the master ADC
+      bit_offset: 0
+      bit_size: 16
+    - name: RDATA_SLV
+      description: Regular data of the slave ADC
+      bit_offset: 16
+      bit_size: 16
+fieldset/CSR:
+  description: ADC Common status register
+  fields:
+    - name: ADDRDY_MST
+      description: ADDRDY_MST
+      bit_offset: 0
+      bit_size: 1
+    - name: EOSMP_MST
+      description: EOSMP_MST
+      bit_offset: 1
+      bit_size: 1
+    - name: EOC_MST
+      description: EOC_MST
+      bit_offset: 2
+      bit_size: 1
+    - name: EOS_MST
+      description: EOS_MST
+      bit_offset: 3
+      bit_size: 1
+    - name: OVR_MST
+      description: OVR_MST
+      bit_offset: 4
+      bit_size: 1
+    - name: JEOC_MST
+      description: JEOC_MST
+      bit_offset: 5
+      bit_size: 1
+    - name: JEOS_MST
+      description: JEOS_MST
+      bit_offset: 6
+      bit_size: 1
+    - name: AWD1_MST
+      description: AWD1_MST
+      bit_offset: 7
+      bit_size: 1
+    - name: AWD2_MST
+      description: AWD2_MST
+      bit_offset: 8
+      bit_size: 1
+    - name: AWD3_MST
+      description: AWD3_MST
+      bit_offset: 9
+      bit_size: 1
+    - name: JQOVF_MST
+      description: JQOVF_MST
+      bit_offset: 10
+      bit_size: 1
+    - name: ADRDY_SLV
+      description: ADRDY_SLV
+      bit_offset: 16
+      bit_size: 1
+    - name: EOSMP_SLV
+      description: EOSMP_SLV
+      bit_offset: 17
+      bit_size: 1
+    - name: EOC_SLV
+      description: End of regular conversion of the slave ADC
+      bit_offset: 18
+      bit_size: 1
+    - name: EOS_SLV
+      description: End of regular sequence flag of the slave ADC
+      bit_offset: 19
+      bit_size: 1
+    - name: OVR_SLV
+      description: Overrun flag of the slave ADC
+      bit_offset: 20
+      bit_size: 1
+    - name: JEOC_SLV
+      description: End of injected conversion flag of the slave ADC
+      bit_offset: 21
+      bit_size: 1
+    - name: JEOS_SLV
+      description: End of injected sequence flag of the slave ADC
+      bit_offset: 22
+      bit_size: 1
+    - name: AWD1_SLV
+      description: Analog watchdog 1 flag of the slave ADC
+      bit_offset: 23
+      bit_size: 1
+    - name: AWD2_SLV
+      description: Analog watchdog 2 flag of the slave ADC
+      bit_offset: 24
+      bit_size: 1
+    - name: AWD3_SLV
+      description: Analog watchdog 3 flag of the slave ADC
+      bit_offset: 25
+      bit_size: 1
+    - name: JQOVF_SLV
+      description: Injected Context Queue Overflow flag of the slave ADC
+      bit_offset: 26
+      bit_size: 1
diff --git a/data/registers/vrefintcal_v1.yaml b/data/registers/vrefintcal_v1.yaml
new file mode 100644
index 0000000..3b27b74
--- /dev/null
+++ b/data/registers/vrefintcal_v1.yaml
@@ -0,0 +1,16 @@
+---
+block/VREFINTCAL:
+  description: VREFINT Factory Calibration
+  items:
+    - name: DATA
+      description: Factory calibration
+      byte_offset: 0
+      access: Read
+      fieldset: DATA
+fieldset/DATA:
+  description: Factory calibration data
+  fields:
+    - name: VALUE
+      description: Calibration value
+      bit_offset: 0
+      bit_size: 16
diff --git a/parse.py b/parse.py
index 9014f11..8c6e072 100644
--- a/parse.py
+++ b/parse.py
@@ -238,6 +238,8 @@ perimap = [
     ('.*:I2C:i2c2_v1_1F7', 'i2c_v2/I2C'),
     ('.*:DAC:dacif_v2_0', 'dac_v2/DAC'),
     ('.*:DAC:dacif_v3_0', 'dac_v2/DAC'),
+    ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
+    ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
     ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
     ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
     ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
@@ -360,6 +362,8 @@ def parse_chips():
             rcc = removesuffix(rcc, '_rcc_v1_0')
 
             core = r['Core']
+            family = r['@Family']
+
             # multicores have a list here. Just keep the first, to not break the schema.
             if isinstance(core, list):
                 core = core[0]
@@ -367,7 +371,7 @@ def parse_chips():
             if chip_name not in chips:
                 chips[chip_name] = OrderedDict({
                     'name': chip_name,
-                    'family': r['@Family'],
+                    'family': family,
                     'line': r['@Line'],
                     'core': core,
                     'flash': flash,
@@ -386,10 +390,12 @@ def parse_chips():
                 'package': r['@Package'],
             }))
 
+
             # Some packages have some peripehrals removed because the package had to
             # remove GPIOs useful for that peripheral. So we merge all peripherals from all packages.
             peris = chips[chip_name]['peripherals']
             pins = chips[chip_name]['pins']
+
             for ip in r['IP']:
                 pname = ip['@InstanceName']
                 pkind = ip['@Name']+':'+ip['@Version']
@@ -399,6 +405,9 @@ def parse_chips():
                     pname = 'SYSCFG'
                 if pname in FAKE_PERIPHERALS:
                     continue
+                if pname.startswith('ADC'):
+                    if not pname + '_COMMON' in peris:
+                        peris[pname + '_COMMON'] = ip['@Name'] + '_COMMON:'+removesuffix(ip['@Version'], '_Cube')
                 peris[pname] = pkind
                 pins[pname] = []
 
@@ -476,6 +485,13 @@ def parse_chips():
 
             peris[pname] = p
 
+        family_extra = "data/extra/family/" + chip['family'] + ".yaml";
+        if os.path.exists(family_extra) :
+            with open(family_extra) as extra_f:
+                extra = yaml.load(extra_f, Loader=yaml.SafeLoader)
+                for (extra_name, extra_p) in extra['peripherals'].items():
+                    peris[extra_name] = extra_p
+
         # Handle GPIO specially.
         for p in range(20):
             port = 'GPIO' + chr(ord('A')+p)