Dario Nieuwenhuis
GitHub
commit
bd402a58f2
26
README.md
26
README.md
@ -42,4 +42,28 @@ This generates all the YAMLs in `data/` except those in `data/registers/`, which
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## Extracting new register blocks
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TODO document
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For instance, to add support for the G0 series first download all the source
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SVDs:
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```
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$ ./d download-all
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```
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Now extract the RCC peripheral registers:
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```
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./d install-chiptool
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./d extract-all RCC --transform ./transform-RCC.yaml
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```
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Note that we have used a transform to mechanically clean up some of the RCC
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definitions. This will produce a YAML file for each chip model in `./tmp/RCC`
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At this point we need to choose the model with the largest peripheral set (e.g.
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the STM32G081) and compare its YAML against each of the other models' to verify
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that they are all mutually consistent.
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Finally, we can merge
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```
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./merge_regs.py tmp/RCC/g0*.yaml
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```
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This will produce `regs_merged.yaml`, which we can copy into its final resting
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place:
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```
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mv regs_merged.yaml data/registers/rcc_g0.yaml
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```
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196
data/registers/exti_g0.yaml
Normal file
196
data/registers/exti_g0.yaml
Normal file
@ -0,0 +1,196 @@
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---
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block/EXTI:
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description: External interrupt/event controller
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items:
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- name: RTSR
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description: Rising Trigger selection register (EXTI_RTSR)
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byte_offset: 0
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reset_value: 0
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fieldset: RTSR
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array:
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len: 2
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stride: 40
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- name: FTSR
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description: Falling Trigger selection register (EXTI_FTSR)
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byte_offset: 4
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reset_value: 0
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fieldset: FTSR
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array:
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len: 2
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stride: 40
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- name: SWIER
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description: Software interrupt event register (EXTI_SWIER)
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byte_offset: 8
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reset_value: 0
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fieldset: SWIER
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array:
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len: 2
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stride: 40
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- name: RPR
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description: Rising pending register (EXTI_RPR)
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byte_offset: 12
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reset_value: 0
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fieldset: RPR
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array:
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len: 2
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stride: 40
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- name: FPR
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description: Falling pending register (EXTI_FPR)
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byte_offset: 16
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reset_value: 0
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fieldset: FPR
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array:
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len: 2
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stride: 40
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- name: EXTICR
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description: external interrupt configuration register
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array:
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len: 4
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stride: 4
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byte_offset: 96
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fieldset: EXTICR
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- name: IMR
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description: internal interrupt configuration register 1
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array:
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len: 2
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stride: 16
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byte_offset: 128
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fieldset: IMR
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- name: EMR
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description: external interrupt configuration register 1
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array:
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len: 2
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stride: 16
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byte_offset: 132
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fieldset: EMR
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fieldset/EMR:
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description: Event mask register (EXTI_EMR)
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fields:
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- name: MR
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description: Event Mask on line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: MR
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fieldset/FPR:
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description: Falling Trigger pending register (EXTI_FPR)
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fields:
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- name: FPIF
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description: Falling edge event pending for line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: PRR
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fieldset/FTSR:
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description: Falling Trigger selection register (EXTI_FTSR)
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fields:
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- name: TR
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description: Falling trigger event configuration of line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: TR
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fieldset/IMR:
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description: Interrupt mask register (EXTI_IMR)
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fields:
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- name: MR
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description: Interrupt Mask on line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: MR
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fieldset/RPR:
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description: Rising Trigger pending register (EXTI_RPR)
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fields:
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- name: RPIF
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description: Rising edge event pending for line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: PRR
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fieldset/RTSR:
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description: Rising Trigger selection register (EXTI_RTSR)
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fields:
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- name: TR
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description: Rising trigger event configuration of line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: TR
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fieldset/SWIER:
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description: Software interrupt event register (EXTI_SWIER)
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fields:
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- name: SWIER
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description: Software Interrupt on line 0
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum_write: SWIERW
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fieldset/EXTICR:
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description: external interrupt configuration register 1
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fields:
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- name: EXTI
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description: EXTI configuration bits
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bit_offset: 0
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bit_size: 4
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array:
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len: 4
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stride: 4
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enum/MR:
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bit_size: 1
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variants:
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- name: Masked
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description: Interrupt request line is masked
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value: 0
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- name: Unmasked
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description: Interrupt request line is unmasked
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value: 1
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enum/TR:
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bit_size: 1
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variants:
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- name: Disabled
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description: Falling edge trigger is disabled
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value: 0
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- name: Enabled
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description: Falling edge trigger is enabled
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value: 1
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enum/PRR:
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bit_size: 1
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variants:
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- name: NotPending
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description: No trigger request occurred
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value: 0
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- name: Pending
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description: Selected trigger request occurred
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value: 1
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enum/PRW:
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bit_size: 1
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variants:
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- name: Clear
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description: Clears pending bit
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value: 1
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enum/SWIERW:
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bit_size: 1
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variants:
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- name: Pend
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description: Generates an interrupt request
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value: 1
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955
data/registers/rcc_g0.yaml
Normal file
955
data/registers/rcc_g0.yaml
Normal file
@ -0,0 +1,955 @@
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block/RCC:
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description: Reset and clock control
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items:
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- byte_offset: 0
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description: Clock control register
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fieldset: CR
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name: CR
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- byte_offset: 4
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description: Internal clock sources calibration register
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fieldset: ICSCR
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name: ICSCR
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- byte_offset: 8
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description: Clock configuration register
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fieldset: CFGR
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name: CFGR
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- byte_offset: 12
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description: PLL configuration register
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fieldset: PLLSYSCFGR
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name: PLLSYSCFGR
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- byte_offset: 24
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description: Clock interrupt enable register
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fieldset: CIER
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name: CIER
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- access: Read
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byte_offset: 28
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description: Clock interrupt flag register
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fieldset: CIFR
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name: CIFR
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- access: Write
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byte_offset: 32
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description: Clock interrupt clear register
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fieldset: CICR
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name: CICR
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- byte_offset: 36
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description: GPIO reset register
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fieldset: IOPRSTR
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name: IOPRSTR
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- byte_offset: 40
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description: AHB peripheral reset register
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fieldset: AHBRSTR
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name: AHBRSTR
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- byte_offset: 44
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description: APB peripheral reset register 1
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fieldset: APBRSTR1
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name: APBRSTR1
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- byte_offset: 48
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description: APB peripheral reset register 2
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fieldset: APBRSTR2
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name: APBRSTR2
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- byte_offset: 52
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description: GPIO clock enable register
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fieldset: IOPENR
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name: IOPENR
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- byte_offset: 56
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description: AHB peripheral clock enable register
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fieldset: AHBENR
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name: AHBENR
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- byte_offset: 60
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description: APB peripheral clock enable register 1
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fieldset: APBENR1
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name: APBENR1
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- byte_offset: 64
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description: APB peripheral clock enable register 2
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fieldset: APBENR2
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name: APBENR2
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- byte_offset: 68
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description: GPIO in Sleep mode clock enable register
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fieldset: IOPSMENR
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name: IOPSMENR
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- byte_offset: 72
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description: AHB peripheral clock enable in Sleep mode register
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fieldset: AHBSMENR
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name: AHBSMENR
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- byte_offset: 76
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description: APB peripheral clock enable in Sleep mode register 1
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fieldset: APBSMENR1
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name: APBSMENR1
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- byte_offset: 80
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description: APB peripheral clock enable in Sleep mode register 2
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fieldset: APBSMENR2
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name: APBSMENR2
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- byte_offset: 84
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description: Peripherals independent clock configuration register
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fieldset: CCIPR
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name: CCIPR
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- byte_offset: 92
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description: RTC domain control register
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fieldset: BDCR
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name: BDCR
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- byte_offset: 96
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description: Control/status register
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fieldset: CSR
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name: CSR
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fieldset/AHBENR:
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description: AHB peripheral clock enable register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA clock enable
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name: DMAEN
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- bit_offset: 8
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bit_size: 1
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description: Flash memory interface clock enable
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name: FLASHEN
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- bit_offset: 12
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bit_size: 1
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description: CRC clock enable
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name: CRCEN
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- bit_offset: 16
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bit_size: 1
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description: AES hardware accelerator
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name: AESEN
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- bit_offset: 18
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bit_size: 1
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description: Random number generator clock enable
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name: RNGEN
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fieldset/AHBRSTR:
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description: AHB peripheral reset register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1 reset
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name: DMARST
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- bit_offset: 8
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bit_size: 1
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description: FLITF reset
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name: FLASHRST
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- bit_offset: 12
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bit_size: 1
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description: CRC reset
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name: CRCRST
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- bit_offset: 16
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bit_size: 1
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description: AES hardware accelerator reset
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name: AESRST
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- bit_offset: 18
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bit_size: 1
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description: Random number generator reset
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name: RNGRST
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fieldset/AHBSMENR:
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description: AHB peripheral clock enable in Sleep mode register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA clock enable during Sleep mode
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name: DMASMEN
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- bit_offset: 8
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bit_size: 1
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description: Flash memory interface clock enable during Sleep mode
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name: FLASHSMEN
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- bit_offset: 9
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bit_size: 1
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description: SRAM clock enable during Sleep mode
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name: SRAMSMEN
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- bit_offset: 12
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bit_size: 1
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description: CRC clock enable during Sleep mode
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name: CRCSMEN
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- bit_offset: 16
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bit_size: 1
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description: AES hardware accelerator clock enable during Sleep mode
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name: AESSMEN
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- bit_offset: 18
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bit_size: 1
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description: Random number generator clock enable during Sleep mode
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name: RNGSMEN
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fieldset/APBENR1:
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description: APB peripheral clock enable register 1
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fields:
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- bit_offset: 0
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bit_size: 1
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description: TIM2 timer clock enable
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name: TIM2EN
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- bit_offset: 1
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bit_size: 1
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description: TIM3 timer clock enable
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name: TIM3EN
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- bit_offset: 4
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bit_size: 1
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description: TIM6 timer clock enable
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name: TIM6EN
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- bit_offset: 5
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bit_size: 1
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description: TIM7 timer clock enable
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name: TIM7EN
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- bit_offset: 10
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bit_size: 1
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description: RTC APB clock enable
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name: RTCAPBEN
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- bit_offset: 11
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bit_size: 1
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description: WWDG clock enable
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name: WWDGEN
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- bit_offset: 14
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bit_size: 1
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description: SPI2 clock enable
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name: SPI2EN
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- bit_offset: 17
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bit_size: 1
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description: USART2 clock enable
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name: USART2EN
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- bit_offset: 18
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bit_size: 1
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description: USART3 clock enable
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name: USART3EN
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- bit_offset: 19
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bit_size: 1
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description: USART4 clock enable
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name: USART4EN
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- bit_offset: 20
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bit_size: 1
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description: LPUART1 clock enable
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name: LPUART1EN
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- bit_offset: 21
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bit_size: 1
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description: I2C1 clock enable
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name: I2C1EN
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- bit_offset: 22
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bit_size: 1
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description: I2C2 clock enable
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name: I2C2EN
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- bit_offset: 24
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bit_size: 1
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description: HDMI CEC clock enable
|
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name: CECEN
|
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- bit_offset: 25
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bit_size: 1
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description: UCPD1 clock enable
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name: UCPD1EN
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- bit_offset: 26
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bit_size: 1
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description: UCPD2 clock enable
|
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name: UCPD2EN
|
||||
- bit_offset: 27
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bit_size: 1
|
||||
description: Debug support clock enable
|
||||
name: DBGEN
|
||||
- bit_offset: 28
|
||||
bit_size: 1
|
||||
description: Power interface clock enable
|
||||
name: PWREN
|
||||
- bit_offset: 29
|
||||
bit_size: 1
|
||||
description: DAC1 interface clock enable
|
||||
name: DAC1EN
|
||||
- bit_offset: 30
|
||||
bit_size: 1
|
||||
description: LPTIM2 clock enable
|
||||
name: LPTIM2EN
|
||||
- bit_offset: 31
|
||||
bit_size: 1
|
||||
description: LPTIM1 clock enable
|
||||
name: LPTIM1EN
|
||||
fieldset/APBENR2:
|
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description: APB peripheral clock enable register 2
|
||||
fields:
|
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- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SYSCFG, COMP and VREFBUF clock enable
|
||||
name: SYSCFGEN
|
||||
- bit_offset: 11
|
||||
bit_size: 1
|
||||
description: TIM1 timer clock enable
|
||||
name: TIM1EN
|
||||
- bit_offset: 12
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||||
bit_size: 1
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||||
description: SPI1 clock enable
|
||||
name: SPI1EN
|
||||
- bit_offset: 14
|
||||
bit_size: 1
|
||||
description: USART1 clock enable
|
||||
name: USART1EN
|
||||
- bit_offset: 15
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||||
bit_size: 1
|
||||
description: TIM14 timer clock enable
|
||||
name: TIM14EN
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: TIM15 timer clock enable
|
||||
name: TIM15EN
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: TIM16 timer clock enable
|
||||
name: TIM16EN
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: TIM16 timer clock enable
|
||||
name: TIM17EN
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: ADC clock enable
|
||||
name: ADCEN
|
||||
fieldset/APBRSTR1:
|
||||
description: APB peripheral reset register 1
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM2 timer reset
|
||||
name: TIM2RST
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: TIM3 timer reset
|
||||
name: TIM3RST
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: TIM6 timer reset
|
||||
name: TIM6RST
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: TIM7 timer reset
|
||||
name: TIM7RST
|
||||
- bit_offset: 14
|
||||
bit_size: 1
|
||||
description: SPI2 reset
|
||||
name: SPI2RST
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: USART2 reset
|
||||
name: USART2RST
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: USART3 reset
|
||||
name: USART3RST
|
||||
- bit_offset: 19
|
||||
bit_size: 1
|
||||
description: USART4 reset
|
||||
name: USART4RST
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: LPUART1 reset
|
||||
name: LPUART1RST
|
||||
- bit_offset: 21
|
||||
bit_size: 1
|
||||
description: I2C1 reset
|
||||
name: I2C1RST
|
||||
- bit_offset: 22
|
||||
bit_size: 1
|
||||
description: I2C2 reset
|
||||
name: I2C2RST
|
||||
- bit_offset: 24
|
||||
bit_size: 1
|
||||
description: HDMI CEC reset
|
||||
name: CECRST
|
||||
- bit_offset: 25
|
||||
bit_size: 1
|
||||
description: UCPD1 reset
|
||||
name: UCPD1RST
|
||||
- bit_offset: 26
|
||||
bit_size: 1
|
||||
description: UCPD2 reset
|
||||
name: UCPD2RST
|
||||
- bit_offset: 27
|
||||
bit_size: 1
|
||||
description: Debug support reset
|
||||
name: DBGRST
|
||||
- bit_offset: 28
|
||||
bit_size: 1
|
||||
description: Power interface reset
|
||||
name: PWRRST
|
||||
- bit_offset: 29
|
||||
bit_size: 1
|
||||
description: DAC1 interface reset
|
||||
name: DAC1RST
|
||||
- bit_offset: 30
|
||||
bit_size: 1
|
||||
description: Low Power Timer 2 reset
|
||||
name: LPTIM2RST
|
||||
- bit_offset: 31
|
||||
bit_size: 1
|
||||
description: Low Power Timer 1 reset
|
||||
name: LPTIM1RST
|
||||
fieldset/APBRSTR2:
|
||||
description: APB peripheral reset register 2
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SYSCFG, COMP and VREFBUF reset
|
||||
name: SYSCFGRST
|
||||
- bit_offset: 11
|
||||
bit_size: 1
|
||||
description: TIM1 timer reset
|
||||
name: TIM1RST
|
||||
- bit_offset: 12
|
||||
bit_size: 1
|
||||
description: SPI1 reset
|
||||
name: SPI1RST
|
||||
- bit_offset: 14
|
||||
bit_size: 1
|
||||
description: USART1 reset
|
||||
name: USART1RST
|
||||
- bit_offset: 15
|
||||
bit_size: 1
|
||||
description: TIM14 timer reset
|
||||
name: TIM14RST
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: TIM15 timer reset
|
||||
name: TIM15RST
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: TIM16 timer reset
|
||||
name: TIM16RST
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: TIM17 timer reset
|
||||
name: TIM17RST
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: ADC reset
|
||||
name: ADCRST
|
||||
fieldset/APBSMENR1:
|
||||
description: APB peripheral clock enable in Sleep mode register 1
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM2 timer clock enable during Sleep mode
|
||||
name: TIM2SMEN
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: TIM3 timer clock enable during Sleep mode
|
||||
name: TIM3SMEN
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: TIM6 timer clock enable during Sleep mode
|
||||
name: TIM6SMEN
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: TIM7 timer clock enable during Sleep mode
|
||||
name: TIM7SMEN
|
||||
- bit_offset: 10
|
||||
bit_size: 1
|
||||
description: RTC APB clock enable during Sleep mode
|
||||
name: RTCAPBSMEN
|
||||
- bit_offset: 11
|
||||
bit_size: 1
|
||||
description: WWDG clock enable during Sleep mode
|
||||
name: WWDGSMEN
|
||||
- bit_offset: 14
|
||||
bit_size: 1
|
||||
description: SPI2 clock enable during Sleep mode
|
||||
name: SPI2SMEN
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: USART2 clock enable during Sleep mode
|
||||
name: USART2SMEN
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: USART3 clock enable during Sleep mode
|
||||
name: USART3SMEN
|
||||
- bit_offset: 19
|
||||
bit_size: 1
|
||||
description: USART4 clock enable during Sleep mode
|
||||
name: USART4SMEN
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: LPUART1 clock enable during Sleep mode
|
||||
name: LPUART1SMEN
|
||||
- bit_offset: 21
|
||||
bit_size: 1
|
||||
description: I2C1 clock enable during Sleep mode
|
||||
name: I2C1SMEN
|
||||
- bit_offset: 22
|
||||
bit_size: 1
|
||||
description: I2C2 clock enable during Sleep mode
|
||||
name: I2C2SMEN
|
||||
- bit_offset: 24
|
||||
bit_size: 1
|
||||
description: HDMI CEC clock enable during Sleep mode
|
||||
name: CECSMEN
|
||||
- bit_offset: 25
|
||||
bit_size: 1
|
||||
description: UCPD1 clock enable during Sleep mode
|
||||
name: UCPD1SMEN
|
||||
- bit_offset: 26
|
||||
bit_size: 1
|
||||
description: UCPD2 clock enable during Sleep mode
|
||||
name: UCPD2SMEN
|
||||
- bit_offset: 27
|
||||
bit_size: 1
|
||||
description: Debug support clock enable during Sleep mode
|
||||
name: DBGSMEN
|
||||
- bit_offset: 28
|
||||
bit_size: 1
|
||||
description: Power interface clock enable during Sleep mode
|
||||
name: PWRSMEN
|
||||
- bit_offset: 29
|
||||
bit_size: 1
|
||||
description: DAC1 interface clock enable during Sleep mode
|
||||
name: DAC1SMEN
|
||||
- bit_offset: 30
|
||||
bit_size: 1
|
||||
description: Low Power Timer 2 clock enable during Sleep mode
|
||||
name: LPTIM2SMEN
|
||||
- bit_offset: 31
|
||||
bit_size: 1
|
||||
description: Low Power Timer 1 clock enable during Sleep mode
|
||||
name: LPTIM1SMEN
|
||||
fieldset/APBSMENR2:
|
||||
description: APB peripheral clock enable in Sleep mode register 2
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SYSCFG, COMP and VREFBUF clock enable during Sleep mode
|
||||
name: SYSCFGSMEN
|
||||
- bit_offset: 11
|
||||
bit_size: 1
|
||||
description: TIM1 timer clock enable during Sleep mode
|
||||
name: TIM1SMEN
|
||||
- bit_offset: 12
|
||||
bit_size: 1
|
||||
description: SPI1 clock enable during Sleep mode
|
||||
name: SPI1SMEN
|
||||
- bit_offset: 14
|
||||
bit_size: 1
|
||||
description: USART1 clock enable during Sleep mode
|
||||
name: USART1SMEN
|
||||
- bit_offset: 15
|
||||
bit_size: 1
|
||||
description: TIM14 timer clock enable during Sleep mode
|
||||
name: TIM14SMEN
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: TIM15 timer clock enable during Sleep mode
|
||||
name: TIM15SMEN
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: TIM16 timer clock enable during Sleep mode
|
||||
name: TIM16SMEN
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: TIM16 timer clock enable during Sleep mode
|
||||
name: TIM17SMEN
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: ADC clock enable during Sleep mode
|
||||
name: ADCSMEN
|
||||
fieldset/BDCR:
|
||||
description: RTC domain control register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: LSE oscillator enable
|
||||
name: LSEON
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LSE oscillator ready
|
||||
name: LSERDY
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: LSE oscillator bypass
|
||||
name: LSEBYP
|
||||
- bit_offset: 3
|
||||
bit_size: 2
|
||||
description: LSE oscillator drive capability
|
||||
name: LSEDRV
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: CSS on LSE enable
|
||||
name: LSECSSON
|
||||
- bit_offset: 6
|
||||
bit_size: 1
|
||||
description: CSS on LSE failure Detection
|
||||
name: LSECSSD
|
||||
- bit_offset: 8
|
||||
bit_size: 2
|
||||
description: RTC clock source selection
|
||||
name: RTCSEL
|
||||
- bit_offset: 15
|
||||
bit_size: 1
|
||||
description: RTC clock enable
|
||||
name: RTCEN
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: RTC domain software reset
|
||||
name: BDRST
|
||||
- bit_offset: 24
|
||||
bit_size: 1
|
||||
description: Low-speed clock output (LSCO) enable
|
||||
name: LSCOEN
|
||||
- bit_offset: 25
|
||||
bit_size: 1
|
||||
description: Low-speed clock output selection
|
||||
name: LSCOSEL
|
||||
fieldset/CCIPR:
|
||||
description: Peripherals independent clock configuration register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 2
|
||||
description: USART1 clock source selection
|
||||
name: USART1SEL
|
||||
- bit_offset: 2
|
||||
bit_size: 2
|
||||
description: USART2 clock source selection
|
||||
name: USART2SEL
|
||||
- bit_offset: 6
|
||||
bit_size: 1
|
||||
description: HDMI CEC clock source selection
|
||||
name: CECSEL
|
||||
- bit_offset: 10
|
||||
bit_size: 2
|
||||
description: LPUART1 clock source selection
|
||||
name: LPUART1SEL
|
||||
- bit_offset: 12
|
||||
bit_size: 2
|
||||
description: I2C1 clock source selection
|
||||
name: I2C1SEL
|
||||
- bit_offset: 14
|
||||
bit_size: 2
|
||||
description: I2S1 clock source selection
|
||||
name: I2S2SEL
|
||||
- bit_offset: 18
|
||||
bit_size: 2
|
||||
description: LPTIM1 clock source selection
|
||||
name: LPTIM1SEL
|
||||
- bit_offset: 20
|
||||
bit_size: 2
|
||||
description: LPTIM2 clock source selection
|
||||
name: LPTIM2SEL
|
||||
- bit_offset: 22
|
||||
bit_size: 1
|
||||
description: TIM1 clock source selection
|
||||
name: TIM1SEL
|
||||
- bit_offset: 24
|
||||
bit_size: 1
|
||||
description: TIM15 clock source selection
|
||||
name: TIM15SEL
|
||||
- bit_offset: 26
|
||||
bit_size: 2
|
||||
description: RNG clock source selection
|
||||
name: RNGSEL
|
||||
- bit_offset: 28
|
||||
bit_size: 2
|
||||
description: Division factor of RNG clock divider
|
||||
name: RNGDIV
|
||||
- bit_offset: 30
|
||||
bit_size: 2
|
||||
description: ADCs clock source selection
|
||||
name: ADCSEL
|
||||
fieldset/CFGR:
|
||||
description: Clock configuration register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 3
|
||||
description: System clock switch
|
||||
name: SW
|
||||
- bit_offset: 3
|
||||
bit_size: 3
|
||||
description: System clock switch status
|
||||
name: SWS
|
||||
- bit_offset: 8
|
||||
bit_size: 4
|
||||
description: AHB prescaler
|
||||
name: HPRE
|
||||
- bit_offset: 12
|
||||
bit_size: 3
|
||||
description: APB prescaler
|
||||
name: PPRE
|
||||
- bit_offset: 24
|
||||
bit_size: 3
|
||||
description: Microcontroller clock output
|
||||
name: MCOSEL
|
||||
- bit_offset: 28
|
||||
bit_size: 3
|
||||
description: Microcontroller clock output prescaler
|
||||
name: MCOPRE
|
||||
fieldset/CICR:
|
||||
description: Clock interrupt clear register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: LSI ready interrupt clear
|
||||
name: LSIRDYC
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LSE ready interrupt clear
|
||||
name: LSERDYC
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: HSI ready interrupt clear
|
||||
name: HSIRDYC
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: HSE ready interrupt clear
|
||||
name: HSERDYC
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: PLL ready interrupt clear
|
||||
name: PLLSYSRDYC
|
||||
- bit_offset: 8
|
||||
bit_size: 1
|
||||
description: Clock security system interrupt clear
|
||||
name: CSSC
|
||||
- bit_offset: 9
|
||||
bit_size: 1
|
||||
description: LSE Clock security system interrupt clear
|
||||
name: LSECSSC
|
||||
fieldset/CIER:
|
||||
description: Clock interrupt enable register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: LSI ready interrupt enable
|
||||
name: LSIRDYIE
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LSE ready interrupt enable
|
||||
name: LSERDYIE
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: HSI ready interrupt enable
|
||||
name: HSIRDYIE
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: HSE ready interrupt enable
|
||||
name: HSERDYIE
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: PLL ready interrupt enable
|
||||
name: PLLSYSRDYIE
|
||||
fieldset/CIFR:
|
||||
description: Clock interrupt flag register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: LSI ready interrupt flag
|
||||
name: LSIRDYF
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LSE ready interrupt flag
|
||||
name: LSERDYF
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: HSI ready interrupt flag
|
||||
name: HSIRDYF
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: HSE ready interrupt flag
|
||||
name: HSERDYF
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: PLL ready interrupt flag
|
||||
name: PLLSYSRDYF
|
||||
- bit_offset: 8
|
||||
bit_size: 1
|
||||
description: Clock security system interrupt flag
|
||||
name: CSSF
|
||||
- bit_offset: 9
|
||||
bit_size: 1
|
||||
description: LSE Clock security system interrupt flag
|
||||
name: LSECSSF
|
||||
fieldset/CR:
|
||||
description: Clock control register
|
||||
fields:
|
||||
- bit_offset: 8
|
||||
bit_size: 1
|
||||
description: HSI16 clock enable
|
||||
name: HSION
|
||||
- bit_offset: 9
|
||||
bit_size: 1
|
||||
description: HSI16 always enable for peripheral kernels
|
||||
name: HSIKERON
|
||||
- bit_offset: 10
|
||||
bit_size: 1
|
||||
description: HSI16 clock ready flag
|
||||
name: HSIRDY
|
||||
- bit_offset: 11
|
||||
bit_size: 3
|
||||
description: HSI16 clock division factor
|
||||
name: HSIDIV
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: HSE clock enable
|
||||
name: HSEON
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: HSE clock ready flag
|
||||
name: HSERDY
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: HSE crystal oscillator bypass
|
||||
name: HSEBYP
|
||||
- bit_offset: 19
|
||||
bit_size: 1
|
||||
description: Clock security system enable
|
||||
name: CSSON
|
||||
- bit_offset: 24
|
||||
bit_size: 1
|
||||
description: PLL enable
|
||||
name: PLLON
|
||||
- bit_offset: 25
|
||||
bit_size: 1
|
||||
description: PLL clock ready flag
|
||||
name: PLLRDY
|
||||
fieldset/CSR:
|
||||
description: Control/status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: LSI oscillator enable
|
||||
name: LSION
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LSI oscillator ready
|
||||
name: LSIRDY
|
||||
- bit_offset: 23
|
||||
bit_size: 1
|
||||
description: Remove reset flags
|
||||
name: RMVF
|
||||
- bit_offset: 25
|
||||
bit_size: 1
|
||||
description: Option byte loader reset flag
|
||||
name: OBLRSTF
|
||||
- bit_offset: 26
|
||||
bit_size: 1
|
||||
description: Pin reset flag
|
||||
name: PINRSTF
|
||||
- bit_offset: 27
|
||||
bit_size: 1
|
||||
description: BOR or POR/PDR flag
|
||||
name: PWRRSTF
|
||||
- bit_offset: 28
|
||||
bit_size: 1
|
||||
description: Software reset flag
|
||||
name: SFTRSTF
|
||||
- bit_offset: 29
|
||||
bit_size: 1
|
||||
description: Independent window watchdog reset flag
|
||||
name: IWDGRSTF
|
||||
- bit_offset: 30
|
||||
bit_size: 1
|
||||
description: Window watchdog reset flag
|
||||
name: WWDGRSTF
|
||||
- bit_offset: 31
|
||||
bit_size: 1
|
||||
description: Low-power reset flag
|
||||
name: LPWRRSTF
|
||||
fieldset/ICSCR:
|
||||
description: Internal clock sources calibration register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 8
|
||||
description: HSI16 clock calibration
|
||||
name: HSICAL
|
||||
- bit_offset: 8
|
||||
bit_size: 7
|
||||
description: HSI16 clock trimming
|
||||
name: HSITRIM
|
||||
fieldset/IOPENR:
|
||||
description: GPIO clock enable register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I/O port A clock enable
|
||||
name: IOPAEN
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: I/O port B clock enable
|
||||
name: IOPBEN
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: I/O port C clock enable
|
||||
name: IOPCEN
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: I/O port D clock enable
|
||||
name: IOPDEN
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: I/O port F clock enable
|
||||
name: IOPFEN
|
||||
fieldset/IOPRSTR:
|
||||
description: GPIO reset register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I/O port A reset
|
||||
name: IOPARST
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: I/O port B reset
|
||||
name: IOPBRST
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: I/O port C reset
|
||||
name: IOPCRST
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: I/O port D reset
|
||||
name: IOPDRST
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: I/O port F reset
|
||||
name: IOPFRST
|
||||
fieldset/IOPSMENR:
|
||||
description: GPIO in Sleep mode clock enable register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I/O port A clock enable during Sleep mode
|
||||
name: IOPASMEN
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: I/O port B clock enable during Sleep mode
|
||||
name: IOPBSMEN
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: I/O port C clock enable during Sleep mode
|
||||
name: IOPCSMEN
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: I/O port D clock enable during Sleep mode
|
||||
name: IOPDSMEN
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: I/O port F clock enable during Sleep mode
|
||||
name: IOPFSMEN
|
||||
fieldset/PLLSYSCFGR:
|
||||
description: PLL configuration register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 2
|
||||
description: PLL input clock source
|
||||
name: PLLSRC
|
||||
- bit_offset: 4
|
||||
bit_size: 3
|
||||
description: Division factor M of the PLL input clock divider
|
||||
name: PLLM
|
||||
- bit_offset: 8
|
||||
bit_size: 7
|
||||
description: PLL frequency multiplication factor N
|
||||
name: PLLN
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: PLLPCLK clock output enable
|
||||
name: PLLPEN
|
||||
- bit_offset: 17
|
||||
bit_size: 5
|
||||
description: PLL VCO division factor P for PLLPCLK clock output
|
||||
name: PLLP
|
||||
- bit_offset: 24
|
||||
bit_size: 1
|
||||
description: PLLQCLK clock output enable
|
||||
name: PLLQEN
|
||||
- bit_offset: 25
|
||||
bit_size: 3
|
||||
description: PLL VCO division factor Q for PLLQCLK clock output
|
||||
name: PLLQ
|
||||
- bit_offset: 28
|
||||
bit_size: 1
|
||||
description: PLLRCLK clock output enable
|
||||
name: PLLREN
|
||||
- bit_offset: 29
|
||||
bit_size: 3
|
||||
description: PLL VCO division factor R for PLLRCLK clock output
|
||||
name: PLLR
|
||||
660
data/registers/syscfg_g0.yaml
Normal file
660
data/registers/syscfg_g0.yaml
Normal file
@ -0,0 +1,660 @@
|
||||
block/SYSCFG:
|
||||
description: System configuration controller
|
||||
items:
|
||||
- byte_offset: 0
|
||||
description: SYSCFG configuration register 1
|
||||
fieldset: CFGR1
|
||||
name: CFGR1
|
||||
- byte_offset: 24
|
||||
description: SYSCFG configuration register 1
|
||||
fieldset: CFGR2
|
||||
name: CFGR2
|
||||
- byte_offset: 48
|
||||
description: VREFBUF control and status register
|
||||
fieldset: VREFBUF_CSR
|
||||
name: VREFBUF_CSR
|
||||
- byte_offset: 52
|
||||
description: VREFBUF calibration control register
|
||||
fieldset: VREFBUF_CCR
|
||||
name: VREFBUF_CCR
|
||||
- access: Read
|
||||
byte_offset: 128
|
||||
description: interrupt line 0 status register
|
||||
fieldset: ITLINE0
|
||||
name: ITLINE0
|
||||
- access: Read
|
||||
byte_offset: 132
|
||||
description: interrupt line 1 status register
|
||||
fieldset: ITLINE1
|
||||
name: ITLINE1
|
||||
- access: Read
|
||||
byte_offset: 136
|
||||
description: interrupt line 2 status register
|
||||
fieldset: ITLINE2
|
||||
name: ITLINE2
|
||||
- access: Read
|
||||
byte_offset: 140
|
||||
description: interrupt line 3 status register
|
||||
fieldset: ITLINE3
|
||||
name: ITLINE3
|
||||
- access: Read
|
||||
byte_offset: 144
|
||||
description: interrupt line 4 status register
|
||||
fieldset: ITLINE4
|
||||
name: ITLINE4
|
||||
- access: Read
|
||||
byte_offset: 148
|
||||
description: interrupt line 5 status register
|
||||
fieldset: ITLINE5
|
||||
name: ITLINE5
|
||||
- access: Read
|
||||
byte_offset: 152
|
||||
description: interrupt line 6 status register
|
||||
fieldset: ITLINE6
|
||||
name: ITLINE6
|
||||
- access: Read
|
||||
byte_offset: 156
|
||||
description: interrupt line 7 status register
|
||||
fieldset: ITLINE7
|
||||
name: ITLINE7
|
||||
- access: Read
|
||||
byte_offset: 160
|
||||
description: interrupt line 8 status register
|
||||
fieldset: ITLINE8
|
||||
name: ITLINE8
|
||||
- access: Read
|
||||
byte_offset: 164
|
||||
description: interrupt line 9 status register
|
||||
fieldset: ITLINE9
|
||||
name: ITLINE9
|
||||
- access: Read
|
||||
byte_offset: 168
|
||||
description: interrupt line 10 status register
|
||||
fieldset: ITLINE10
|
||||
name: ITLINE10
|
||||
- access: Read
|
||||
byte_offset: 172
|
||||
description: interrupt line 11 status register
|
||||
fieldset: ITLINE11
|
||||
name: ITLINE11
|
||||
- access: Read
|
||||
byte_offset: 176
|
||||
description: interrupt line 12 status register
|
||||
fieldset: ITLINE12
|
||||
name: ITLINE12
|
||||
- access: Read
|
||||
byte_offset: 180
|
||||
description: interrupt line 13 status register
|
||||
fieldset: ITLINE13
|
||||
name: ITLINE13
|
||||
- access: Read
|
||||
byte_offset: 184
|
||||
description: interrupt line 14 status register
|
||||
fieldset: ITLINE14
|
||||
name: ITLINE14
|
||||
- access: Read
|
||||
byte_offset: 188
|
||||
description: interrupt line 15 status register
|
||||
fieldset: ITLINE15
|
||||
name: ITLINE15
|
||||
- access: Read
|
||||
byte_offset: 192
|
||||
description: interrupt line 16 status register
|
||||
fieldset: ITLINE16
|
||||
name: ITLINE16
|
||||
- access: Read
|
||||
byte_offset: 196
|
||||
description: interrupt line 17 status register
|
||||
fieldset: ITLINE17
|
||||
name: ITLINE17
|
||||
- access: Read
|
||||
byte_offset: 200
|
||||
description: interrupt line 18 status register
|
||||
fieldset: ITLINE18
|
||||
name: ITLINE18
|
||||
- access: Read
|
||||
byte_offset: 204
|
||||
description: interrupt line 19 status register
|
||||
fieldset: ITLINE19
|
||||
name: ITLINE19
|
||||
- access: Read
|
||||
byte_offset: 208
|
||||
description: interrupt line 20 status register
|
||||
fieldset: ITLINE20
|
||||
name: ITLINE20
|
||||
- access: Read
|
||||
byte_offset: 212
|
||||
description: interrupt line 21 status register
|
||||
fieldset: ITLINE21
|
||||
name: ITLINE21
|
||||
- access: Read
|
||||
byte_offset: 216
|
||||
description: interrupt line 22 status register
|
||||
fieldset: ITLINE22
|
||||
name: ITLINE22
|
||||
- access: Read
|
||||
byte_offset: 220
|
||||
description: interrupt line 23 status register
|
||||
fieldset: ITLINE23
|
||||
name: ITLINE23
|
||||
- access: Read
|
||||
byte_offset: 224
|
||||
description: interrupt line 24 status register
|
||||
fieldset: ITLINE24
|
||||
name: ITLINE24
|
||||
- access: Read
|
||||
byte_offset: 228
|
||||
description: interrupt line 25 status register
|
||||
fieldset: ITLINE25
|
||||
name: ITLINE25
|
||||
- access: Read
|
||||
byte_offset: 232
|
||||
description: interrupt line 26 status register
|
||||
fieldset: ITLINE26
|
||||
name: ITLINE26
|
||||
- access: Read
|
||||
byte_offset: 236
|
||||
description: interrupt line 27 status register
|
||||
fieldset: ITLINE27
|
||||
name: ITLINE27
|
||||
- access: Read
|
||||
byte_offset: 240
|
||||
description: interrupt line 28 status register
|
||||
fieldset: ITLINE28
|
||||
name: ITLINE28
|
||||
- access: Read
|
||||
byte_offset: 244
|
||||
description: interrupt line 29 status register
|
||||
fieldset: ITLINE29
|
||||
name: ITLINE29
|
||||
- access: Read
|
||||
byte_offset: 248
|
||||
description: interrupt line 30 status register
|
||||
fieldset: ITLINE30
|
||||
name: ITLINE30
|
||||
- access: Read
|
||||
byte_offset: 252
|
||||
description: interrupt line 31 status register
|
||||
fieldset: ITLINE31
|
||||
name: ITLINE31
|
||||
fieldset/CFGR1:
|
||||
description: SYSCFG configuration register 1
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 2
|
||||
description: Memory mapping selection bits
|
||||
name: MEM_MODE
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: PA11 and PA12 remapping bit.
|
||||
name: PA11_PA12_RMP
|
||||
- bit_offset: 5
|
||||
bit_size: 1
|
||||
description: IR output polarity selection
|
||||
name: IR_POL
|
||||
- bit_offset: 6
|
||||
bit_size: 2
|
||||
description: IR Modulation Envelope signal selection.
|
||||
name: IR_MOD
|
||||
- bit_offset: 8
|
||||
bit_size: 1
|
||||
description: I/O analog switch voltage booster enable
|
||||
name: BOOSTEN
|
||||
- bit_offset: 9
|
||||
bit_size: 1
|
||||
description: Strobe signal bit for UCPD1
|
||||
name: UCPD1_STROBE
|
||||
- bit_offset: 10
|
||||
bit_size: 1
|
||||
description: Strobe signal bit for UCPD2
|
||||
name: UCPD2_STROBE
|
||||
- bit_offset: 16
|
||||
bit_size: 4
|
||||
description: Fast Mode Plus (FM+) driving capability activation bits
|
||||
name: I2C_PBx_FMP
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: FM+ driving capability activation for I2C1
|
||||
name: I2C1_FMP
|
||||
- bit_offset: 21
|
||||
bit_size: 1
|
||||
description: FM+ driving capability activation for I2C2
|
||||
name: I2C2_FMP
|
||||
- bit_offset: 22
|
||||
bit_size: 2
|
||||
description: Fast Mode Plus (FM+) driving capability activation bits
|
||||
name: I2C_PAx_FMP
|
||||
fieldset/CFGR2:
|
||||
description: SYSCFG configuration register 1
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: Cortex-M0+ LOCKUP bit enable bit
|
||||
name: LOCKUP_LOCK
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: SRAM parity lock bit
|
||||
name: SRAM_PARITY_LOCK
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: PVD lock enable bit
|
||||
name: PVD_LOCK
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: ECC error lock bit
|
||||
name: ECC_LOCK
|
||||
- bit_offset: 8
|
||||
bit_size: 1
|
||||
description: SRAM parity error flag
|
||||
name: SRAM_PEF
|
||||
- bit_offset: 16
|
||||
bit_size: 1
|
||||
description: PA1_CDEN
|
||||
name: PA1_CDEN
|
||||
- bit_offset: 17
|
||||
bit_size: 1
|
||||
description: PA3_CDEN
|
||||
name: PA3_CDEN
|
||||
- bit_offset: 18
|
||||
bit_size: 1
|
||||
description: PA5_CDEN
|
||||
name: PA5_CDEN
|
||||
- bit_offset: 19
|
||||
bit_size: 1
|
||||
description: PA6_CDEN
|
||||
name: PA6_CDEN
|
||||
- bit_offset: 20
|
||||
bit_size: 1
|
||||
description: PA13_CDEN
|
||||
name: PA13_CDEN
|
||||
- bit_offset: 21
|
||||
bit_size: 1
|
||||
description: PB0_CDEN
|
||||
name: PB0_CDEN
|
||||
- bit_offset: 22
|
||||
bit_size: 1
|
||||
description: PB1_CDEN
|
||||
name: PB1_CDEN
|
||||
- bit_offset: 23
|
||||
bit_size: 1
|
||||
description: PB2_CDEN
|
||||
name: PB2_CDEN
|
||||
fieldset/ITLINE0:
|
||||
description: interrupt line 0 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: Window watchdog interrupt pending flag
|
||||
name: WWDG
|
||||
fieldset/ITLINE1:
|
||||
description: interrupt line 1 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: PVD supply monitoring interrupt request pending (EXTI line 16).
|
||||
name: PVDOUT
|
||||
fieldset/ITLINE10:
|
||||
description: interrupt line 10 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: DMA1_CH1
|
||||
name: DMA1_CH2
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: DMA1_CH3
|
||||
name: DMA1_CH3
|
||||
fieldset/ITLINE11:
|
||||
description: interrupt line 11 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: DMAMUX
|
||||
name: DMAMUX
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: DMA1_CH4
|
||||
name: DMA1_CH4
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: DMA1_CH5
|
||||
name: DMA1_CH5
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: DMA1_CH6
|
||||
name: DMA1_CH6
|
||||
- bit_offset: 4
|
||||
bit_size: 1
|
||||
description: DMA1_CH7
|
||||
name: DMA1_CH7
|
||||
fieldset/ITLINE12:
|
||||
description: interrupt line 12 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: ADC
|
||||
name: ADC
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
description: COMP1
|
||||
name: COMP
|
||||
fieldset/ITLINE13:
|
||||
description: interrupt line 13 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM1_CCU
|
||||
name: TIM1_CCU
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: TIM1_TRG
|
||||
name: TIM1_TRG
|
||||
- bit_offset: 2
|
||||
bit_size: 1
|
||||
description: TIM1_UPD
|
||||
name: TIM1_UPD
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: TIM1_BRK
|
||||
name: TIM1_BRK
|
||||
fieldset/ITLINE14:
|
||||
description: interrupt line 14 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM1_CC
|
||||
name: TIM1_CC
|
||||
fieldset/ITLINE15:
|
||||
description: interrupt line 15 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM2
|
||||
name: TIM
|
||||
fieldset/ITLINE16:
|
||||
description: interrupt line 16 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM3
|
||||
name: TIM
|
||||
fieldset/ITLINE17:
|
||||
description: interrupt line 17 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM6
|
||||
name: TIM
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: DAC
|
||||
name: DAC
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
description: LPTIM1
|
||||
name: LPTIM
|
||||
fieldset/ITLINE18:
|
||||
description: interrupt line 18 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM7
|
||||
name: TIM
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
description: LPTIM2
|
||||
name: LPTIM
|
||||
fieldset/ITLINE19:
|
||||
description: interrupt line 19 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM14
|
||||
name: TIM
|
||||
fieldset/ITLINE2:
|
||||
description: interrupt line 2 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TAMP
|
||||
name: TAMP
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: RTC
|
||||
name: RTC
|
||||
fieldset/ITLINE20:
|
||||
description: interrupt line 20 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM15
|
||||
name: TIM
|
||||
fieldset/ITLINE21:
|
||||
description: interrupt line 21 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM16
|
||||
name: TIM
|
||||
fieldset/ITLINE22:
|
||||
description: interrupt line 22 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: TIM17
|
||||
name: TIM
|
||||
fieldset/ITLINE23:
|
||||
description: interrupt line 23 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I2C1
|
||||
name: I2C1
|
||||
fieldset/ITLINE24:
|
||||
description: interrupt line 24 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: I2C2
|
||||
name: I2C2
|
||||
fieldset/ITLINE25:
|
||||
description: interrupt line 25 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SPI1
|
||||
name: SPI
|
||||
fieldset/ITLINE26:
|
||||
description: interrupt line 26 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: SPI2
|
||||
name: SPI
|
||||
fieldset/ITLINE27:
|
||||
description: interrupt line 27 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: USART1
|
||||
name: USART
|
||||
fieldset/ITLINE28:
|
||||
description: interrupt line 28 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: USART2
|
||||
name: USART
|
||||
fieldset/ITLINE29:
|
||||
description: interrupt line 29 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 3
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: USART3
|
||||
name: USART
|
||||
fieldset/ITLINE3:
|
||||
description: interrupt line 3 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: FLASH_ITF
|
||||
name: FLASH_ITF
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: FLASH_ECC
|
||||
name: FLASH_ECC
|
||||
fieldset/ITLINE30:
|
||||
description: interrupt line 30 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 1
|
||||
stride: 0
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: CEC
|
||||
name: USART
|
||||
fieldset/ITLINE31:
|
||||
description: interrupt line 31 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: RNG
|
||||
name: RNG
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: AES
|
||||
name: AES
|
||||
fieldset/ITLINE4:
|
||||
description: interrupt line 4 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: RCC
|
||||
name: RCC
|
||||
fieldset/ITLINE5:
|
||||
description: interrupt line 5 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: EXTI0
|
||||
name: EXTI
|
||||
fieldset/ITLINE6:
|
||||
description: interrupt line 6 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: EXTI2
|
||||
name: EXTI
|
||||
fieldset/ITLINE7:
|
||||
description: interrupt line 7 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 12
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: EXTI4
|
||||
name: EXTI
|
||||
fieldset/ITLINE8:
|
||||
description: interrupt line 8 status register
|
||||
fields:
|
||||
- array:
|
||||
len: 2
|
||||
stride: 1
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
description: UCPD1
|
||||
name: UCPD
|
||||
fieldset/ITLINE9:
|
||||
description: interrupt line 9 status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: DMA1_CH1
|
||||
name: DMA1_CH1
|
||||
fieldset/VREFBUF_CCR:
|
||||
description: VREFBUF calibration control register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 6
|
||||
description: Trimming code These bits are automatically initialized after reset
|
||||
with the trimming value stored in the Flash memory during the production test.
|
||||
Writing into these bits allows to tune the internal reference buffer voltage.
|
||||
name: TRIM
|
||||
fieldset/VREFBUF_CSR:
|
||||
description: VREFBUF control and status register
|
||||
fields:
|
||||
- bit_offset: 0
|
||||
bit_size: 1
|
||||
description: Voltage reference buffer mode enable This bit is used to enable the
|
||||
voltage reference buffer mode.
|
||||
name: ENVR
|
||||
- bit_offset: 1
|
||||
bit_size: 1
|
||||
description: 'High impedance mode This bit controls the analog switch to connect
|
||||
or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions
|
||||
depending on ENVR bit configuration.'
|
||||
name: HIZ
|
||||
- bit_offset: 3
|
||||
bit_size: 1
|
||||
description: Voltage reference buffer ready
|
||||
name: VRR
|
||||
- bit_offset: 4
|
||||
bit_size: 3
|
||||
description: 'Voltage reference scale These bits select the value generated by
|
||||
the voltage reference buffer. Other: Reserved'
|
||||
name: VRS
|
||||
@ -1,4 +1,4 @@
|
||||
#!/bin/bash
|
||||
#!/usr/bin/env bash
|
||||
|
||||
echo "Usage: ./extract.sh all|<board_name> <peripheral>"
|
||||
|
||||
|
||||
2
merge_regs.py
Normal file → Executable file
2
merge_regs.py
Normal file → Executable file
@ -1,3 +1,5 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import xmltodict
|
||||
import yaml
|
||||
import re
|
||||
|
||||
39
parse.py
39
parse.py
@ -48,7 +48,7 @@ def removeprefix(value: str, prefix: str, /) -> str:
|
||||
|
||||
|
||||
def corename(d):
|
||||
#print("CHECKING CORENAME", d)
|
||||
# print("CHECKING CORENAME", d)
|
||||
if m := re.match('.*Cortex-M(\d+)(\+?)\s*(.*)', d):
|
||||
name = "cm" + str(m.group(1))
|
||||
if m.group(2) == "+":
|
||||
@ -340,6 +340,8 @@ perimap = [
|
||||
('.*:DAC:dacif_v2_0', 'dac_v2/DAC'),
|
||||
('.*:DAC:dacif_v3_0', 'dac_v2/DAC'),
|
||||
('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'),
|
||||
('STM32G0.*:ADC:.*', 'adc_v3/ADC'),
|
||||
('STM32G0.*:ADC_COMMON:.*', 'adccommon_v3/ADC_COMMON'),
|
||||
('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
|
||||
('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
|
||||
('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'),
|
||||
@ -347,6 +349,7 @@ perimap = [
|
||||
('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
|
||||
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
|
||||
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
|
||||
('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
|
||||
('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
|
||||
('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
|
||||
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
|
||||
@ -357,6 +360,7 @@ perimap = [
|
||||
('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
|
||||
('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
|
||||
('STM32F1.*:RCC:.*', 'rcc_f1/RCC'),
|
||||
('STM32G0.*:RCC:.*', 'rcc_g0/RCC'),
|
||||
('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
|
||||
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
|
||||
('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
|
||||
@ -408,6 +412,7 @@ address_overrides = {
|
||||
'STM32F412VG:GPIOG_BASE': 0x40021800,
|
||||
}
|
||||
|
||||
|
||||
def lookup_address(defines, name, d):
|
||||
if addr := defines.get(d):
|
||||
return addr
|
||||
@ -660,6 +665,8 @@ def parse_chips():
|
||||
pname = 'SYSCFG'
|
||||
if pname == 'SUBGHZ':
|
||||
pname = 'SUBGHZSPI'
|
||||
if pname == 'SYSCFG_VREFBUF':
|
||||
pname = 'SYSCFG'
|
||||
if pname in FAKE_PERIPHERALS:
|
||||
continue
|
||||
if pname.startswith('ADC'):
|
||||
@ -698,7 +705,9 @@ def parse_chips():
|
||||
if af_num is not None:
|
||||
entry['af'] = af_num
|
||||
|
||||
pins[peri_name].append(entry)
|
||||
# Some SVDs have duplicate pin definitions
|
||||
if entry not in pins[peri_name]:
|
||||
pins[peri_name].append(entry)
|
||||
|
||||
for chip_name, chip in chips.items():
|
||||
if len(sys.argv) > 1:
|
||||
@ -746,9 +755,9 @@ def parse_chips():
|
||||
|
||||
found.append(key)
|
||||
|
||||
chip['flash']['regions'][key] = OrderedDict( {
|
||||
chip['flash']['regions'][key] = OrderedDict({
|
||||
'base': HexInt(h['defines']['all'][each + '_BASE'])
|
||||
} )
|
||||
})
|
||||
|
||||
if key == 'BANK_1' or key == 'BANK_2':
|
||||
flash_size = determine_flash_size(chip_name)
|
||||
@ -773,9 +782,9 @@ def parse_chips():
|
||||
|
||||
found.append(key)
|
||||
|
||||
chip['ram']['regions'][key] = OrderedDict( {
|
||||
chip['ram']['regions'][key] = OrderedDict({
|
||||
'base': HexInt(h['defines']['all'][each + '_BASE'])
|
||||
} )
|
||||
})
|
||||
|
||||
if key == 'SRAM':
|
||||
ram_size = determine_ram_size(chip_name)
|
||||
@ -893,6 +902,8 @@ def parse_chips():
|
||||
block = 'exti_wl5x/EXTI'
|
||||
elif chip_name.startswith("STM32H7"):
|
||||
block = 'exti_h7/EXTI'
|
||||
elif chip_name.startswith("STM32G0"):
|
||||
block = 'exti_g0/EXTI'
|
||||
else:
|
||||
block = 'exti_v1/EXTI'
|
||||
|
||||
@ -954,7 +965,15 @@ def parse_chips():
|
||||
|
||||
for (name, body) in core['peripherals'].items():
|
||||
if 'clock' not in body:
|
||||
if (peri_clock := match_peri_clock(rcc_block, name)) is not None:
|
||||
peri_clock = None
|
||||
if chip_name.startswith('STM32G0') and name.startswith('TIM'):
|
||||
peri_clock = 'APB'
|
||||
elif chip_name.startswith('STM32G0') and name.startswith('SYSCFG'):
|
||||
peri_clock = 'APB'
|
||||
else:
|
||||
peri_clock = match_peri_clock(rcc_block, name)
|
||||
|
||||
if peri_clock is not None:
|
||||
core['peripherals'][name]['clock'] = peri_clock
|
||||
|
||||
# Process DMA channels
|
||||
@ -1356,8 +1375,10 @@ def filter_interrupts(peri_irqs, all_irqs):
|
||||
|
||||
return filtered
|
||||
|
||||
|
||||
memories = []
|
||||
|
||||
|
||||
def parse_memories():
|
||||
with open('data/memories.yaml', 'r') as yaml_file:
|
||||
m = yaml.load(yaml_file, Loader=SafeLoader)
|
||||
@ -1373,6 +1394,7 @@ def determine_ram_size(chip_name):
|
||||
|
||||
return None
|
||||
|
||||
|
||||
def determine_flash_size(chip_name):
|
||||
for each in memories:
|
||||
for name in each['names']:
|
||||
@ -1381,6 +1403,7 @@ def determine_flash_size(chip_name):
|
||||
|
||||
return None
|
||||
|
||||
|
||||
def determine_device_id(chip_name):
|
||||
for each in memories:
|
||||
for name in each['names']:
|
||||
@ -1388,12 +1411,12 @@ def determine_device_id(chip_name):
|
||||
return each['device-id']
|
||||
return None
|
||||
|
||||
|
||||
def is_chip_name_match(pattern, chip_name):
|
||||
pattern = pattern.replace('x', '.')
|
||||
return re.match(pattern + ".*", chip_name)
|
||||
|
||||
|
||||
|
||||
parse_memories()
|
||||
parse_interrupts()
|
||||
parse_rcc_regs()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user