From 9a56721608a5bfa66919750aa378910c08c445c4 Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 09:51:50 +0300 Subject: [PATCH 1/8] add unmodified AES yamls --- data/registers/aes_f7.yaml | 330 ++++++++++++++++++++++++++++ data/registers/aes_g081.yaml | 398 +++++++++++++++++++++++++++++++++ data/registers/aes_u5.yaml | 414 +++++++++++++++++++++++++++++++++++ data/registers/aes_v1.yaml | 321 +++++++++++++++++++++++++++ data/registers/aes_v2.yaml | 332 ++++++++++++++++++++++++++++ 5 files changed, 1795 insertions(+) create mode 100644 data/registers/aes_f7.yaml create mode 100644 data/registers/aes_g081.yaml create mode 100644 data/registers/aes_u5.yaml create mode 100644 data/registers/aes_v1.yaml create mode 100644 data/registers/aes_v2.yaml diff --git a/data/registers/aes_f7.yaml b/data/registers/aes_f7.yaml new file mode 100644 index 0000000..6325adf --- /dev/null +++ b/data/registers/aes_f7.yaml @@ -0,0 +1,330 @@ +--- +block/AES: + description: Advanced encryption standard hardware accelerator 1 + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + access: Read + fieldset: SR + - name: DINR + description: data input register + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: data output register + byte_offset: 12 + access: Read + fieldset: DOUTR + - name: KEYR0 + description: key register 0 + byte_offset: 16 + fieldset: KEYR0 + - name: KEYR1 + description: key register 1 + byte_offset: 20 + fieldset: KEYR1 + - name: KEYR2 + description: key register 2 + byte_offset: 24 + fieldset: KEYR2 + - name: KEYR3 + description: key register 3 + byte_offset: 28 + fieldset: KEYR3 + - name: IVR0 + description: initialization vector register 0 + byte_offset: 32 + fieldset: IVR0 + - name: IVR1 + description: initialization vector register 1 + byte_offset: 36 + fieldset: IVR1 + - name: IVR2 + description: initialization vector register 2 + byte_offset: 40 + fieldset: IVR2 + - name: IVR3 + description: initialization vector register 3 + byte_offset: 44 + fieldset: IVR3 + - name: KEYR4 + description: key register 4 + byte_offset: 48 + fieldset: KEYR4 + - name: KEYR5 + description: key register 5 + byte_offset: 52 + fieldset: KEYR5 + - name: KEYR6 + description: key register 6 + byte_offset: 56 + fieldset: KEYR6 + - name: KEYR7 + description: key register 7 + byte_offset: 60 + fieldset: KEYR7 + - name: SUSP0R + description: AES suspend register 0 + byte_offset: 64 + fieldset: SUSP0R + - name: SUSP1R + description: AES suspend register 1 + byte_offset: 68 + fieldset: SUSP1R + - name: SUSP2R + description: AES suspend register 2 + byte_offset: 72 + fieldset: SUSP2R + - name: SUSP3R + description: AES suspend register 3 + byte_offset: 76 + fieldset: SUSP3R + - name: SUSP4R + description: AES suspend register 4 + byte_offset: 80 + fieldset: SUSP4R + - name: SUSP5R + description: AES suspend register 5 + byte_offset: 84 + fieldset: SUSP5R + - name: SUSP6R + description: AES suspend register 6 + byte_offset: 88 + fieldset: SUSP6R + - name: SUSP7R + description: AES suspend register 7 + byte_offset: 92 + fieldset: SUSP7R +fieldset/CR: + description: control register + fields: + - name: EN + description: AES enable + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: Data type selection (for data in and data out to/from the cryptographic block) + bit_offset: 1 + bit_size: 2 + - name: MODE + description: AES operating mode + bit_offset: 3 + bit_size: 2 + - name: CHMOD10 + description: AES chaining mode Bit1 Bit0 + bit_offset: 5 + bit_size: 2 + - name: CCFC + description: Computation Complete Flag Clear + bit_offset: 7 + bit_size: 1 + - name: ERRC + description: Error clear + bit_offset: 8 + bit_size: 1 + - name: CCFIE + description: CCF flag interrupt enable + bit_offset: 9 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 10 + bit_size: 1 + - name: DMAINEN + description: Enable DMA management of data input phase + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: Enable DMA management of data output phase + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: "Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected" + bit_offset: 13 + bit_size: 2 + - name: CHMOD2 + description: AES chaining mode Bit2 + bit_offset: 16 + bit_size: 1 + - name: KEYSIZE + description: Key size selection + bit_offset: 18 + bit_size: 1 +fieldset/DINR: + description: data input register + fields: + - name: AES_DINR + description: Data Input Register + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: data output register + fields: + - name: AES_DOUTR + description: Data output register + bit_offset: 0 + bit_size: 32 +fieldset/IVR0: + description: initialization vector register 0 + fields: + - name: AES_IVR0 + description: "initialization vector register (LSB IVR [31:0])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR1: + description: initialization vector register 1 + fields: + - name: AES_IVR1 + description: "Initialization Vector Register (IVR [63:32])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR2: + description: initialization vector register 2 + fields: + - name: AES_IVR2 + description: "Initialization Vector Register (IVR [95:64])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR3: + description: initialization vector register 3 + fields: + - name: AES_IVR3 + description: "Initialization Vector Register (MSB IVR [127:96])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR0: + description: key register 0 + fields: + - name: AES_KEYR0 + description: "Data Output Register (LSB key [31:0])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR1: + description: key register 1 + fields: + - name: AES_KEYR1 + description: "AES key register (key [63:32])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR2: + description: key register 2 + fields: + - name: AES_KEYR2 + description: "AES key register (key [95:64])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR3: + description: key register 3 + fields: + - name: AES_KEYR3 + description: "AES key register (MSB key [127:96])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR4: + description: key register 4 + fields: + - name: AES_KEYR4 + description: "AES key register (MSB key [159:128])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR5: + description: key register 5 + fields: + - name: AES_KEYR5 + description: "AES key register (MSB key [191:160])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR6: + description: key register 6 + fields: + - name: AES_KEYR6 + description: "AES key register (MSB key [223:192])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR7: + description: key register 7 + fields: + - name: AES_KEYR7 + description: "AES key register (MSB key [255:224])" + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: Read error flag + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: Write error flag + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy flag + bit_offset: 3 + bit_size: 1 +fieldset/SUSP0R: + description: AES suspend register 0 + fields: + - name: AES_SUSP0R + description: AES suspend register 0 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP1R: + description: AES suspend register 1 + fields: + - name: AES_SUSP1R + description: AES suspend register 1 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP2R: + description: AES suspend register 2 + fields: + - name: AES_SUSP2R + description: AES suspend register 2 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP3R: + description: AES suspend register 3 + fields: + - name: AES_SUSP3R + description: AES suspend register 3 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP4R: + description: AES suspend register 4 + fields: + - name: AES_SUSP4R + description: AES suspend register 4 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP5R: + description: AES suspend register 5 + fields: + - name: AES_SUSP5R + description: AES suspend register 5 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP6R: + description: AES suspend register 6 + fields: + - name: AES_SUSP6R + description: AES suspend register 6 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP7R: + description: AES suspend register 7 + fields: + - name: AES_SUSP7R + description: AES suspend register 7 + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/aes_g081.yaml b/data/registers/aes_g081.yaml new file mode 100644 index 0000000..d0b8e82 --- /dev/null +++ b/data/registers/aes_g081.yaml @@ -0,0 +1,398 @@ +--- +block/AES: + description: Advanced encryption standard hardware accelerator 1 + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + access: Read + fieldset: SR + - name: DINR + description: data input register + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: data output register + byte_offset: 12 + access: Read + fieldset: DOUTR + - name: KEYR0 + description: key register 0 + byte_offset: 16 + fieldset: KEYR0 + - name: KEYR1 + description: key register 1 + byte_offset: 20 + fieldset: KEYR1 + - name: KEYR2 + description: key register 2 + byte_offset: 24 + fieldset: KEYR2 + - name: KEYR3 + description: key register 3 + byte_offset: 28 + fieldset: KEYR3 + - name: IVR0 + description: initialization vector register 0 + byte_offset: 32 + fieldset: IVR0 + - name: IVR1 + description: initialization vector register 1 + byte_offset: 36 + fieldset: IVR1 + - name: IVR2 + description: initialization vector register 2 + byte_offset: 40 + fieldset: IVR2 + - name: IVR3 + description: initialization vector register 3 + byte_offset: 44 + fieldset: IVR3 + - name: KEYR4 + description: key register 4 + byte_offset: 48 + fieldset: KEYR4 + - name: KEYR5 + description: key register 5 + byte_offset: 52 + fieldset: KEYR5 + - name: KEYR6 + description: key register 6 + byte_offset: 56 + fieldset: KEYR6 + - name: KEYR7 + description: key register 7 + byte_offset: 60 + fieldset: KEYR7 + - name: SUSP0R + description: AES suspend register 0 + byte_offset: 64 + fieldset: SUSP0R + - name: SUSP1R + description: AES suspend register 1 + byte_offset: 68 + fieldset: SUSP1R + - name: SUSP2R + description: AES suspend register 2 + byte_offset: 72 + fieldset: SUSP2R + - name: SUSP3R + description: AES suspend register 3 + byte_offset: 76 + fieldset: SUSP3R + - name: SUSP4R + description: AES suspend register 4 + byte_offset: 80 + fieldset: SUSP4R + - name: SUSP5R + description: AES suspend register 5 + byte_offset: 84 + fieldset: SUSP5R + - name: SUSP6R + description: AES suspend register 6 + byte_offset: 88 + fieldset: SUSP6R + - name: SUSP7R + description: AES suspend register 7 + byte_offset: 92 + fieldset: SUSP7R + - name: HWCFR + description: AES hardware configuration register + byte_offset: 1008 + access: Read + fieldset: HWCFR + - name: VERR + description: AES version register + byte_offset: 1012 + access: Read + fieldset: VERR + - name: IPIDR + description: AES identification register + byte_offset: 1016 + access: Read + fieldset: IPIDR + - name: SIDR + description: AES size ID register + byte_offset: 1020 + access: Read + fieldset: SIDR +fieldset/CR: + description: control register + fields: + - name: EN + description: AES enable + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: Data type selection (for data in and data out to/from the cryptographic block) + bit_offset: 1 + bit_size: 2 + - name: MODE + description: AES operating mode + bit_offset: 3 + bit_size: 2 + - name: CHMOD10 + description: AES chaining mode Bit1 Bit0 + bit_offset: 5 + bit_size: 2 + - name: CCFC + description: Computation Complete Flag Clear + bit_offset: 7 + bit_size: 1 + - name: ERRC + description: Error clear + bit_offset: 8 + bit_size: 1 + - name: CCFIE + description: CCF flag interrupt enable + bit_offset: 9 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 10 + bit_size: 1 + - name: DMAINEN + description: Enable DMA management of data input phase + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: Enable DMA management of data output phase + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: "Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected" + bit_offset: 13 + bit_size: 2 + - name: CHMOD2 + description: AES chaining mode Bit2 + bit_offset: 16 + bit_size: 1 + - name: KEYSIZE + description: Key size selection + bit_offset: 18 + bit_size: 1 + - name: NPBLB + description: Number of padding bytes in last block of payload + bit_offset: 20 + bit_size: 4 +fieldset/DINR: + description: data input register + fields: + - name: AES_DINR + description: Data Input Register + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: data output register + fields: + - name: AES_DOUTR + description: Data output register + bit_offset: 0 + bit_size: 32 +fieldset/HWCFR: + description: AES hardware configuration register + fields: + - name: CFG1 + description: HW Generic 1 + bit_offset: 0 + bit_size: 4 + - name: CFG2 + description: HW Generic 2 + bit_offset: 4 + bit_size: 4 + - name: CFG3 + description: HW Generic 3 + bit_offset: 8 + bit_size: 4 + - name: CFG4 + description: HW Generic 4 + bit_offset: 12 + bit_size: 4 +fieldset/IPIDR: + description: AES identification register + fields: + - name: ID + description: Identification code + bit_offset: 0 + bit_size: 32 +fieldset/IVR0: + description: initialization vector register 0 + fields: + - name: AES_IVR0 + description: "initialization vector register (LSB IVR [31:0])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR1: + description: initialization vector register 1 + fields: + - name: AES_IVR1 + description: "Initialization Vector Register (IVR [63:32])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR2: + description: initialization vector register 2 + fields: + - name: AES_IVR2 + description: "Initialization Vector Register (IVR [95:64])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR3: + description: initialization vector register 3 + fields: + - name: AES_IVR3 + description: "Initialization Vector Register (MSB IVR [127:96])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR0: + description: key register 0 + fields: + - name: AES_KEYR0 + description: "Data Output Register (LSB key [31:0])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR1: + description: key register 1 + fields: + - name: AES_KEYR1 + description: "AES key register (key [63:32])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR2: + description: key register 2 + fields: + - name: AES_KEYR2 + description: "AES key register (key [95:64])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR3: + description: key register 3 + fields: + - name: AES_KEYR3 + description: "AES key register (MSB key [127:96])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR4: + description: key register 4 + fields: + - name: AES_KEYR4 + description: "AES key register (MSB key [159:128])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR5: + description: key register 5 + fields: + - name: AES_KEYR5 + description: "AES key register (MSB key [191:160])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR6: + description: key register 6 + fields: + - name: AES_KEYR6 + description: "AES key register (MSB key [223:192])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR7: + description: key register 7 + fields: + - name: AES_KEYR7 + description: "AES key register (MSB key [255:224])" + bit_offset: 0 + bit_size: 32 +fieldset/SIDR: + description: AES size ID register + fields: + - name: ID + description: Size Identification code + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: Read error flag + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: Write error flag + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy flag + bit_offset: 3 + bit_size: 1 +fieldset/SUSP0R: + description: AES suspend register 0 + fields: + - name: AES_SUSP0R + description: AES suspend register 0 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP1R: + description: AES suspend register 1 + fields: + - name: AES_SUSP1R + description: AES suspend register 1 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP2R: + description: AES suspend register 2 + fields: + - name: AES_SUSP2R + description: AES suspend register 2 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP3R: + description: AES suspend register 3 + fields: + - name: AES_SUSP3R + description: AES suspend register 3 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP4R: + description: AES suspend register 4 + fields: + - name: AES_SUSP4R + description: AES suspend register 4 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP5R: + description: AES suspend register 5 + fields: + - name: AES_SUSP5R + description: AES suspend register 5 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP6R: + description: AES suspend register 6 + fields: + - name: AES_SUSP6R + description: AES suspend register 6 + bit_offset: 0 + bit_size: 32 +fieldset/SUSP7R: + description: AES suspend register 7 + fields: + - name: AES_SUSP7R + description: AES suspend register 7 + bit_offset: 0 + bit_size: 32 +fieldset/VERR: + description: AES version register + fields: + - name: MINREV + description: Minor revision + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: Major revision + bit_offset: 4 + bit_size: 4 diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_u5.yaml new file mode 100644 index 0000000..b4366cc --- /dev/null +++ b/data/registers/aes_u5.yaml @@ -0,0 +1,414 @@ +--- +block/AES: + description: Advanced encryption standard hardware accelerator + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + access: Read + fieldset: SR + - name: DINR + description: data input register + byte_offset: 8 + access: Write + fieldset: DINR + - name: DOUTR + description: data output register + byte_offset: 12 + access: Read + fieldset: DOUTR + - name: KEYR0 + description: key register 0 + byte_offset: 16 + access: Write + fieldset: KEYR0 + - name: KEYR1 + description: key register 1 + byte_offset: 20 + access: Write + fieldset: KEYR1 + - name: KEYR2 + description: key register 2 + byte_offset: 24 + access: Write + fieldset: KEYR2 + - name: KEYR3 + description: key register 3 + byte_offset: 28 + access: Write + fieldset: KEYR3 + - name: IVR0 + description: initialization vector register 0 + byte_offset: 32 + fieldset: IVR0 + - name: IVR1 + description: initialization vector register 1 + byte_offset: 36 + fieldset: IVR1 + - name: IVR2 + description: initialization vector register 2 + byte_offset: 40 + fieldset: IVR2 + - name: IVR3 + description: initialization vector register 3 + byte_offset: 44 + fieldset: IVR3 + - name: KEYR4 + description: key register 4 + byte_offset: 48 + access: Write + fieldset: KEYR4 + - name: KEYR5 + description: key register 5 + byte_offset: 52 + access: Write + fieldset: KEYR5 + - name: KEYR6 + description: key register 6 + byte_offset: 56 + access: Write + fieldset: KEYR6 + - name: KEYR7 + description: key register 7 + byte_offset: 60 + access: Write + fieldset: KEYR7 + - name: SUSP0R + description: suspend registers + byte_offset: 64 + access: Write + fieldset: SUSP0R + - name: SUSP1R + description: suspend registers + byte_offset: 68 + access: Write + fieldset: SUSP1R + - name: SUSP2R + description: suspend registers + byte_offset: 72 + access: Write + fieldset: SUSP2R + - name: SUSP3R + description: suspend registers + byte_offset: 76 + access: Write + fieldset: SUSP3R + - name: SUSP4R + description: suspend registers + byte_offset: 80 + access: Write + fieldset: SUSP4R + - name: SUSP5R + description: suspend registers + byte_offset: 84 + access: Write + fieldset: SUSP5R + - name: SUSP6R + description: suspend registers + byte_offset: 88 + access: Write + fieldset: SUSP6R + - name: SUSP7R + description: suspend registers + byte_offset: 92 + access: Write + fieldset: SUSP7R + - name: IER + description: interrupt enable register + byte_offset: 768 + fieldset: IER + - name: ISR + description: interrupt status register + byte_offset: 772 + access: Read + fieldset: ISR + - name: ICR + description: interrupt clear register + byte_offset: 776 + access: Write + fieldset: ICR +fieldset/CR: + description: control register + fields: + - name: EN + description: AES enable + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: Data type selection (for data in and data out to/from the cryptographic block) + bit_offset: 1 + bit_size: 2 + - name: MODE + description: AES operating mode + bit_offset: 3 + bit_size: 2 + - name: CHMOD + description: AES chaining mode + bit_offset: 5 + bit_size: 2 + - name: DMAINEN + description: Enable DMA management of data input phase + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: Enable DMA management of data output phase + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: GCMPH + bit_offset: 13 + bit_size: 2 + - name: CHMOD_2 + description: CHMOD_2 + bit_offset: 16 + bit_size: 1 + - name: KEYSIZE + description: KEYSIZE + bit_offset: 18 + bit_size: 1 + - name: NPBLB + description: NPBLB + bit_offset: 20 + bit_size: 4 + - name: KMOD + description: KMOD + bit_offset: 24 + bit_size: 2 + - name: IPRST + description: IPRST + bit_offset: 31 + bit_size: 1 +fieldset/DINR: + description: data input register + fields: + - name: DIN + description: Input data word + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: data output register + fields: + - name: DOUT + description: Output data word + bit_offset: 0 + bit_size: 32 +fieldset/ICR: + description: interrupt clear register + fields: + - name: CCF + description: Computation complete flag clear + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag clear + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag clear + bit_offset: 2 + bit_size: 1 +fieldset/IER: + description: interrupt enable register + fields: + - name: CCFIE + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RWEIE + description: Read or write error interrupt flag + bit_offset: 1 + bit_size: 1 + - name: KEIE + description: Key error interrupt flag + bit_offset: 2 + bit_size: 1 + - name: RNGEIE + description: Key error interrupt flag + bit_offset: 3 + bit_size: 1 +fieldset/ISR: + description: interrupt status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RWEIF + description: Read or write error interrupt flag + bit_offset: 1 + bit_size: 1 + - name: KEIF + description: Key error interrupt flag + bit_offset: 2 + bit_size: 1 + - name: RNGEIF + description: Key error interrupt flag + bit_offset: 3 + bit_size: 1 +fieldset/IVR0: + description: initialization vector register 0 + fields: + - name: IVI + description: "Initialization vector input, bits [31:0]" + bit_offset: 0 + bit_size: 32 +fieldset/IVR1: + description: initialization vector register 1 + fields: + - name: IVI + description: "Initialization vector input, bits [63:32]" + bit_offset: 0 + bit_size: 32 +fieldset/IVR2: + description: initialization vector register 2 + fields: + - name: IVI + description: "Initialization vector input, bits [95:64]" + bit_offset: 0 + bit_size: 32 +fieldset/IVR3: + description: initialization vector register 3 + fields: + - name: IVI + description: "Initialization vector input, bits [127:96]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR0: + description: key register 0 + fields: + - name: KEY + description: "Cryptographic key, bits [31:0]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR1: + description: key register 1 + fields: + - name: KEY + description: "Cryptographic key, bits [63:32]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR2: + description: key register 2 + fields: + - name: KEYR + description: "Cryptographic key, bits [95:64]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR3: + description: key register 3 + fields: + - name: AES_KEYR3 + description: "Cryptographic key, bits [127:96]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR4: + description: key register 4 + fields: + - name: KEY + description: "Cryptographic key, bits [159:128]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR5: + description: key register 5 + fields: + - name: KEY + description: "Cryptographic key, bits [191:160]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR6: + description: key register 6 + fields: + - name: KEY + description: "Cryptographic key, bits [223:192]" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR7: + description: key register 7 + fields: + - name: KEY + description: "Cryptographic key, bits [255:224]" + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: Read error flag + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: Write error flag + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: BUSY + bit_offset: 3 + bit_size: 1 + - name: KEYVALID + description: Key Valid flag + bit_offset: 7 + bit_size: 1 +fieldset/SUSP0R: + description: suspend registers + fields: + - name: SUSP0 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP1R: + description: suspend registers + fields: + - name: SUSP1 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP2R: + description: suspend registers + fields: + - name: SUSP2 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP3R: + description: suspend registers + fields: + - name: SUSP3 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP4R: + description: suspend registers + fields: + - name: SUSP4 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP5R: + description: suspend registers + fields: + - name: SUSP5 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP6R: + description: suspend registers + fields: + - name: SUSP6 + description: AES suspend + bit_offset: 0 + bit_size: 32 +fieldset/SUSP7R: + description: suspend registers + fields: + - name: SUSP7 + description: AES suspend + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/aes_v1.yaml b/data/registers/aes_v1.yaml new file mode 100644 index 0000000..1f2ee7e --- /dev/null +++ b/data/registers/aes_v1.yaml @@ -0,0 +1,321 @@ +--- +block/AES: + description: Advanced encryption standard hardware accelerator + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + access: Read + fieldset: SR + - name: DINR + description: data input register + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: data output register + byte_offset: 12 + access: Read + fieldset: DOUTR + - name: KEYR0 + description: key register 0 + byte_offset: 16 + fieldset: KEYR0 + - name: KEYR1 + description: key register 1 + byte_offset: 20 + fieldset: KEYR1 + - name: KEYR2 + description: key register 2 + byte_offset: 24 + fieldset: KEYR2 + - name: KEYR3 + description: key register 3 + byte_offset: 28 + fieldset: KEYR3 + - name: IVR0 + description: initialization vector register 0 + byte_offset: 32 + fieldset: IVR0 + - name: IVR1 + description: initialization vector register 1 + byte_offset: 36 + fieldset: IVR1 + - name: IVR2 + description: initialization vector register 2 + byte_offset: 40 + fieldset: IVR2 + - name: IVR3 + description: initialization vector register 3 + byte_offset: 44 + fieldset: IVR3 +fieldset/CR: + description: control register + fields: + - name: EN + description: AES enable + bit_offset: 0 + bit_size: 1 + enum: EN + - name: DATATYPE + description: Data type selection (for data in and data out to/from the cryptographic block) + bit_offset: 1 + bit_size: 2 + enum: DATATYPE + - name: MODE + description: AES operating mode + bit_offset: 3 + bit_size: 2 + enum: MODE + - name: CHMOD + description: AES chaining mode + bit_offset: 5 + bit_size: 2 + enum: CHMOD + - name: CCFC + description: Computation Complete Flag Clear + bit_offset: 7 + bit_size: 1 + enum: CCFC + - name: ERRC + description: Error clear + bit_offset: 8 + bit_size: 1 + enum: ERRC + - name: CCFIE + description: CCF flag interrupt enable + bit_offset: 9 + bit_size: 1 + enum: CCFIE + - name: ERRIE + description: Error interrupt enable + bit_offset: 10 + bit_size: 1 + enum: ERRIE + - name: DMAINEN + description: Enable DMA management of data input phase + bit_offset: 11 + bit_size: 1 + enum: DMAINEN + - name: DMAOUTEN + description: Enable DMA management of data output phase + bit_offset: 12 + bit_size: 1 + enum: DMAOUTEN +fieldset/DINR: + description: data input register + fields: + - name: DIN + description: Data Input Register. + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: data output register + fields: + - name: DOUT + description: Data output register + bit_offset: 0 + bit_size: 32 +fieldset/IVR0: + description: initialization vector register 0 + fields: + - name: IV0 + description: "initialization vector register (LSB IVR [31:0])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR1: + description: initialization vector register 1 + fields: + - name: IV1 + description: "Initialization Vector Register (IVR [63:32])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR2: + description: initialization vector register 2 + fields: + - name: IV2 + description: "Initialization Vector Register (IVR [95:64])" + bit_offset: 0 + bit_size: 32 +fieldset/IVR3: + description: initialization vector register 3 + fields: + - name: IV3 + description: "Initialization Vector Register (MSB IVR [127:96])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR0: + description: key register 0 + fields: + - name: KEY0 + description: "Data Output Register (LSB key [31:0])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR1: + description: key register 1 + fields: + - name: KEY1 + description: "AES key register (key [63:32])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR2: + description: key register 2 + fields: + - name: KEY2 + description: "AES key register (key [95:64])" + bit_offset: 0 + bit_size: 32 +fieldset/KEYR3: + description: key register 3 + fields: + - name: KEY3 + description: "AES key register (MSB key [127:96])" + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: status register + fields: + - name: CCF + description: Computation complete flag + bit_offset: 0 + bit_size: 1 + enum: CCF + - name: RDERR + description: Read error flag + bit_offset: 1 + bit_size: 1 + enum: RDERR + - name: WRERR + description: Write error flag + bit_offset: 2 + bit_size: 1 + enum: WRERR +enum/CCF: + bit_size: 1 + variants: + - name: Complete + description: Computation complete + value: 0 + - name: NotComplete + description: Computation not complete + value: 1 +enum/CCFC: + bit_size: 1 + variants: + - name: Clear + description: Clear computation complete flag + value: 1 +enum/CCFIE: + bit_size: 1 + variants: + - name: Disabled + description: Disable (mask) CCF interrupt + value: 0 + - name: Enabled + description: Enable CCF interrupt + value: 1 +enum/CHMOD: + bit_size: 2 + variants: + - name: ECB + description: Electronic codebook (ECB) + value: 0 + - name: CBC + description: Cipher-Block Chaining (CBC) + value: 1 + - name: CTR + description: Counter Mode (CTR) + value: 2 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/DMAINEN: + bit_size: 1 + variants: + - name: Disabled + description: Disable DMA Input + value: 0 + - name: Enabled + description: Enable DMA Input + value: 1 +enum/DMAOUTEN: + bit_size: 1 + variants: + - name: Disabled + description: Disable DMA Output + value: 0 + - name: Enabled + description: Enabled DMA Output + value: 1 +enum/EN: + bit_size: 1 + variants: + - name: Disabled + description: Disable AES + value: 0 + - name: Enabled + description: Enable AES + value: 1 +enum/ERRC: + bit_size: 1 + variants: + - name: Clear + description: Clear RDERR and WRERR flags + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Disable (mask) error interrupt + value: 0 + - name: Enabled + description: Enable error interrupt + value: 1 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: "Mode 1: encryption" + value: 0 + - name: Mode2 + description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + value: 1 + - name: Mode3 + description: "Mode 3: decryption" + value: 2 + - name: Mode4 + description: "Mode 4: key derivation then single decryption" + value: 3 +enum/RDERR: + bit_size: 1 + variants: + - name: NoError + description: Read error not detected + value: 0 + - name: Error + description: Read error detected + value: 1 +enum/WRERR: + bit_size: 1 + variants: + - name: NoError + description: Write error not detected + value: 0 + - name: Error + description: Write error detected + value: 1 diff --git a/data/registers/aes_v2.yaml b/data/registers/aes_v2.yaml new file mode 100644 index 0000000..ec689a3 --- /dev/null +++ b/data/registers/aes_v2.yaml @@ -0,0 +1,332 @@ +--- +block/AES: + description: Advanced Encryption Standard + items: + - name: CR + description: AES control register + byte_offset: 0 + fieldset: CR + - name: SR + description: AES status register + byte_offset: 4 + fieldset: SR + - name: DINR + description: "AES data input register " + byte_offset: 8 + fieldset: DINR + - name: DOUTR + description: "AES data output register " + byte_offset: 12 + fieldset: DOUTR + - name: KEYR0 + description: AES key register 0 + byte_offset: 16 + fieldset: KEYR0 + - name: KEYR1 + description: AES key register 1 + byte_offset: 20 + fieldset: KEYR1 + - name: KEYR2 + description: AES key register 2 + byte_offset: 24 + fieldset: KEYR2 + - name: KEYR3 + description: AES key register 3 + byte_offset: 28 + fieldset: KEYR3 + - name: IVR0 + description: AES initialization vector register 0 + byte_offset: 32 + fieldset: IVR0 + - name: IVR1 + description: AES initialization vector register 1 + byte_offset: 36 + fieldset: IVR1 + - name: IVR2 + description: AES initialization vector register 2 + byte_offset: 40 + fieldset: IVR2 + - name: IVR3 + description: AES initialization vector register 3 + byte_offset: 44 + fieldset: IVR3 + - name: KEYR4 + description: AES key register 4 + byte_offset: 48 + fieldset: KEYR4 + - name: KEYR5 + description: AES key register 5 + byte_offset: 52 + fieldset: KEYR5 + - name: KEYR6 + description: AES key register 6 + byte_offset: 56 + fieldset: KEYR6 + - name: KEYR7 + description: AES key register 7 + byte_offset: 60 + fieldset: KEYR7 + - name: SUSP0R + description: "AES suspend registers " + byte_offset: 64 + fieldset: SUSP0R + - name: SUSP1R + description: "AES suspend registers " + byte_offset: 68 + fieldset: SUSP1R + - name: SUSP2R + description: "AES suspend registers " + byte_offset: 72 + fieldset: SUSP2R + - name: SUSP3R + description: "AES suspend registers " + byte_offset: 76 + fieldset: SUSP3R + - name: SUSP4R + description: "AES suspend registers " + byte_offset: 80 + fieldset: SUSP4R + - name: SUSP5R + description: "AES suspend registers " + byte_offset: 84 + fieldset: SUSP5R + - name: SUSP6R + description: "AES suspend registers " + byte_offset: 88 + fieldset: SUSP6R + - name: SUSP7R + description: "AES suspend registers " + byte_offset: 92 + fieldset: SUSP7R +fieldset/CR: + description: AES control register + fields: + - name: EN + description: "AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase." + bit_offset: 0 + bit_size: 1 + - name: DATATYPE + description: "Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + bit_offset: 1 + bit_size: 2 + - name: MODE + description: "AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4." + bit_offset: 3 + bit_size: 2 + - name: CHMOD1 + description: "Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + bit_offset: 5 + bit_size: 2 + - name: CCFC + description: "Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero." + bit_offset: 7 + bit_size: 1 + - name: ERRC + description: "Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero." + bit_offset: 8 + bit_size: 1 + - name: CCFIE + description: "CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:" + bit_offset: 9 + bit_size: 1 + - name: ERRIE + description: "Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:" + bit_offset: 10 + bit_size: 1 + - name: DMAINEN + description: "DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended." + bit_offset: 11 + bit_size: 1 + - name: DMAOUTEN + description: "DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended." + bit_offset: 12 + bit_size: 1 + - name: GCMPH + description: "GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield)." + bit_offset: 13 + bit_size: 2 + - name: CHMOD2 + description: "Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + bit_offset: 16 + bit_size: 1 + - name: KEYSIZE + description: "Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + bit_offset: 18 + bit_size: 1 + - name: NPBLB + description: "Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ..." + bit_offset: 20 + bit_size: 4 +fieldset/DINR: + description: "AES data input register " + fields: + - name: DIN + description: "Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the AES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext The data swap operation is described in page 499." + bit_offset: 0 + bit_size: 32 +fieldset/DOUTR: + description: "AES data output register " + fields: + - name: DOUT + description: "Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext The data swap operation is described in page 499." + bit_offset: 0 + bit_size: 32 +fieldset/IVR0: + description: AES initialization vector register 0 + fields: + - name: IVI + description: "Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled" + bit_offset: 0 + bit_size: 32 +fieldset/IVR1: + description: AES initialization vector register 1 + fields: + - name: IVI + description: "Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/IVR2: + description: AES initialization vector register 2 + fields: + - name: IVI + description: "Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/IVR3: + description: AES initialization vector register 3 + fields: + - name: IVI + description: "Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR0: + description: AES key register 0 + fields: + - name: KEY + description: "Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key. Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR1: + description: AES key register 1 + fields: + - name: KEY + description: "Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR2: + description: AES key register 2 + fields: + - name: KEY + description: "Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR3: + description: AES key register 3 + fields: + - name: KEY + description: "Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR4: + description: AES key register 4 + fields: + - name: KEY + description: "Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR5: + description: AES key register 5 + fields: + - name: KEY + description: "Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR6: + description: AES key register 6 + fields: + - name: KEY + description: "Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/KEYR7: + description: AES key register 7 + fields: + - name: KEY + description: "Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: AES status register + fields: + - name: CCF + description: "Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1." + bit_offset: 0 + bit_size: 1 + - name: RDERR + description: "Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero." + bit_offset: 1 + bit_size: 1 + - name: WRERR + description: "Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored." + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: "Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process." + bit_offset: 3 + bit_size: 1 +fieldset/SUSP0R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP1R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP2R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP3R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP4R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP5R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP6R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 +fieldset/SUSP7R: + description: "AES suspend registers " + fields: + - name: SUSP + description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + bit_offset: 0 + bit_size: 32 From 37a93d46270a874a1143386d6352fb55706325f7 Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 20:33:11 +0300 Subject: [PATCH 2/8] aes: make all yamls as similar as possible --- data/registers/aes_f7.yaml | 246 +++++++++++++++++++------------- data/registers/aes_g081.yaml | 266 ++++++++++++++++++++--------------- data/registers/aes_u5.yaml | 228 ++++++++++++++++-------------- data/registers/aes_v1.yaml | 201 ++++++-------------------- data/registers/aes_v2.yaml | 220 ++++++++++++++++++----------- 5 files changed, 606 insertions(+), 555 deletions(-) diff --git a/data/registers/aes_f7.yaml b/data/registers/aes_f7.yaml index 6325adf..3e20b93 100644 --- a/data/registers/aes_f7.yaml +++ b/data/registers/aes_f7.yaml @@ -1,122 +1,122 @@ --- block/AES: - description: Advanced encryption standard hardware accelerator 1 + description: Advanced encryption standard hardware accelerator items: - name: CR - description: control register + description: Control register byte_offset: 0 fieldset: CR - name: SR - description: status register + description: Status register byte_offset: 4 - access: Read fieldset: SR - name: DINR - description: data input register + description: Data input register byte_offset: 8 fieldset: DINR - name: DOUTR - description: data output register + description: Data output register byte_offset: 12 - access: Read fieldset: DOUTR - name: KEYR0 - description: key register 0 + description: Key register 0 byte_offset: 16 fieldset: KEYR0 - name: KEYR1 - description: key register 1 + description: Key register 1 byte_offset: 20 fieldset: KEYR1 - name: KEYR2 - description: key register 2 + description: Key register 2 byte_offset: 24 fieldset: KEYR2 - name: KEYR3 - description: key register 3 + description: Key register 3 byte_offset: 28 fieldset: KEYR3 - name: IVR0 - description: initialization vector register 0 + description: Initialization vector register 0 byte_offset: 32 fieldset: IVR0 - name: IVR1 - description: initialization vector register 1 + description: Initialization vector register 1 byte_offset: 36 fieldset: IVR1 - name: IVR2 - description: initialization vector register 2 + description: Initialization vector register 2 byte_offset: 40 fieldset: IVR2 - name: IVR3 - description: initialization vector register 3 + description: Initialization vector register 3 byte_offset: 44 fieldset: IVR3 - name: KEYR4 - description: key register 4 + description: Key register 4 byte_offset: 48 fieldset: KEYR4 - name: KEYR5 - description: key register 5 + description: Key register 5 byte_offset: 52 fieldset: KEYR5 - name: KEYR6 - description: key register 6 + description: Key register 6 byte_offset: 56 fieldset: KEYR6 - name: KEYR7 - description: key register 7 + description: Key register 7 byte_offset: 60 fieldset: KEYR7 - name: SUSP0R - description: AES suspend register 0 + description: Suspend register 0 byte_offset: 64 fieldset: SUSP0R - name: SUSP1R - description: AES suspend register 1 + description: Suspend register 1 byte_offset: 68 fieldset: SUSP1R - name: SUSP2R - description: AES suspend register 2 + description: Suspend register 2 byte_offset: 72 fieldset: SUSP2R - name: SUSP3R - description: AES suspend register 3 + description: Suspend register 3 byte_offset: 76 fieldset: SUSP3R - name: SUSP4R - description: AES suspend register 4 + description: Suspend register 4 byte_offset: 80 fieldset: SUSP4R - name: SUSP5R - description: AES suspend register 5 + description: Suspend register 5 byte_offset: 84 fieldset: SUSP5R - name: SUSP6R - description: AES suspend register 6 + description: Suspend register 6 byte_offset: 88 fieldset: SUSP6R - name: SUSP7R - description: AES suspend register 7 + description: Suspend register 7 byte_offset: 92 fieldset: SUSP7R fieldset/CR: - description: control register + description: Control register fields: - name: EN description: AES enable bit_offset: 0 bit_size: 1 - name: DATATYPE - description: Data type selection (for data in and data out to/from the cryptographic block) + description: Data type selection bit_offset: 1 bit_size: 2 + enum: DATATYPE - name: MODE - description: AES operating mode + description: Operating mode bit_offset: 3 bit_size: 2 + enum: MODE - name: CHMOD10 - description: AES chaining mode Bit1 Bit0 + description: Chaining mode bit1 bit0 bit_offset: 5 bit_size: 2 - name: CCFC @@ -144,11 +144,12 @@ fieldset/CR: bit_offset: 12 bit_size: 1 - name: GCMPH - description: "Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected" + description: GCM or CCM phase selection bit_offset: 13 bit_size: 2 + enum: GCMPH - name: CHMOD2 - description: AES chaining mode Bit2 + description: Chaining mode bit2 bit_offset: 16 bit_size: 1 - name: KEYSIZE @@ -156,105 +157,105 @@ fieldset/CR: bit_offset: 18 bit_size: 1 fieldset/DINR: - description: data input register + description: Data input register fields: - - name: AES_DINR - description: Data Input Register + - name: DIN + description: Input data word bit_offset: 0 bit_size: 32 fieldset/DOUTR: - description: data output register + description: Data output register fields: - - name: AES_DOUTR - description: Data output register + - name: DOUT + description: Output data word bit_offset: 0 bit_size: 32 fieldset/IVR0: - description: initialization vector register 0 + description: AES initialization vector register 0 fields: - - name: AES_IVR0 - description: "initialization vector register (LSB IVR [31:0])" + - name: IVI + description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: initialization vector register 1 + description: AES initialization vector register 1 fields: - - name: AES_IVR1 - description: "Initialization Vector Register (IVR [63:32])" + - name: IVI + description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: initialization vector register 2 + description: AES initialization vector register 2 fields: - - name: AES_IVR2 - description: "Initialization Vector Register (IVR [95:64])" + - name: IVI + description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: initialization vector register 3 + description: AES initialization vector register 3 fields: - - name: AES_IVR3 - description: "Initialization Vector Register (MSB IVR [127:96])" + - name: IVI + description: Initialization vector input, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR0: - description: key register 0 + description: Key register 0 fields: - - name: AES_KEYR0 - description: "Data Output Register (LSB key [31:0])" + - name: KEY + description: Cryptographic key, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/KEYR1: - description: key register 1 + description: Key register 1 fields: - - name: AES_KEYR1 - description: "AES key register (key [63:32])" + - name: KEY + description: Cryptographic key, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/KEYR2: - description: key register 2 + description: Key register 2 fields: - - name: AES_KEYR2 - description: "AES key register (key [95:64])" + - name: KEY + description: Cryptographic key, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/KEYR3: - description: key register 3 + description: Key register 3 fields: - - name: AES_KEYR3 - description: "AES key register (MSB key [127:96])" + - name: KEY + description: Cryptographic key, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR4: - description: key register 4 + description: Key register 4 fields: - - name: AES_KEYR4 - description: "AES key register (MSB key [159:128])" + - name: KEY + description: Cryptographic key, bits [159:128] bit_offset: 0 bit_size: 32 fieldset/KEYR5: - description: key register 5 + description: Key register 5 fields: - - name: AES_KEYR5 - description: "AES key register (MSB key [191:160])" + - name: KEY + description: Cryptographic key, bits [191:160] bit_offset: 0 bit_size: 32 fieldset/KEYR6: - description: key register 6 + description: Key register 6 fields: - - name: AES_KEYR6 - description: "AES key register (MSB key [223:192])" + - name: KEY + description: Cryptographic key, bits [223:192] bit_offset: 0 bit_size: 32 fieldset/KEYR7: - description: key register 7 + description: Key register 7 fields: - - name: AES_KEYR7 - description: "AES key register (MSB key [255:224])" + - name: KEY + description: Cryptographic key, bits [255:224] bit_offset: 0 bit_size: 32 fieldset/SR: - description: status register + description: Status register fields: - name: CCF description: Computation complete flag @@ -273,58 +274,103 @@ fieldset/SR: bit_offset: 3 bit_size: 1 fieldset/SUSP0R: - description: AES suspend register 0 + description: Suspend register 0 fields: - - name: AES_SUSP0R - description: AES suspend register 0 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP1R: - description: AES suspend register 1 + description: Suspend register 1 fields: - - name: AES_SUSP1R - description: AES suspend register 1 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP2R: - description: AES suspend register 2 + description: Suspend register 2 fields: - - name: AES_SUSP2R - description: AES suspend register 2 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP3R: - description: AES suspend register 3 + description: Suspend register 3 fields: - - name: AES_SUSP3R - description: AES suspend register 3 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP4R: - description: AES suspend register 4 + description: Suspend register 4 fields: - - name: AES_SUSP4R - description: AES suspend register 4 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP5R: - description: AES suspend register 5 + description: Suspend register 5 fields: - - name: AES_SUSP5R - description: AES suspend register 5 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP6R: - description: AES suspend register 6 + description: Suspend register 6 fields: - - name: AES_SUSP6R - description: AES suspend register 6 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP7R: - description: AES suspend register 7 + description: Suspend register 7 fields: - - name: AES_SUSP7R - description: AES suspend register 7 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: "Mode 1: encryption" + value: 0 + - name: Mode2 + description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + value: 1 + - name: Mode3 + description: "Mode 3: decryption" + value: 2 + - name: Mode4 + description: "Mode 4: key derivation then single decryption" + value: 3 diff --git a/data/registers/aes_g081.yaml b/data/registers/aes_g081.yaml index d0b8e82..5e66002 100644 --- a/data/registers/aes_g081.yaml +++ b/data/registers/aes_g081.yaml @@ -1,142 +1,138 @@ --- block/AES: - description: Advanced encryption standard hardware accelerator 1 + description: Advanced encryption standard hardware accelerator items: - name: CR - description: control register + description: Control register byte_offset: 0 fieldset: CR - name: SR - description: status register + description: Status register byte_offset: 4 - access: Read fieldset: SR - name: DINR - description: data input register + description: Data input register byte_offset: 8 fieldset: DINR - name: DOUTR - description: data output register + description: Data output register byte_offset: 12 - access: Read fieldset: DOUTR - name: KEYR0 - description: key register 0 + description: Key register 0 byte_offset: 16 fieldset: KEYR0 - name: KEYR1 - description: key register 1 + description: Key register 1 byte_offset: 20 fieldset: KEYR1 - name: KEYR2 - description: key register 2 + description: Key register 2 byte_offset: 24 fieldset: KEYR2 - name: KEYR3 - description: key register 3 + description: Key register 3 byte_offset: 28 fieldset: KEYR3 - name: IVR0 - description: initialization vector register 0 + description: Initialization vector register 0 byte_offset: 32 fieldset: IVR0 - name: IVR1 - description: initialization vector register 1 + description: Initialization vector register 1 byte_offset: 36 fieldset: IVR1 - name: IVR2 - description: initialization vector register 2 + description: Initialization vector register 2 byte_offset: 40 fieldset: IVR2 - name: IVR3 - description: initialization vector register 3 + description: Initialization vector register 3 byte_offset: 44 fieldset: IVR3 - name: KEYR4 - description: key register 4 + description: Key register 4 byte_offset: 48 fieldset: KEYR4 - name: KEYR5 - description: key register 5 + description: Key register 5 byte_offset: 52 fieldset: KEYR5 - name: KEYR6 - description: key register 6 + description: Key register 6 byte_offset: 56 fieldset: KEYR6 - name: KEYR7 - description: key register 7 + description: Key register 7 byte_offset: 60 fieldset: KEYR7 - name: SUSP0R - description: AES suspend register 0 + description: Suspend register 0 byte_offset: 64 fieldset: SUSP0R - name: SUSP1R - description: AES suspend register 1 + description: Suspend register 1 byte_offset: 68 fieldset: SUSP1R - name: SUSP2R - description: AES suspend register 2 + description: Suspend register 2 byte_offset: 72 fieldset: SUSP2R - name: SUSP3R - description: AES suspend register 3 + description: Suspend register 3 byte_offset: 76 fieldset: SUSP3R - name: SUSP4R - description: AES suspend register 4 + description: Suspend register 4 byte_offset: 80 fieldset: SUSP4R - name: SUSP5R - description: AES suspend register 5 + description: Suspend register 5 byte_offset: 84 fieldset: SUSP5R - name: SUSP6R - description: AES suspend register 6 + description: Suspend register 6 byte_offset: 88 fieldset: SUSP6R - name: SUSP7R - description: AES suspend register 7 + description: Suspend register 7 byte_offset: 92 fieldset: SUSP7R - name: HWCFR - description: AES hardware configuration register + description: Hardware configuration register byte_offset: 1008 - access: Read fieldset: HWCFR - name: VERR - description: AES version register + description: Version register byte_offset: 1012 - access: Read fieldset: VERR - name: IPIDR - description: AES identification register + description: Identification register byte_offset: 1016 - access: Read fieldset: IPIDR - name: SIDR - description: AES size ID register + description: Size ID register byte_offset: 1020 - access: Read fieldset: SIDR fieldset/CR: - description: control register + description: Control register fields: - name: EN description: AES enable bit_offset: 0 bit_size: 1 - name: DATATYPE - description: Data type selection (for data in and data out to/from the cryptographic block) + description: Data type selection bit_offset: 1 bit_size: 2 + enum: DATATYPE - name: MODE - description: AES operating mode + description: Operating mode bit_offset: 3 bit_size: 2 + enum: MODE - name: CHMOD10 - description: AES chaining mode Bit1 Bit0 + description: Chaining mode bit1 bit0 bit_offset: 5 bit_size: 2 - name: CCFC @@ -164,11 +160,12 @@ fieldset/CR: bit_offset: 12 bit_size: 1 - name: GCMPH - description: "Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected" + description: GCM or CCM phase selection bit_offset: 13 bit_size: 2 + enum: GCMPH - name: CHMOD2 - description: AES chaining mode Bit2 + description: Chaining mode bit2 bit_offset: 16 bit_size: 1 - name: KEYSIZE @@ -180,21 +177,21 @@ fieldset/CR: bit_offset: 20 bit_size: 4 fieldset/DINR: - description: data input register + description: Data input register fields: - - name: AES_DINR - description: Data Input Register + - name: DIN + description: Input data word bit_offset: 0 bit_size: 32 fieldset/DOUTR: - description: data output register + description: Data output register fields: - - name: AES_DOUTR - description: Data output register + - name: DOUT + description: Output data word bit_offset: 0 bit_size: 32 fieldset/HWCFR: - description: AES hardware configuration register + description: Hardware configuration register fields: - name: CFG1 description: HW Generic 1 @@ -213,105 +210,105 @@ fieldset/HWCFR: bit_offset: 12 bit_size: 4 fieldset/IPIDR: - description: AES identification register + description: Identification register fields: - name: ID description: Identification code bit_offset: 0 bit_size: 32 fieldset/IVR0: - description: initialization vector register 0 + description: AES initialization vector register 0 fields: - - name: AES_IVR0 - description: "initialization vector register (LSB IVR [31:0])" + - name: IVI + description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: initialization vector register 1 + description: AES initialization vector register 1 fields: - - name: AES_IVR1 - description: "Initialization Vector Register (IVR [63:32])" + - name: IVI + description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: initialization vector register 2 + description: AES initialization vector register 2 fields: - - name: AES_IVR2 - description: "Initialization Vector Register (IVR [95:64])" + - name: IVI + description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: initialization vector register 3 + description: AES initialization vector register 3 fields: - - name: AES_IVR3 - description: "Initialization Vector Register (MSB IVR [127:96])" + - name: IVI + description: Initialization vector input, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR0: - description: key register 0 + description: Key register 0 fields: - - name: AES_KEYR0 - description: "Data Output Register (LSB key [31:0])" + - name: KEY + description: Cryptographic key, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/KEYR1: - description: key register 1 + description: Key register 1 fields: - - name: AES_KEYR1 - description: "AES key register (key [63:32])" + - name: KEY + description: Cryptographic key, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/KEYR2: - description: key register 2 + description: Key register 2 fields: - - name: AES_KEYR2 - description: "AES key register (key [95:64])" + - name: KEY + description: Cryptographic key, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/KEYR3: - description: key register 3 + description: Key register 3 fields: - - name: AES_KEYR3 - description: "AES key register (MSB key [127:96])" + - name: KEY + description: Cryptographic key, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR4: - description: key register 4 + description: Key register 4 fields: - - name: AES_KEYR4 - description: "AES key register (MSB key [159:128])" + - name: KEY + description: Cryptographic key, bits [159:128] bit_offset: 0 bit_size: 32 fieldset/KEYR5: - description: key register 5 + description: Key register 5 fields: - - name: AES_KEYR5 - description: "AES key register (MSB key [191:160])" + - name: KEY + description: Cryptographic key, bits [191:160] bit_offset: 0 bit_size: 32 fieldset/KEYR6: - description: key register 6 + description: Key register 6 fields: - - name: AES_KEYR6 - description: "AES key register (MSB key [223:192])" + - name: KEY + description: Cryptographic key, bits [223:192] bit_offset: 0 bit_size: 32 fieldset/KEYR7: - description: key register 7 + description: Key register 7 fields: - - name: AES_KEYR7 - description: "AES key register (MSB key [255:224])" + - name: KEY + description: Cryptographic key, bits [255:224] bit_offset: 0 bit_size: 32 fieldset/SIDR: - description: AES size ID register + description: Size ID register fields: - name: ID description: Size Identification code bit_offset: 0 bit_size: 32 fieldset/SR: - description: status register + description: Status register fields: - name: CCF description: Computation complete flag @@ -330,63 +327,63 @@ fieldset/SR: bit_offset: 3 bit_size: 1 fieldset/SUSP0R: - description: AES suspend register 0 + description: Suspend register 0 fields: - - name: AES_SUSP0R - description: AES suspend register 0 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP1R: - description: AES suspend register 1 + description: Suspend register 1 fields: - - name: AES_SUSP1R - description: AES suspend register 1 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP2R: - description: AES suspend register 2 + description: Suspend register 2 fields: - - name: AES_SUSP2R - description: AES suspend register 2 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP3R: - description: AES suspend register 3 + description: Suspend register 3 fields: - - name: AES_SUSP3R - description: AES suspend register 3 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP4R: - description: AES suspend register 4 + description: Suspend register 4 fields: - - name: AES_SUSP4R - description: AES suspend register 4 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP5R: - description: AES suspend register 5 + description: Suspend register 5 fields: - - name: AES_SUSP5R - description: AES suspend register 5 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP6R: - description: AES suspend register 6 + description: Suspend register 6 fields: - - name: AES_SUSP6R - description: AES suspend register 6 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP7R: - description: AES suspend register 7 + description: Suspend register 7 fields: - - name: AES_SUSP7R - description: AES suspend register 7 + - name: SUSP + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/VERR: - description: AES version register + description: Version register fields: - name: MINREV description: Minor revision @@ -396,3 +393,48 @@ fieldset/VERR: description: Major revision bit_offset: 4 bit_size: 4 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: "Mode 1: encryption" + value: 0 + - name: Mode2 + description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + value: 1 + - name: Mode3 + description: "Mode 3: decryption" + value: 2 + - name: Mode4 + description: "Mode 4: key derivation then single decryption" + value: 3 diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_u5.yaml index b4366cc..2f6ef40 100644 --- a/data/registers/aes_u5.yaml +++ b/data/registers/aes_u5.yaml @@ -3,119 +3,100 @@ block/AES: description: Advanced encryption standard hardware accelerator items: - name: CR - description: control register + description: Control register byte_offset: 0 fieldset: CR - name: SR - description: status register + description: Status register byte_offset: 4 - access: Read fieldset: SR - name: DINR - description: data input register + description: Data input register byte_offset: 8 - access: Write fieldset: DINR - name: DOUTR - description: data output register + description: Data output register byte_offset: 12 - access: Read fieldset: DOUTR - name: KEYR0 - description: key register 0 + description: Key register 0 byte_offset: 16 - access: Write fieldset: KEYR0 - name: KEYR1 - description: key register 1 + description: Key register 1 byte_offset: 20 - access: Write fieldset: KEYR1 - name: KEYR2 - description: key register 2 + description: Key register 2 byte_offset: 24 - access: Write fieldset: KEYR2 - name: KEYR3 - description: key register 3 + description: Key register 3 byte_offset: 28 - access: Write fieldset: KEYR3 - name: IVR0 - description: initialization vector register 0 + description: Initialization vector register 0 byte_offset: 32 fieldset: IVR0 - name: IVR1 - description: initialization vector register 1 + description: Initialization vector register 1 byte_offset: 36 fieldset: IVR1 - name: IVR2 - description: initialization vector register 2 + description: Initialization vector register 2 byte_offset: 40 fieldset: IVR2 - name: IVR3 - description: initialization vector register 3 + description: Initialization vector register 3 byte_offset: 44 fieldset: IVR3 - name: KEYR4 - description: key register 4 + description: Key register 4 byte_offset: 48 - access: Write fieldset: KEYR4 - name: KEYR5 - description: key register 5 + description: Key register 5 byte_offset: 52 - access: Write fieldset: KEYR5 - name: KEYR6 - description: key register 6 + description: Key register 6 byte_offset: 56 - access: Write fieldset: KEYR6 - name: KEYR7 - description: key register 7 + description: Key register 7 byte_offset: 60 - access: Write fieldset: KEYR7 - name: SUSP0R - description: suspend registers + description: Suspend register 0 byte_offset: 64 - access: Write fieldset: SUSP0R - name: SUSP1R - description: suspend registers + description: Suspend register 1 byte_offset: 68 - access: Write fieldset: SUSP1R - name: SUSP2R - description: suspend registers + description: Suspend register 2 byte_offset: 72 - access: Write fieldset: SUSP2R - name: SUSP3R - description: suspend registers + description: Suspend register 3 byte_offset: 76 - access: Write fieldset: SUSP3R - name: SUSP4R - description: suspend registers + description: Suspend register 4 byte_offset: 80 - access: Write fieldset: SUSP4R - name: SUSP5R - description: suspend registers + description: Suspend register 5 byte_offset: 84 - access: Write fieldset: SUSP5R - name: SUSP6R - description: suspend registers + description: Suspend register 6 byte_offset: 88 - access: Write fieldset: SUSP6R - name: SUSP7R - description: suspend registers + description: Suspend register 7 byte_offset: 92 - access: Write fieldset: SUSP7R - name: IER description: interrupt enable register @@ -124,30 +105,30 @@ block/AES: - name: ISR description: interrupt status register byte_offset: 772 - access: Read fieldset: ISR - name: ICR description: interrupt clear register byte_offset: 776 - access: Write fieldset: ICR fieldset/CR: - description: control register + description: Control register fields: - name: EN description: AES enable bit_offset: 0 bit_size: 1 - name: DATATYPE - description: Data type selection (for data in and data out to/from the cryptographic block) + description: Data type selection bit_offset: 1 bit_size: 2 + enum: DATATYPE - name: MODE - description: AES operating mode + description: Operating mode bit_offset: 3 bit_size: 2 - - name: CHMOD - description: AES chaining mode + enum: MODE + - name: CHMOD10 + description: Chaining mode bit1 bit0 bit_offset: 5 bit_size: 2 - name: DMAINEN @@ -159,19 +140,20 @@ fieldset/CR: bit_offset: 12 bit_size: 1 - name: GCMPH - description: GCMPH + description: GCM or CCM phase selection bit_offset: 13 bit_size: 2 - - name: CHMOD_2 - description: CHMOD_2 + enum: GCMPH + - name: CHMOD2 + description: Chaining mode bit2 bit_offset: 16 bit_size: 1 - name: KEYSIZE - description: KEYSIZE + description: Key size selection bit_offset: 18 bit_size: 1 - name: NPBLB - description: NPBLB + description: Number of padding bytes in last block of payload bit_offset: 20 bit_size: 4 - name: KMOD @@ -183,14 +165,14 @@ fieldset/CR: bit_offset: 31 bit_size: 1 fieldset/DINR: - description: data input register + description: Data input register fields: - name: DIN description: Input data word bit_offset: 0 bit_size: 32 fieldset/DOUTR: - description: data output register + description: Data output register fields: - name: DOUT description: Output data word @@ -250,91 +232,91 @@ fieldset/ISR: bit_offset: 3 bit_size: 1 fieldset/IVR0: - description: initialization vector register 0 + description: AES initialization vector register 0 fields: - name: IVI - description: "Initialization vector input, bits [31:0]" + description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: initialization vector register 1 + description: AES initialization vector register 1 fields: - name: IVI - description: "Initialization vector input, bits [63:32]" + description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: initialization vector register 2 + description: AES initialization vector register 2 fields: - name: IVI - description: "Initialization vector input, bits [95:64]" + description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: initialization vector register 3 + description: AES initialization vector register 3 fields: - name: IVI - description: "Initialization vector input, bits [127:96]" + description: Initialization vector input, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR0: - description: key register 0 + description: Key register 0 fields: - name: KEY - description: "Cryptographic key, bits [31:0]" + description: Cryptographic key, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/KEYR1: - description: key register 1 + description: Key register 1 fields: - name: KEY - description: "Cryptographic key, bits [63:32]" + description: Cryptographic key, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/KEYR2: - description: key register 2 + description: Key register 2 fields: - - name: KEYR - description: "Cryptographic key, bits [95:64]" + - name: KEY + description: Cryptographic key, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/KEYR3: - description: key register 3 + description: Key register 3 fields: - - name: AES_KEYR3 - description: "Cryptographic key, bits [127:96]" + - name: KEY + description: Cryptographic key, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR4: - description: key register 4 + description: Key register 4 fields: - name: KEY - description: "Cryptographic key, bits [159:128]" + description: Cryptographic key, bits [159:128] bit_offset: 0 bit_size: 32 fieldset/KEYR5: - description: key register 5 + description: Key register 5 fields: - name: KEY - description: "Cryptographic key, bits [191:160]" + description: Cryptographic key, bits [191:160] bit_offset: 0 bit_size: 32 fieldset/KEYR6: - description: key register 6 + description: Key register 6 fields: - name: KEY - description: "Cryptographic key, bits [223:192]" + description: Cryptographic key, bits [223:192] bit_offset: 0 bit_size: 32 fieldset/KEYR7: - description: key register 7 + description: Key register 7 fields: - name: KEY - description: "Cryptographic key, bits [255:224]" + description: Cryptographic key, bits [255:224] bit_offset: 0 bit_size: 32 fieldset/SR: - description: status register + description: Status register fields: - name: CCF description: Computation complete flag @@ -349,66 +331,108 @@ fieldset/SR: bit_offset: 2 bit_size: 1 - name: BUSY - description: BUSY + description: Busy flag bit_offset: 3 bit_size: 1 - name: KEYVALID - description: Key Valid flag + description: Key valid flag bit_offset: 7 bit_size: 1 fieldset/SUSP0R: - description: suspend registers + description: Suspend register 0 fields: - - name: SUSP0 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP1R: - description: suspend registers + description: Suspend register 1 fields: - - name: SUSP1 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP2R: - description: suspend registers + description: Suspend register 2 fields: - - name: SUSP2 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP3R: - description: suspend registers + description: Suspend register 3 fields: - - name: SUSP3 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP4R: - description: suspend registers + description: Suspend register 4 fields: - - name: SUSP4 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP5R: - description: suspend registers + description: Suspend register 5 fields: - - name: SUSP5 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP6R: - description: suspend registers + description: Suspend register 6 fields: - - name: SUSP6 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP7R: - description: suspend registers + description: Suspend register 7 fields: - - name: SUSP7 + - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: "Mode 1: encryption" + value: 0 + - name: Mode2 + description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + value: 1 + - name: Mode3 + description: "Mode 3: decryption" + value: 2 diff --git a/data/registers/aes_v1.yaml b/data/registers/aes_v1.yaml index 1f2ee7e..6fbc6cc 100644 --- a/data/registers/aes_v1.yaml +++ b/data/registers/aes_v1.yaml @@ -3,232 +3,183 @@ block/AES: description: Advanced encryption standard hardware accelerator items: - name: CR - description: control register + description: Control register byte_offset: 0 fieldset: CR - name: SR - description: status register + description: Status register byte_offset: 4 - access: Read fieldset: SR - name: DINR - description: data input register + description: Data input register byte_offset: 8 fieldset: DINR - name: DOUTR - description: data output register + description: Data output register byte_offset: 12 - access: Read fieldset: DOUTR - name: KEYR0 - description: key register 0 + description: Key register 0 byte_offset: 16 fieldset: KEYR0 - name: KEYR1 - description: key register 1 + description: Key register 1 byte_offset: 20 fieldset: KEYR1 - name: KEYR2 - description: key register 2 + description: Key register 2 byte_offset: 24 fieldset: KEYR2 - name: KEYR3 - description: key register 3 + description: Key register 3 byte_offset: 28 fieldset: KEYR3 - name: IVR0 - description: initialization vector register 0 + description: Initialization vector register 0 byte_offset: 32 fieldset: IVR0 - name: IVR1 - description: initialization vector register 1 + description: Initialization vector register 1 byte_offset: 36 fieldset: IVR1 - name: IVR2 - description: initialization vector register 2 + description: Initialization vector register 2 byte_offset: 40 fieldset: IVR2 - name: IVR3 - description: initialization vector register 3 + description: Initialization vector register 3 byte_offset: 44 fieldset: IVR3 fieldset/CR: - description: control register + description: Control register fields: - name: EN description: AES enable bit_offset: 0 bit_size: 1 - enum: EN - name: DATATYPE - description: Data type selection (for data in and data out to/from the cryptographic block) + description: Data type selection bit_offset: 1 bit_size: 2 enum: DATATYPE - name: MODE - description: AES operating mode + description: Operating mode bit_offset: 3 bit_size: 2 enum: MODE - - name: CHMOD - description: AES chaining mode + - name: CHMOD10 + description: Chaining mode bit1 bit0 bit_offset: 5 bit_size: 2 - enum: CHMOD - name: CCFC description: Computation Complete Flag Clear bit_offset: 7 bit_size: 1 - enum: CCFC - name: ERRC description: Error clear bit_offset: 8 bit_size: 1 - enum: ERRC - name: CCFIE description: CCF flag interrupt enable bit_offset: 9 bit_size: 1 - enum: CCFIE - name: ERRIE description: Error interrupt enable bit_offset: 10 bit_size: 1 - enum: ERRIE - name: DMAINEN description: Enable DMA management of data input phase bit_offset: 11 bit_size: 1 - enum: DMAINEN - name: DMAOUTEN description: Enable DMA management of data output phase bit_offset: 12 bit_size: 1 - enum: DMAOUTEN fieldset/DINR: - description: data input register + description: Data input register fields: - name: DIN - description: Data Input Register. + description: Input data word bit_offset: 0 bit_size: 32 fieldset/DOUTR: - description: data output register + description: Data output register fields: - name: DOUT - description: Data output register + description: Output data word bit_offset: 0 bit_size: 32 fieldset/IVR0: - description: initialization vector register 0 + description: AES initialization vector register 0 fields: - - name: IV0 - description: "initialization vector register (LSB IVR [31:0])" + - name: IVI + description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: initialization vector register 1 + description: AES initialization vector register 1 fields: - - name: IV1 - description: "Initialization Vector Register (IVR [63:32])" + - name: IVI + description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: initialization vector register 2 + description: AES initialization vector register 2 fields: - - name: IV2 - description: "Initialization Vector Register (IVR [95:64])" + - name: IVI + description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: initialization vector register 3 + description: AES initialization vector register 3 fields: - - name: IV3 - description: "Initialization Vector Register (MSB IVR [127:96])" + - name: IVI + description: Initialization vector input, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR0: - description: key register 0 + description: Key register 0 fields: - - name: KEY0 - description: "Data Output Register (LSB key [31:0])" + - name: KEY + description: Cryptographic key, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/KEYR1: - description: key register 1 + description: Key register 1 fields: - - name: KEY1 - description: "AES key register (key [63:32])" + - name: KEY + description: Cryptographic key, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/KEYR2: - description: key register 2 + description: Key register 2 fields: - - name: KEY2 - description: "AES key register (key [95:64])" + - name: KEY + description: Cryptographic key, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/KEYR3: - description: key register 3 + description: Key register 3 fields: - - name: KEY3 - description: "AES key register (MSB key [127:96])" + - name: KEY + description: Cryptographic key, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/SR: - description: status register + description: Status register fields: - name: CCF description: Computation complete flag bit_offset: 0 bit_size: 1 - enum: CCF - name: RDERR description: Read error flag bit_offset: 1 bit_size: 1 - enum: RDERR - name: WRERR description: Write error flag bit_offset: 2 bit_size: 1 - enum: WRERR -enum/CCF: - bit_size: 1 - variants: - - name: Complete - description: Computation complete - value: 0 - - name: NotComplete - description: Computation not complete - value: 1 -enum/CCFC: - bit_size: 1 - variants: - - name: Clear - description: Clear computation complete flag - value: 1 -enum/CCFIE: - bit_size: 1 - variants: - - name: Disabled - description: Disable (mask) CCF interrupt - value: 0 - - name: Enabled - description: Enable CCF interrupt - value: 1 -enum/CHMOD: - bit_size: 2 - variants: - - name: ECB - description: Electronic codebook (ECB) - value: 0 - - name: CBC - description: Cipher-Block Chaining (CBC) - value: 1 - - name: CTR - description: Counter Mode (CTR) - value: 2 enum/DATATYPE: bit_size: 2 variants: @@ -244,48 +195,6 @@ enum/DATATYPE: - name: Bit description: Bit value: 3 -enum/DMAINEN: - bit_size: 1 - variants: - - name: Disabled - description: Disable DMA Input - value: 0 - - name: Enabled - description: Enable DMA Input - value: 1 -enum/DMAOUTEN: - bit_size: 1 - variants: - - name: Disabled - description: Disable DMA Output - value: 0 - - name: Enabled - description: Enabled DMA Output - value: 1 -enum/EN: - bit_size: 1 - variants: - - name: Disabled - description: Disable AES - value: 0 - - name: Enabled - description: Enable AES - value: 1 -enum/ERRC: - bit_size: 1 - variants: - - name: Clear - description: Clear RDERR and WRERR flags - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - name: Disabled - description: Disable (mask) error interrupt - value: 0 - - name: Enabled - description: Enable error interrupt - value: 1 enum/MODE: bit_size: 2 variants: @@ -301,21 +210,3 @@ enum/MODE: - name: Mode4 description: "Mode 4: key derivation then single decryption" value: 3 -enum/RDERR: - bit_size: 1 - variants: - - name: NoError - description: Read error not detected - value: 0 - - name: Error - description: Read error detected - value: 1 -enum/WRERR: - bit_size: 1 - variants: - - name: NoError - description: Write error not detected - value: 0 - - name: Error - description: Write error detected - value: 1 diff --git a/data/registers/aes_v2.yaml b/data/registers/aes_v2.yaml index ec689a3..1857320 100644 --- a/data/registers/aes_v2.yaml +++ b/data/registers/aes_v2.yaml @@ -1,332 +1,380 @@ --- block/AES: - description: Advanced Encryption Standard + description: Advanced encryption standard hardware accelerator items: - name: CR - description: AES control register + description: Control register byte_offset: 0 fieldset: CR - name: SR - description: AES status register + description: Status register byte_offset: 4 fieldset: SR - name: DINR - description: "AES data input register " + description: Data input register byte_offset: 8 fieldset: DINR - name: DOUTR - description: "AES data output register " + description: Data output register byte_offset: 12 fieldset: DOUTR - name: KEYR0 - description: AES key register 0 + description: Key register 0 byte_offset: 16 fieldset: KEYR0 - name: KEYR1 - description: AES key register 1 + description: Key register 1 byte_offset: 20 fieldset: KEYR1 - name: KEYR2 - description: AES key register 2 + description: Key register 2 byte_offset: 24 fieldset: KEYR2 - name: KEYR3 - description: AES key register 3 + description: Key register 3 byte_offset: 28 fieldset: KEYR3 - name: IVR0 - description: AES initialization vector register 0 + description: Initialization vector register 0 byte_offset: 32 fieldset: IVR0 - name: IVR1 - description: AES initialization vector register 1 + description: Initialization vector register 1 byte_offset: 36 fieldset: IVR1 - name: IVR2 - description: AES initialization vector register 2 + description: Initialization vector register 2 byte_offset: 40 fieldset: IVR2 - name: IVR3 - description: AES initialization vector register 3 + description: Initialization vector register 3 byte_offset: 44 fieldset: IVR3 - name: KEYR4 - description: AES key register 4 + description: Key register 4 byte_offset: 48 fieldset: KEYR4 - name: KEYR5 - description: AES key register 5 + description: Key register 5 byte_offset: 52 fieldset: KEYR5 - name: KEYR6 - description: AES key register 6 + description: Key register 6 byte_offset: 56 fieldset: KEYR6 - name: KEYR7 - description: AES key register 7 + description: Key register 7 byte_offset: 60 fieldset: KEYR7 - name: SUSP0R - description: "AES suspend registers " + description: Suspend register 0 byte_offset: 64 fieldset: SUSP0R - name: SUSP1R - description: "AES suspend registers " + description: Suspend register 1 byte_offset: 68 fieldset: SUSP1R - name: SUSP2R - description: "AES suspend registers " + description: Suspend register 2 byte_offset: 72 fieldset: SUSP2R - name: SUSP3R - description: "AES suspend registers " + description: Suspend register 3 byte_offset: 76 fieldset: SUSP3R - name: SUSP4R - description: "AES suspend registers " + description: Suspend register 4 byte_offset: 80 fieldset: SUSP4R - name: SUSP5R - description: "AES suspend registers " + description: Suspend register 5 byte_offset: 84 fieldset: SUSP5R - name: SUSP6R - description: "AES suspend registers " + description: Suspend register 6 byte_offset: 88 fieldset: SUSP6R - name: SUSP7R - description: "AES suspend registers " + description: Suspend register 7 byte_offset: 92 fieldset: SUSP7R fieldset/CR: - description: AES control register + description: Control register fields: - name: EN - description: "AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase." + description: AES enable bit_offset: 0 bit_size: 1 - name: DATATYPE - description: "Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + description: Data type selection bit_offset: 1 bit_size: 2 + enum: DATATYPE - name: MODE - description: "AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4." + description: Operating mode bit_offset: 3 bit_size: 2 - - name: CHMOD1 - description: "Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + enum: MODE + - name: CHMOD10 + description: Chaining mode bit1 bit0 bit_offset: 5 bit_size: 2 - name: CCFC - description: "Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero." + description: Computation Complete Flag Clear bit_offset: 7 bit_size: 1 - name: ERRC - description: "Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero." + description: Error clear bit_offset: 8 bit_size: 1 - name: CCFIE - description: "CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:" + description: CCF flag interrupt enable bit_offset: 9 bit_size: 1 - name: ERRIE - description: "Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:" + description: Error interrupt enable bit_offset: 10 bit_size: 1 - name: DMAINEN - description: "DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended." + description: Enable DMA management of data input phase bit_offset: 11 bit_size: 1 - name: DMAOUTEN - description: "DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended." + description: Enable DMA management of data output phase bit_offset: 12 bit_size: 1 - name: GCMPH - description: "GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield)." + description: GCM or CCM phase selection bit_offset: 13 bit_size: 2 + enum: GCMPH - name: CHMOD2 - description: "Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + description: Chaining mode bit2 bit_offset: 16 bit_size: 1 - name: KEYSIZE - description: "Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access." + description: Key size selection bit_offset: 18 bit_size: 1 - name: NPBLB - description: "Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ..." + description: Number of padding bytes in last block of payload bit_offset: 20 bit_size: 4 fieldset/DINR: - description: "AES data input register " + description: Data input register fields: - name: DIN - description: "Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the AES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext The data swap operation is described in page 499." + description: Input data word bit_offset: 0 bit_size: 32 fieldset/DOUTR: - description: "AES data output register " + description: Data output register fields: - name: DOUT - description: "Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext The data swap operation is described in page 499." + description: Output data word bit_offset: 0 bit_size: 32 fieldset/IVR0: description: AES initialization vector register 0 fields: - name: IVI - description: "Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled" + description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: description: AES initialization vector register 1 fields: - name: IVI - description: "Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield." + description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: description: AES initialization vector register 2 fields: - name: IVI - description: "Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield." + description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: description: AES initialization vector register 3 fields: - name: IVI - description: "Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield." + description: Initialization vector input, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR0: - description: AES key register 0 + description: Key register 0 fields: - name: KEY - description: "Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key. Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details." + description: Cryptographic key, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/KEYR1: - description: AES key register 1 + description: Key register 1 fields: - name: KEY - description: "Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/KEYR2: - description: AES key register 2 + description: Key register 2 fields: - name: KEY - description: "Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/KEYR3: - description: AES key register 3 + description: Key register 3 fields: - name: KEY - description: "Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [127:96] bit_offset: 0 bit_size: 32 fieldset/KEYR4: - description: AES key register 4 + description: Key register 4 fields: - name: KEY - description: "Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [159:128] bit_offset: 0 bit_size: 32 fieldset/KEYR5: - description: AES key register 5 + description: Key register 5 fields: - name: KEY - description: "Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [191:160] bit_offset: 0 bit_size: 32 fieldset/KEYR6: - description: AES key register 6 + description: Key register 6 fields: - name: KEY - description: "Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [223:192] bit_offset: 0 bit_size: 32 fieldset/KEYR7: - description: AES key register 7 + description: Key register 7 fields: - name: KEY - description: "Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield." + description: Cryptographic key, bits [255:224] bit_offset: 0 bit_size: 32 fieldset/SR: - description: AES status register + description: Status register fields: - name: CCF - description: "Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1." + description: Computation complete flag bit_offset: 0 bit_size: 1 - name: RDERR - description: "Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero." + description: Read error flag bit_offset: 1 bit_size: 1 - name: WRERR - description: "Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored." + description: Write error flag bit_offset: 2 bit_size: 1 - name: BUSY - description: "Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process." + description: Busy flag bit_offset: 3 bit_size: 1 fieldset/SUSP0R: - description: "AES suspend registers " + description: Suspend register 0 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP1R: - description: "AES suspend registers " + description: Suspend register 1 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP2R: - description: "AES suspend registers " + description: Suspend register 2 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP3R: - description: "AES suspend registers " + description: Suspend register 3 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP4R: - description: "AES suspend registers " + description: Suspend register 4 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP5R: - description: "AES suspend registers " + description: Suspend register 5 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP6R: - description: "AES suspend registers " + description: Suspend register 6 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 fieldset/SUSP7R: - description: "AES suspend registers " + description: Suspend register 7 fields: - name: SUSP - description: "AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers." + description: AES suspend bit_offset: 0 bit_size: 32 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 +enum/DATATYPE: + bit_size: 2 + variants: + - name: None + description: Word + value: 0 + - name: HalfWord + description: Half-word (16-bit) + value: 1 + - name: Byte + description: Byte (8-bit) + value: 2 + - name: Bit + description: Bit + value: 3 +enum/MODE: + bit_size: 2 + variants: + - name: Mode1 + description: "Mode 1: encryption" + value: 0 + - name: Mode2 + description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + value: 1 + - name: Mode3 + description: "Mode 3: decryption" + value: 2 + - name: Mode4 + description: "Mode 4: key derivation then single decryption" + value: 3 From 34fec9129a958a8b3240197696924bdb9e6adfad Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 20:37:08 +0300 Subject: [PATCH 3/8] aes_g081: rm unknow regs Those registers are not mentioned in RM0444 AES register map. --- data/registers/aes_g081.yaml | 60 ------------------------------------ 1 file changed, 60 deletions(-) diff --git a/data/registers/aes_g081.yaml b/data/registers/aes_g081.yaml index 5e66002..1857320 100644 --- a/data/registers/aes_g081.yaml +++ b/data/registers/aes_g081.yaml @@ -98,22 +98,6 @@ block/AES: description: Suspend register 7 byte_offset: 92 fieldset: SUSP7R - - name: HWCFR - description: Hardware configuration register - byte_offset: 1008 - fieldset: HWCFR - - name: VERR - description: Version register - byte_offset: 1012 - fieldset: VERR - - name: IPIDR - description: Identification register - byte_offset: 1016 - fieldset: IPIDR - - name: SIDR - description: Size ID register - byte_offset: 1020 - fieldset: SIDR fieldset/CR: description: Control register fields: @@ -190,32 +174,6 @@ fieldset/DOUTR: description: Output data word bit_offset: 0 bit_size: 32 -fieldset/HWCFR: - description: Hardware configuration register - fields: - - name: CFG1 - description: HW Generic 1 - bit_offset: 0 - bit_size: 4 - - name: CFG2 - description: HW Generic 2 - bit_offset: 4 - bit_size: 4 - - name: CFG3 - description: HW Generic 3 - bit_offset: 8 - bit_size: 4 - - name: CFG4 - description: HW Generic 4 - bit_offset: 12 - bit_size: 4 -fieldset/IPIDR: - description: Identification register - fields: - - name: ID - description: Identification code - bit_offset: 0 - bit_size: 32 fieldset/IVR0: description: AES initialization vector register 0 fields: @@ -300,13 +258,6 @@ fieldset/KEYR7: description: Cryptographic key, bits [255:224] bit_offset: 0 bit_size: 32 -fieldset/SIDR: - description: Size ID register - fields: - - name: ID - description: Size Identification code - bit_offset: 0 - bit_size: 32 fieldset/SR: description: Status register fields: @@ -382,17 +333,6 @@ fieldset/SUSP7R: description: AES suspend bit_offset: 0 bit_size: 32 -fieldset/VERR: - description: Version register - fields: - - name: MINREV - description: Minor revision - bit_offset: 0 - bit_size: 4 - - name: MAJREV - description: Major revision - bit_offset: 4 - bit_size: 4 enum/GCMPH: bit_size: 2 variants: From b6da305f855304795c466d93f7ddd87be8165f9f Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 20:37:56 +0300 Subject: [PATCH 4/8] rm aes_g081.yaml, it is now same as aes_v2.yaml. --- data/registers/aes_g081.yaml | 380 ----------------------------------- 1 file changed, 380 deletions(-) delete mode 100644 data/registers/aes_g081.yaml diff --git a/data/registers/aes_g081.yaml b/data/registers/aes_g081.yaml deleted file mode 100644 index 1857320..0000000 --- a/data/registers/aes_g081.yaml +++ /dev/null @@ -1,380 +0,0 @@ ---- -block/AES: - description: Advanced encryption standard hardware accelerator - items: - - name: CR - description: Control register - byte_offset: 0 - fieldset: CR - - name: SR - description: Status register - byte_offset: 4 - fieldset: SR - - name: DINR - description: Data input register - byte_offset: 8 - fieldset: DINR - - name: DOUTR - description: Data output register - byte_offset: 12 - fieldset: DOUTR - - name: KEYR0 - description: Key register 0 - byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: Key register 1 - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: Key register 2 - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: Key register 3 - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 - description: Initialization vector register 0 - byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: Initialization vector register 1 - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: Initialization vector register 2 - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: Initialization vector register 3 - byte_offset: 44 - fieldset: IVR3 - - name: KEYR4 - description: Key register 4 - byte_offset: 48 - fieldset: KEYR4 - - name: KEYR5 - description: Key register 5 - byte_offset: 52 - fieldset: KEYR5 - - name: KEYR6 - description: Key register 6 - byte_offset: 56 - fieldset: KEYR6 - - name: KEYR7 - description: Key register 7 - byte_offset: 60 - fieldset: KEYR7 - - name: SUSP0R - description: Suspend register 0 - byte_offset: 64 - fieldset: SUSP0R - - name: SUSP1R - description: Suspend register 1 - byte_offset: 68 - fieldset: SUSP1R - - name: SUSP2R - description: Suspend register 2 - byte_offset: 72 - fieldset: SUSP2R - - name: SUSP3R - description: Suspend register 3 - byte_offset: 76 - fieldset: SUSP3R - - name: SUSP4R - description: Suspend register 4 - byte_offset: 80 - fieldset: SUSP4R - - name: SUSP5R - description: Suspend register 5 - byte_offset: 84 - fieldset: SUSP5R - - name: SUSP6R - description: Suspend register 6 - byte_offset: 88 - fieldset: SUSP6R - - name: SUSP7R - description: Suspend register 7 - byte_offset: 92 - fieldset: SUSP7R -fieldset/CR: - description: Control register - fields: - - name: EN - description: AES enable - bit_offset: 0 - bit_size: 1 - - name: DATATYPE - description: Data type selection - bit_offset: 1 - bit_size: 2 - enum: DATATYPE - - name: MODE - description: Operating mode - bit_offset: 3 - bit_size: 2 - enum: MODE - - name: CHMOD10 - description: Chaining mode bit1 bit0 - bit_offset: 5 - bit_size: 2 - - name: CCFC - description: Computation Complete Flag Clear - bit_offset: 7 - bit_size: 1 - - name: ERRC - description: Error clear - bit_offset: 8 - bit_size: 1 - - name: CCFIE - description: CCF flag interrupt enable - bit_offset: 9 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable - bit_offset: 10 - bit_size: 1 - - name: DMAINEN - description: Enable DMA management of data input phase - bit_offset: 11 - bit_size: 1 - - name: DMAOUTEN - description: Enable DMA management of data output phase - bit_offset: 12 - bit_size: 1 - - name: GCMPH - description: GCM or CCM phase selection - bit_offset: 13 - bit_size: 2 - enum: GCMPH - - name: CHMOD2 - description: Chaining mode bit2 - bit_offset: 16 - bit_size: 1 - - name: KEYSIZE - description: Key size selection - bit_offset: 18 - bit_size: 1 - - name: NPBLB - description: Number of padding bytes in last block of payload - bit_offset: 20 - bit_size: 4 -fieldset/DINR: - description: Data input register - fields: - - name: DIN - description: Input data word - bit_offset: 0 - bit_size: 32 -fieldset/DOUTR: - description: Data output register - fields: - - name: DOUT - description: Output data word - bit_offset: 0 - bit_size: 32 -fieldset/IVR0: - description: AES initialization vector register 0 - fields: - - name: IVI - description: Initialization vector input, bits [31:0] - bit_offset: 0 - bit_size: 32 -fieldset/IVR1: - description: AES initialization vector register 1 - fields: - - name: IVI - description: Initialization vector input, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: AES initialization vector register 2 - fields: - - name: IVI - description: Initialization vector input, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: AES initialization vector register 3 - fields: - - name: IVI - description: Initialization vector input, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: Key register 0 - fields: - - name: KEY - description: Cryptographic key, bits [31:0] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: Key register 1 - fields: - - name: KEY - description: Cryptographic key, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: Key register 2 - fields: - - name: KEY - description: Cryptographic key, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: Key register 3 - fields: - - name: KEY - description: Cryptographic key, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR4: - description: Key register 4 - fields: - - name: KEY - description: Cryptographic key, bits [159:128] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR5: - description: Key register 5 - fields: - - name: KEY - description: Cryptographic key, bits [191:160] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR6: - description: Key register 6 - fields: - - name: KEY - description: Cryptographic key, bits [223:192] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR7: - description: Key register 7 - fields: - - name: KEY - description: Cryptographic key, bits [255:224] - bit_offset: 0 - bit_size: 32 -fieldset/SR: - description: Status register - fields: - - name: CCF - description: Computation complete flag - bit_offset: 0 - bit_size: 1 - - name: RDERR - description: Read error flag - bit_offset: 1 - bit_size: 1 - - name: WRERR - description: Write error flag - bit_offset: 2 - bit_size: 1 - - name: BUSY - description: Busy flag - bit_offset: 3 - bit_size: 1 -fieldset/SUSP0R: - description: Suspend register 0 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP1R: - description: Suspend register 1 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP2R: - description: Suspend register 2 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP3R: - description: Suspend register 3 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP4R: - description: Suspend register 4 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP5R: - description: Suspend register 5 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP6R: - description: Suspend register 6 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP7R: - description: Suspend register 7 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -enum/GCMPH: - bit_size: 2 - variants: - - name: Init phase - description: Init phase - value: 0 - - name: Header phase - description: Header phase - value: 1 - - name: Payload phase - description: Payload phase - value: 2 - - name: Final phase - description: Final phase - value: 3 -enum/DATATYPE: - bit_size: 2 - variants: - - name: None - description: Word - value: 0 - - name: HalfWord - description: Half-word (16-bit) - value: 1 - - name: Byte - description: Byte (8-bit) - value: 2 - - name: Bit - description: Bit - value: 3 -enum/MODE: - bit_size: 2 - variants: - - name: Mode1 - description: "Mode 1: encryption" - value: 0 - - name: Mode2 - description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" - value: 1 - - name: Mode3 - description: "Mode 3: decryption" - value: 2 - - name: Mode4 - description: "Mode 4: key derivation then single decryption" - value: 3 From 8d1896c4e09f542d302b101f93466be0a42f6597 Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 20:54:49 +0300 Subject: [PATCH 5/8] aes_u5.yaml: remove wrong fields --- data/registers/aes_u5.yaml | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_u5.yaml index 2f6ef40..8343ad6 100644 --- a/data/registers/aes_u5.yaml +++ b/data/registers/aes_u5.yaml @@ -157,11 +157,11 @@ fieldset/CR: bit_offset: 20 bit_size: 4 - name: KMOD - description: KMOD + description: Key mode selection bit_offset: 24 bit_size: 2 - name: IPRST - description: IPRST + description: AES peripheral software reset bit_offset: 31 bit_size: 1 fieldset/DINR: @@ -179,7 +179,7 @@ fieldset/DOUTR: bit_offset: 0 bit_size: 32 fieldset/ICR: - description: interrupt clear register + description: Interrupt clear register fields: - name: CCF description: Computation complete flag clear @@ -194,26 +194,22 @@ fieldset/ICR: bit_offset: 2 bit_size: 1 fieldset/IER: - description: interrupt enable register + description: Interrupt enable register fields: - name: CCFIE - description: Computation complete flag + description: Computation complete flag interrupt enable bit_offset: 0 bit_size: 1 - name: RWEIE - description: Read or write error interrupt flag + description: Read or write error interrupt enable bit_offset: 1 bit_size: 1 - name: KEIE - description: Key error interrupt flag + description: Key error interrupt enable bit_offset: 2 bit_size: 1 - - name: RNGEIE - description: Key error interrupt flag - bit_offset: 3 - bit_size: 1 fieldset/ISR: - description: interrupt status register + description: Interrupt status register fields: - name: CCF description: Computation complete flag @@ -227,10 +223,6 @@ fieldset/ISR: description: Key error interrupt flag bit_offset: 2 bit_size: 1 - - name: RNGEIF - description: Key error interrupt flag - bit_offset: 3 - bit_size: 1 fieldset/IVR0: description: AES initialization vector register 0 fields: From 6efff79ad8993c1971f00379b28f1701bf7b5104 Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 21:20:36 +0300 Subject: [PATCH 6/8] aes: rm AES from IVR description --- data/registers/aes_f7.yaml | 8 ++++---- data/registers/aes_u5.yaml | 8 ++++---- data/registers/aes_v1.yaml | 8 ++++---- data/registers/aes_v2.yaml | 8 ++++---- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/data/registers/aes_f7.yaml b/data/registers/aes_f7.yaml index 3e20b93..98a0012 100644 --- a/data/registers/aes_f7.yaml +++ b/data/registers/aes_f7.yaml @@ -171,28 +171,28 @@ fieldset/DOUTR: bit_offset: 0 bit_size: 32 fieldset/IVR0: - description: AES initialization vector register 0 + description: Initialization vector register 0 fields: - name: IVI description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: AES initialization vector register 1 + description: Initialization vector register 1 fields: - name: IVI description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: AES initialization vector register 2 + description: Initialization vector register 2 fields: - name: IVI description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: AES initialization vector register 3 + description: Initialization vector register 3 fields: - name: IVI description: Initialization vector input, bits [127:96] diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_u5.yaml index 8343ad6..3f0ed12 100644 --- a/data/registers/aes_u5.yaml +++ b/data/registers/aes_u5.yaml @@ -224,28 +224,28 @@ fieldset/ISR: bit_offset: 2 bit_size: 1 fieldset/IVR0: - description: AES initialization vector register 0 + description: Initialization vector register 0 fields: - name: IVI description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: AES initialization vector register 1 + description: Initialization vector register 1 fields: - name: IVI description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: AES initialization vector register 2 + description: Initialization vector register 2 fields: - name: IVI description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: AES initialization vector register 3 + description: Initialization vector register 3 fields: - name: IVI description: Initialization vector input, bits [127:96] diff --git a/data/registers/aes_v1.yaml b/data/registers/aes_v1.yaml index 6fbc6cc..de814d1 100644 --- a/data/registers/aes_v1.yaml +++ b/data/registers/aes_v1.yaml @@ -110,28 +110,28 @@ fieldset/DOUTR: bit_offset: 0 bit_size: 32 fieldset/IVR0: - description: AES initialization vector register 0 + description: Initialization vector register 0 fields: - name: IVI description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: AES initialization vector register 1 + description: Initialization vector register 1 fields: - name: IVI description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: AES initialization vector register 2 + description: Initialization vector register 2 fields: - name: IVI description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: AES initialization vector register 3 + description: Initialization vector register 3 fields: - name: IVI description: Initialization vector input, bits [127:96] diff --git a/data/registers/aes_v2.yaml b/data/registers/aes_v2.yaml index 1857320..1522d8f 100644 --- a/data/registers/aes_v2.yaml +++ b/data/registers/aes_v2.yaml @@ -175,28 +175,28 @@ fieldset/DOUTR: bit_offset: 0 bit_size: 32 fieldset/IVR0: - description: AES initialization vector register 0 + description: Initialization vector register 0 fields: - name: IVI description: Initialization vector input, bits [31:0] bit_offset: 0 bit_size: 32 fieldset/IVR1: - description: AES initialization vector register 1 + description: Initialization vector register 1 fields: - name: IVI description: Initialization vector input, bits [63:32] bit_offset: 0 bit_size: 32 fieldset/IVR2: - description: AES initialization vector register 2 + description: Initialization vector register 2 fields: - name: IVI description: Initialization vector input, bits [95:64] bit_offset: 0 bit_size: 32 fieldset/IVR3: - description: AES initialization vector register 3 + description: Initialization vector register 3 fields: - name: IVI description: Initialization vector input, bits [127:96] From ffea347a4e9ffb3827874dca9b28d62df5360b0d Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 22:59:09 +0300 Subject: [PATCH 7/8] aes: MergeFieldsets and MakeRegisterArray --- data/registers/aes_f7.yaml | 275 +++++++----------------------------- data/registers/aes_u5.yaml | 279 +++++++------------------------------ data/registers/aes_v1.yaml | 104 +++----------- data/registers/aes_v2.yaml | 275 +++++++----------------------------- 4 files changed, 180 insertions(+), 753 deletions(-) diff --git a/data/registers/aes_f7.yaml b/data/registers/aes_f7.yaml index 98a0012..b2bffb8 100644 --- a/data/registers/aes_f7.yaml +++ b/data/registers/aes_f7.yaml @@ -18,86 +18,34 @@ block/AES: description: Data output register byte_offset: 12 fieldset: DOUTR - - name: KEYR0 - description: Key register 0 + - name: KEYR + description: Key register + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: Key register 1 - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: Key register 2 - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: Key register 3 - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 - description: Initialization vector register 0 + fieldset: KEYR + - name: IVR + description: Initialization vector register + array: + len: 4 + stride: 4 byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: Initialization vector register 1 - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: Initialization vector register 2 - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: Initialization vector register 3 - byte_offset: 44 - fieldset: IVR3 - - name: KEYR4 - description: Key register 4 - byte_offset: 48 - fieldset: KEYR4 - - name: KEYR5 - description: Key register 5 - byte_offset: 52 - fieldset: KEYR5 - - name: KEYR6 - description: Key register 6 - byte_offset: 56 - fieldset: KEYR6 - - name: KEYR7 - description: Key register 7 - byte_offset: 60 - fieldset: KEYR7 - - name: SUSP0R - description: Suspend register 0 + fieldset: IVR + - name: SUSPR + description: Suspend register + array: + len: 8 + stride: 4 byte_offset: 64 - fieldset: SUSP0R - - name: SUSP1R - description: Suspend register 1 - byte_offset: 68 - fieldset: SUSP1R - - name: SUSP2R - description: Suspend register 2 - byte_offset: 72 - fieldset: SUSP2R - - name: SUSP3R - description: Suspend register 3 - byte_offset: 76 - fieldset: SUSP3R - - name: SUSP4R - description: Suspend register 4 - byte_offset: 80 - fieldset: SUSP4R - - name: SUSP5R - description: Suspend register 5 - byte_offset: 84 - fieldset: SUSP5R - - name: SUSP6R - description: Suspend register 6 - byte_offset: 88 - fieldset: SUSP6R - - name: SUSP7R - description: Suspend register 7 - byte_offset: 92 - fieldset: SUSP7R + fieldset: SUSPR fieldset/CR: description: Control register fields: @@ -170,88 +118,18 @@ fieldset/DOUTR: description: Output data word bit_offset: 0 bit_size: 32 -fieldset/IVR0: - description: Initialization vector register 0 +fieldset/IVR: + description: Initialization vector register fields: - name: IVI - description: Initialization vector input, bits [31:0] + description: Initialization vector input bit_offset: 0 bit_size: 32 -fieldset/IVR1: - description: Initialization vector register 1 - fields: - - name: IVI - description: Initialization vector input, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: Initialization vector register 2 - fields: - - name: IVI - description: Initialization vector input, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: Initialization vector register 3 - fields: - - name: IVI - description: Initialization vector input, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: Key register 0 +fieldset/KEYR: + description: Key register fields: - name: KEY - description: Cryptographic key, bits [31:0] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: Key register 1 - fields: - - name: KEY - description: Cryptographic key, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: Key register 2 - fields: - - name: KEY - description: Cryptographic key, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: Key register 3 - fields: - - name: KEY - description: Cryptographic key, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR4: - description: Key register 4 - fields: - - name: KEY - description: Cryptographic key, bits [159:128] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR5: - description: Key register 5 - fields: - - name: KEY - description: Cryptographic key, bits [191:160] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR6: - description: Key register 6 - fields: - - name: KEY - description: Cryptographic key, bits [223:192] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR7: - description: Key register 7 - fields: - - name: KEY - description: Cryptographic key, bits [255:224] + description: Cryptographic key bit_offset: 0 bit_size: 32 fieldset/SR: @@ -273,77 +151,13 @@ fieldset/SR: description: Busy flag bit_offset: 3 bit_size: 1 -fieldset/SUSP0R: - description: Suspend register 0 +fieldset/SUSPR: + description: Suspend register fields: - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 -fieldset/SUSP1R: - description: Suspend register 1 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP2R: - description: Suspend register 2 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP3R: - description: Suspend register 3 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP4R: - description: Suspend register 4 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP5R: - description: Suspend register 5 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP6R: - description: Suspend register 6 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP7R: - description: Suspend register 7 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -enum/GCMPH: - bit_size: 2 - variants: - - name: Init phase - description: Init phase - value: 0 - - name: Header phase - description: Header phase - value: 1 - - name: Payload phase - description: Payload phase - value: 2 - - name: Final phase - description: Final phase - value: 3 enum/DATATYPE: bit_size: 2 variants: @@ -359,18 +173,33 @@ enum/DATATYPE: - name: Bit description: Bit value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 enum/MODE: bit_size: 2 variants: - name: Mode1 - description: "Mode 1: encryption" + description: "Encryption" value: 0 - name: Mode2 - description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + description: "Key derivation (or key preparation for ECB/CBC decryption)" value: 1 - name: Mode3 - description: "Mode 3: decryption" + description: "Decryption" value: 2 - name: Mode4 - description: "Mode 4: key derivation then single decryption" + description: "Key derivation then single decryption" value: 3 diff --git a/data/registers/aes_u5.yaml b/data/registers/aes_u5.yaml index 3f0ed12..fc2b46f 100644 --- a/data/registers/aes_u5.yaml +++ b/data/registers/aes_u5.yaml @@ -18,86 +18,6 @@ block/AES: description: Data output register byte_offset: 12 fieldset: DOUTR - - name: KEYR0 - description: Key register 0 - byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: Key register 1 - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: Key register 2 - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: Key register 3 - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 - description: Initialization vector register 0 - byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: Initialization vector register 1 - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: Initialization vector register 2 - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: Initialization vector register 3 - byte_offset: 44 - fieldset: IVR3 - - name: KEYR4 - description: Key register 4 - byte_offset: 48 - fieldset: KEYR4 - - name: KEYR5 - description: Key register 5 - byte_offset: 52 - fieldset: KEYR5 - - name: KEYR6 - description: Key register 6 - byte_offset: 56 - fieldset: KEYR6 - - name: KEYR7 - description: Key register 7 - byte_offset: 60 - fieldset: KEYR7 - - name: SUSP0R - description: Suspend register 0 - byte_offset: 64 - fieldset: SUSP0R - - name: SUSP1R - description: Suspend register 1 - byte_offset: 68 - fieldset: SUSP1R - - name: SUSP2R - description: Suspend register 2 - byte_offset: 72 - fieldset: SUSP2R - - name: SUSP3R - description: Suspend register 3 - byte_offset: 76 - fieldset: SUSP3R - - name: SUSP4R - description: Suspend register 4 - byte_offset: 80 - fieldset: SUSP4R - - name: SUSP5R - description: Suspend register 5 - byte_offset: 84 - fieldset: SUSP5R - - name: SUSP6R - description: Suspend register 6 - byte_offset: 88 - fieldset: SUSP6R - - name: SUSP7R - description: Suspend register 7 - byte_offset: 92 - fieldset: SUSP7R - name: IER description: interrupt enable register byte_offset: 768 @@ -110,6 +30,34 @@ block/AES: description: interrupt clear register byte_offset: 776 fieldset: ICR + - name: KEYR + description: Key register + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 + byte_offset: 16 + fieldset: KEYR + - name: IVR + description: Initialization vector register + array: + len: 4 + stride: 4 + byte_offset: 32 + fieldset: IVR + - name: SUSPR + description: Suspend register + array: + len: 8 + stride: 4 + byte_offset: 64 + fieldset: SUSPR fieldset/CR: description: Control register fields: @@ -223,88 +171,18 @@ fieldset/ISR: description: Key error interrupt flag bit_offset: 2 bit_size: 1 -fieldset/IVR0: - description: Initialization vector register 0 +fieldset/IVR: + description: Initialization vector register fields: - name: IVI - description: Initialization vector input, bits [31:0] + description: Initialization vector input bit_offset: 0 bit_size: 32 -fieldset/IVR1: - description: Initialization vector register 1 - fields: - - name: IVI - description: Initialization vector input, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: Initialization vector register 2 - fields: - - name: IVI - description: Initialization vector input, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: Initialization vector register 3 - fields: - - name: IVI - description: Initialization vector input, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: Key register 0 +fieldset/KEYR: + description: Key register fields: - name: KEY - description: Cryptographic key, bits [31:0] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: Key register 1 - fields: - - name: KEY - description: Cryptographic key, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: Key register 2 - fields: - - name: KEY - description: Cryptographic key, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: Key register 3 - fields: - - name: KEY - description: Cryptographic key, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR4: - description: Key register 4 - fields: - - name: KEY - description: Cryptographic key, bits [159:128] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR5: - description: Key register 5 - fields: - - name: KEY - description: Cryptographic key, bits [191:160] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR6: - description: Key register 6 - fields: - - name: KEY - description: Cryptographic key, bits [223:192] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR7: - description: Key register 7 - fields: - - name: KEY - description: Cryptographic key, bits [255:224] + description: Cryptographic key bit_offset: 0 bit_size: 32 fieldset/SR: @@ -330,77 +208,13 @@ fieldset/SR: description: Key valid flag bit_offset: 7 bit_size: 1 -fieldset/SUSP0R: - description: Suspend register 0 +fieldset/SUSPR: + description: Suspend register fields: - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 -fieldset/SUSP1R: - description: Suspend register 1 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP2R: - description: Suspend register 2 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP3R: - description: Suspend register 3 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP4R: - description: Suspend register 4 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP5R: - description: Suspend register 5 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP6R: - description: Suspend register 6 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP7R: - description: Suspend register 7 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -enum/GCMPH: - bit_size: 2 - variants: - - name: Init phase - description: Init phase - value: 0 - - name: Header phase - description: Header phase - value: 1 - - name: Payload phase - description: Payload phase - value: 2 - - name: Final phase - description: Final phase - value: 3 enum/DATATYPE: bit_size: 2 variants: @@ -416,15 +230,30 @@ enum/DATATYPE: - name: Bit description: Bit value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 enum/MODE: bit_size: 2 variants: - name: Mode1 - description: "Mode 1: encryption" + description: "Encryption" value: 0 - name: Mode2 - description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + description: "Key derivation (or key preparation for ECB/CBC decryption)" value: 1 - name: Mode3 - description: "Mode 3: decryption" + description: "Decryption" value: 2 diff --git a/data/registers/aes_v1.yaml b/data/registers/aes_v1.yaml index de814d1..fda80c5 100644 --- a/data/registers/aes_v1.yaml +++ b/data/registers/aes_v1.yaml @@ -18,38 +18,20 @@ block/AES: description: Data output register byte_offset: 12 fieldset: DOUTR - - name: KEYR0 - description: Key register 0 + - name: KEYR + description: Key register + array: + len: 4 + stride: 4 byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: Key register 1 - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: Key register 2 - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: Key register 3 - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 - description: Initialization vector register 0 + fieldset: KEYR + - name: IVR + description: Initialization vector register + array: + len: 4 + stride: 4 byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: Initialization vector register 1 - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: Initialization vector register 2 - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: Initialization vector register 3 - byte_offset: 44 - fieldset: IVR3 + fieldset: IVR fieldset/CR: description: Control register fields: @@ -109,60 +91,18 @@ fieldset/DOUTR: description: Output data word bit_offset: 0 bit_size: 32 -fieldset/IVR0: - description: Initialization vector register 0 +fieldset/IVR: + description: Initialization vector register fields: - name: IVI - description: Initialization vector input, bits [31:0] + description: "Initialization vector input" bit_offset: 0 bit_size: 32 -fieldset/IVR1: - description: Initialization vector register 1 - fields: - - name: IVI - description: Initialization vector input, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: Initialization vector register 2 - fields: - - name: IVI - description: Initialization vector input, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: Initialization vector register 3 - fields: - - name: IVI - description: Initialization vector input, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: Key register 0 +fieldset/KEYR: + description: Key register fields: - name: KEY - description: Cryptographic key, bits [31:0] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: Key register 1 - fields: - - name: KEY - description: Cryptographic key, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: Key register 2 - fields: - - name: KEY - description: Cryptographic key, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: Key register 3 - fields: - - name: KEY - description: Cryptographic key, bits [127:96] + description: Cryptographic key bit_offset: 0 bit_size: 32 fieldset/SR: @@ -199,14 +139,14 @@ enum/MODE: bit_size: 2 variants: - name: Mode1 - description: "Mode 1: encryption" + description: "Encryption" value: 0 - name: Mode2 - description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + description: "Key derivation (or key preparation for ECB/CBC decryption)" value: 1 - name: Mode3 - description: "Mode 3: decryption" + description: "Decryption" value: 2 - name: Mode4 - description: "Mode 4: key derivation then single decryption" + description: "Key derivation then single decryption" value: 3 diff --git a/data/registers/aes_v2.yaml b/data/registers/aes_v2.yaml index 1522d8f..a9846bf 100644 --- a/data/registers/aes_v2.yaml +++ b/data/registers/aes_v2.yaml @@ -18,86 +18,34 @@ block/AES: description: Data output register byte_offset: 12 fieldset: DOUTR - - name: KEYR0 - description: Key register 0 + - name: KEYR + description: Key register + array: + offsets: + - 0 + - 4 + - 8 + - 12 + - 32 + - 36 + - 40 + - 44 byte_offset: 16 - fieldset: KEYR0 - - name: KEYR1 - description: Key register 1 - byte_offset: 20 - fieldset: KEYR1 - - name: KEYR2 - description: Key register 2 - byte_offset: 24 - fieldset: KEYR2 - - name: KEYR3 - description: Key register 3 - byte_offset: 28 - fieldset: KEYR3 - - name: IVR0 - description: Initialization vector register 0 + fieldset: KEYR + - name: IVR + description: Initialization vector register + array: + len: 4 + stride: 4 byte_offset: 32 - fieldset: IVR0 - - name: IVR1 - description: Initialization vector register 1 - byte_offset: 36 - fieldset: IVR1 - - name: IVR2 - description: Initialization vector register 2 - byte_offset: 40 - fieldset: IVR2 - - name: IVR3 - description: Initialization vector register 3 - byte_offset: 44 - fieldset: IVR3 - - name: KEYR4 - description: Key register 4 - byte_offset: 48 - fieldset: KEYR4 - - name: KEYR5 - description: Key register 5 - byte_offset: 52 - fieldset: KEYR5 - - name: KEYR6 - description: Key register 6 - byte_offset: 56 - fieldset: KEYR6 - - name: KEYR7 - description: Key register 7 - byte_offset: 60 - fieldset: KEYR7 - - name: SUSP0R - description: Suspend register 0 + fieldset: IVR + - name: SUSPR + description: Suspend register + array: + len: 8 + stride: 4 byte_offset: 64 - fieldset: SUSP0R - - name: SUSP1R - description: Suspend register 1 - byte_offset: 68 - fieldset: SUSP1R - - name: SUSP2R - description: Suspend register 2 - byte_offset: 72 - fieldset: SUSP2R - - name: SUSP3R - description: Suspend register 3 - byte_offset: 76 - fieldset: SUSP3R - - name: SUSP4R - description: Suspend register 4 - byte_offset: 80 - fieldset: SUSP4R - - name: SUSP5R - description: Suspend register 5 - byte_offset: 84 - fieldset: SUSP5R - - name: SUSP6R - description: Suspend register 6 - byte_offset: 88 - fieldset: SUSP6R - - name: SUSP7R - description: Suspend register 7 - byte_offset: 92 - fieldset: SUSP7R + fieldset: SUSPR fieldset/CR: description: Control register fields: @@ -174,88 +122,18 @@ fieldset/DOUTR: description: Output data word bit_offset: 0 bit_size: 32 -fieldset/IVR0: - description: Initialization vector register 0 +fieldset/IVR: + description: Initialization vector register fields: - name: IVI - description: Initialization vector input, bits [31:0] + description: Initialization vector input bit_offset: 0 bit_size: 32 -fieldset/IVR1: - description: Initialization vector register 1 - fields: - - name: IVI - description: Initialization vector input, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/IVR2: - description: Initialization vector register 2 - fields: - - name: IVI - description: Initialization vector input, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/IVR3: - description: Initialization vector register 3 - fields: - - name: IVI - description: Initialization vector input, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR0: - description: Key register 0 +fieldset/KEYR: + description: Key register fields: - name: KEY - description: Cryptographic key, bits [31:0] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR1: - description: Key register 1 - fields: - - name: KEY - description: Cryptographic key, bits [63:32] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR2: - description: Key register 2 - fields: - - name: KEY - description: Cryptographic key, bits [95:64] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR3: - description: Key register 3 - fields: - - name: KEY - description: Cryptographic key, bits [127:96] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR4: - description: Key register 4 - fields: - - name: KEY - description: Cryptographic key, bits [159:128] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR5: - description: Key register 5 - fields: - - name: KEY - description: Cryptographic key, bits [191:160] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR6: - description: Key register 6 - fields: - - name: KEY - description: Cryptographic key, bits [223:192] - bit_offset: 0 - bit_size: 32 -fieldset/KEYR7: - description: Key register 7 - fields: - - name: KEY - description: Cryptographic key, bits [255:224] + description: Cryptographic key bit_offset: 0 bit_size: 32 fieldset/SR: @@ -277,77 +155,13 @@ fieldset/SR: description: Busy flag bit_offset: 3 bit_size: 1 -fieldset/SUSP0R: - description: Suspend register 0 +fieldset/SUSPR: + description: Suspend register fields: - name: SUSP description: AES suspend bit_offset: 0 bit_size: 32 -fieldset/SUSP1R: - description: Suspend register 1 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP2R: - description: Suspend register 2 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP3R: - description: Suspend register 3 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP4R: - description: Suspend register 4 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP5R: - description: Suspend register 5 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP6R: - description: Suspend register 6 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -fieldset/SUSP7R: - description: Suspend register 7 - fields: - - name: SUSP - description: AES suspend - bit_offset: 0 - bit_size: 32 -enum/GCMPH: - bit_size: 2 - variants: - - name: Init phase - description: Init phase - value: 0 - - name: Header phase - description: Header phase - value: 1 - - name: Payload phase - description: Payload phase - value: 2 - - name: Final phase - description: Final phase - value: 3 enum/DATATYPE: bit_size: 2 variants: @@ -363,18 +177,33 @@ enum/DATATYPE: - name: Bit description: Bit value: 3 +enum/GCMPH: + bit_size: 2 + variants: + - name: Init phase + description: Init phase + value: 0 + - name: Header phase + description: Header phase + value: 1 + - name: Payload phase + description: Payload phase + value: 2 + - name: Final phase + description: Final phase + value: 3 enum/MODE: bit_size: 2 variants: - name: Mode1 - description: "Mode 1: encryption" + description: "Encryption" value: 0 - name: Mode2 - description: "Mode 2: key derivation (or key preparation for ECB/CBC decryption)" + description: "Key derivation (or key preparation for ECB/CBC decryption)" value: 1 - name: Mode3 - description: "Mode 3: decryption" + description: "Decryption" value: 2 - name: Mode4 - description: "Mode 4: key derivation then single decryption" + description: "Key derivation then single decryption" value: 3 From 5236cc71cea898c6ed7b1a09b906d6411e97192f Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Thu, 7 Sep 2023 23:08:54 +0300 Subject: [PATCH 8/8] chips: add AES entries to perimap --- stm32-data-gen/src/chips.rs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 07fa785..72b1292 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -142,6 +142,17 @@ impl PeriMatcher { ("STM32H7.*:RNG:.*", ("rng", "v1", "RNG")), ("STM32G0.*:RNG:.*", ("rng", "v1", "RNG")), ("STM32G4.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32F7.*:AES:.*", ("aes", "f7", "AES")), + ("STM32F4.*:AES:.*", ("aes", "v1", "AES")), + ("STM32G0.*:AES:.*", ("aes", "v2", "AES")), + ("STM32G4.*:AES:.*", ("aes", "v2", "AES")), + ("STM32L0.*:AES:.*", ("aes", "v1", "AES")), + ("STM32L1.*:AES:.*", ("aes", "v1", "AES")), + ("STM32L4.*:AES:.*", ("aes", "v1", "AES")), + ("STM32L5.*:AES:.*", ("aes", "v2", "AES")), + ("STM32U5.*:AES:.*", ("aes", "u5", "AES")), + ("STM32WL5.*:AES:.*", ("aes", "v2", "AES")), + ("STM32WLE.*:AES:.*", ("aes", "v2", "AES")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")),